arch/arm64/include/asm/kvm_arm.h

   1 /*
   2  * Copyright (C) 2012,2013 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __ARM64_KVM_ARM_H__
  19 #define __ARM64_KVM_ARM_H__
  20
  21 #include <asm/types.h>
  22
  23 /* Hyp Configuration Register (HCR) bits */
  24 #define HCR_ID          (UL(1) << 33)
  25 #define HCR_CD          (UL(1) << 32)
  26 #define HCR_RW_SHIFT    31
  27 #define HCR_RW          (UL(1) << HCR_RW_SHIFT)
  28 #define HCR_TRVM        (UL(1) << 30)
  29 #define HCR_HCD         (UL(1) << 29)
  30 #define HCR_TDZ         (UL(1) << 28)
  31 #define HCR_TGE         (UL(1) << 27)
  32 #define HCR_TVM         (UL(1) << 26)
  33 #define HCR_TTLB        (UL(1) << 25)
  34 #define HCR_TPU         (UL(1) << 24)
  35 #define HCR_TPC         (UL(1) << 23)
  36 #define HCR_TSW         (UL(1) << 22)
  37 #define HCR_TAC         (UL(1) << 21)
  38 #define HCR_TIDCP       (UL(1) << 20)
  39 #define HCR_TSC         (UL(1) << 19)
  40 #define HCR_TID3        (UL(1) << 18)
  41 #define HCR_TID2        (UL(1) << 17)
  42 #define HCR_TID1        (UL(1) << 16)
  43 #define HCR_TID0        (UL(1) << 15)
  44 #define HCR_TWE         (UL(1) << 14)
  45 #define HCR_TWI         (UL(1) << 13)
  46 #define HCR_DC          (UL(1) << 12)
  47 #define HCR_BSU         (3 << 10)
  48 #define HCR_BSU_IS      (UL(1) << 10)
  49 #define HCR_FB          (UL(1) << 9)
  50 #define HCR_VA          (UL(1) << 8)
  51 #define HCR_VI          (UL(1) << 7)
  52 #define HCR_VF          (UL(1) << 6)
  53 #define HCR_AMO         (UL(1) << 5)
  54 #define HCR_IMO         (UL(1) << 4)
  55 #define HCR_FMO         (UL(1) << 3)
  56 #define HCR_PTW         (UL(1) << 2)
  57 #define HCR_SWIO        (UL(1) << 1)
  58 #define HCR_VM          (UL(1) << 0)
  59
  60 /*
  61  * The bits we set in HCR:
  62  * RW:          64bit by default, can be overriden for 32bit VMs
  63  * TAC:         Trap ACTLR
  64  * TSC:         Trap SMC
  65  * TVM:         Trap VM ops (until M+C set in SCTLR_EL1)
  66  * TSW:         Trap cache operations by set/way
  67  * TWE:         Trap WFE
  68  * TWI:         Trap WFI
  69  * TIDCP:       Trap L2CTLR/L2ECTLR
  70  * BSU_IS:      Upgrade barriers to the inner shareable domain
  71  * FB:          Force broadcast of all maintainance operations
  72  * AMO:         Override CPSR.A and enable signaling with VA
  73  * IMO:         Override CPSR.I and enable signaling with VI
  74  * FMO:         Override CPSR.F and enable signaling with VF
  75  * SWIO:        Turn set/way invalidates into set/way clean+invalidate
  76  */
  77 #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
  78                          HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \
  79                          HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW)
  80 #define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF)
  81 #define HCR_INT_OVERRIDE   (HCR_FMO | HCR_IMO)
  82
  83
  84 /* Hyp System Control Register (SCTLR_EL2) bits */
  85 #define SCTLR_EL2_EE    (1 << 25)
  86 #define SCTLR_EL2_WXN   (1 << 19)
  87 #define SCTLR_EL2_I     (1 << 12)
  88 #define SCTLR_EL2_SA    (1 << 3)
  89 #define SCTLR_EL2_C     (1 << 2)
  90 #define SCTLR_EL2_A     (1 << 1)
  91 #define SCTLR_EL2_M     1
  92 #define SCTLR_EL2_FLAGS (SCTLR_EL2_M | SCTLR_EL2_A | SCTLR_EL2_C |      \
  93                          SCTLR_EL2_SA | SCTLR_EL2_I)
  94
  95 /* TCR_EL2 Registers bits */
  96 #define TCR_EL2_TBI     (1 << 20)
  97 #define TCR_EL2_PS      (7 << 16)
  98 #define TCR_EL2_PS_40B  (2 << 16)
  99 #define TCR_EL2_TG0     (1 << 14)
 100 #define TCR_EL2_SH0     (3 << 12)
 101 #define TCR_EL2_ORGN0   (3 << 10)
 102 #define TCR_EL2_IRGN0   (3 << 8)
 103 #define TCR_EL2_T0SZ    0x3f
 104 #define TCR_EL2_MASK    (TCR_EL2_TG0 | TCR_EL2_SH0 | \
 105                          TCR_EL2_ORGN0 | TCR_EL2_IRGN0 | TCR_EL2_T0SZ)
 106
 107 #define TCR_EL2_FLAGS   (TCR_EL2_PS_40B)
 108
 109 /* VTCR_EL2 Registers bits */
 110 #define VTCR_EL2_PS_MASK        (7 << 16)
 111 #define VTCR_EL2_TG0_MASK       (1 << 14)
 112 #define VTCR_EL2_TG0_4K         (0 << 14)
 113 #define VTCR_EL2_TG0_64K        (1 << 14)
 114 #define VTCR_EL2_SH0_MASK       (3 << 12)
 115 #define VTCR_EL2_SH0_INNER      (3 << 12)
 116 #define VTCR_EL2_ORGN0_MASK     (3 << 10)
 117 #define VTCR_EL2_ORGN0_WBWA     (1 << 10)
 118 #define VTCR_EL2_IRGN0_MASK     (3 << 8)
 119 #define VTCR_EL2_IRGN0_WBWA     (1 << 8)
 120 #define VTCR_EL2_SL0_MASK       (3 << 6)
 121 #define VTCR_EL2_SL0_LVL1       (1 << 6)
 122 #define VTCR_EL2_T0SZ_MASK      0x3f
 123 #define VTCR_EL2_T0SZ_40B       24
 124
 125 /*
 126  * We configure the Stage-2 page tables to always restrict the IPA space to be
 127  * 40 bits wide (T0SZ = 24).  Systems with a PARange smaller than 40 bits are
 128  * not known to exist and will break with this configuration.
 129  *
 130  * Note that when using 4K pages, we concatenate two first level page tables
 131  * together.
 132  *
 133  * The magic numbers used for VTTBR_X in this patch can be found in Tables
 134  * D4-23 and D4-25 in ARM DDI 0487A.b.
 135  */
 136 #ifdef CONFIG_ARM64_64K_PAGES
 137 /*
 138  * Stage2 translation configuration:
 139  * 40bits output (PS = 2)
 140  * 40bits input  (T0SZ = 24)
 141  * 64kB pages (TG0 = 1)
 142  * 2 level page tables (SL = 1)
 143  */
 144 #define VTCR_EL2_FLAGS          (VTCR_EL2_TG0_64K | VTCR_EL2_SH0_INNER | \
 145                                  VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \
 146                                  VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B)
 147 #define VTTBR_X         (38 - VTCR_EL2_T0SZ_40B)
 148 #else
 149 /*
 150  * Stage2 translation configuration:
 151  * 40bits output (PS = 2)
 152  * 40bits input  (T0SZ = 24)
 153  * 4kB pages (TG0 = 0)
 154  * 3 level page tables (SL = 1)
 155  */
 156 #define VTCR_EL2_FLAGS          (VTCR_EL2_TG0_4K | VTCR_EL2_SH0_INNER | \
 157                                  VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \
 158                                  VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B)
 159 #define VTTBR_X         (37 - VTCR_EL2_T0SZ_40B)
 160 #endif
 161
 162 #define VTTBR_BADDR_SHIFT (VTTBR_X - 1)
 163 #define VTTBR_BADDR_MASK  (((1LLU << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
 164 #define VTTBR_VMID_SHIFT  (48LLU)
 165 #define VTTBR_VMID_MASK   (0xffLLU << VTTBR_VMID_SHIFT)
 166
 167 /* Hyp System Trap Register */
 168 #define HSTR_EL2_TTEE   (1 << 16)
 169 #define HSTR_EL2_T(x)   (1 << x)
 170
 171 /* Hyp Coprocessor Trap Register */
 172 #define CPTR_EL2_TCPAC  (1 << 31)
 173 #define CPTR_EL2_TTA    (1 << 20)
 174 #define CPTR_EL2_TFP    (1 << 10)
 175
 176 /* Hyp Debug Configuration Register bits */
 177 #define MDCR_EL2_TDRA           (1 << 11)
 178 #define MDCR_EL2_TDOSA          (1 << 10)
 179 #define MDCR_EL2_TDA            (1 << 9)
 180 #define MDCR_EL2_TDE            (1 << 8)
 181 #define MDCR_EL2_HPME           (1 << 7)
 182 #define MDCR_EL2_TPM            (1 << 6)
 183 #define MDCR_EL2_TPMCR          (1 << 5)
 184 #define MDCR_EL2_HPMN_MASK      (0x1F)
 185
 186 /* Exception Syndrome Register (ESR) bits */
 187 #define ESR_EL2_EC_SHIFT        (26)
 188 #define ESR_EL2_EC              (0x3fU << ESR_EL2_EC_SHIFT)
 189 #define ESR_EL2_IL              (1U << 25)
 190 #define ESR_EL2_ISS             (ESR_EL2_IL - 1)
 191 #define ESR_EL2_ISV_SHIFT       (24)
 192 #define ESR_EL2_ISV             (1U << ESR_EL2_ISV_SHIFT)
 193 #define ESR_EL2_SAS_SHIFT       (22)
 194 #define ESR_EL2_SAS             (3U << ESR_EL2_SAS_SHIFT)
 195 #define ESR_EL2_SSE             (1 << 21)
 196 #define ESR_EL2_SRT_SHIFT       (16)
 197 #define ESR_EL2_SRT_MASK        (0x1f << ESR_EL2_SRT_SHIFT)
 198 #define ESR_EL2_SF              (1 << 15)
 199 #define ESR_EL2_AR              (1 << 14)
 200 #define ESR_EL2_EA              (1 << 9)
 201 #define ESR_EL2_CM              (1 << 8)
 202 #define ESR_EL2_S1PTW           (1 << 7)
 203 #define ESR_EL2_WNR             (1 << 6)
 204 #define ESR_EL2_FSC             (0x3f)
 205 #define ESR_EL2_FSC_TYPE        (0x3c)
 206
 207 #define ESR_EL2_CV_SHIFT        (24)
 208 #define ESR_EL2_CV              (1U << ESR_EL2_CV_SHIFT)
 209 #define ESR_EL2_COND_SHIFT      (20)
 210 #define ESR_EL2_COND            (0xfU << ESR_EL2_COND_SHIFT)
 211
 212
 213 #define FSC_FAULT       (0x04)
 214 #define FSC_PERM        (0x0c)
 215
 216 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
 217 #define HPFAR_MASK      (~0xFUL)
 218
 219 #define ESR_EL2_EC_UNKNOWN      (0x00)
 220 #define ESR_EL2_EC_WFI          (0x01)
 221 #define ESR_EL2_EC_CP15_32      (0x03)
 222 #define ESR_EL2_EC_CP15_64      (0x04)
 223 #define ESR_EL2_EC_CP14_MR      (0x05)
 224 #define ESR_EL2_EC_CP14_LS      (0x06)
 225 #define ESR_EL2_EC_FP_ASIMD     (0x07)
 226 #define ESR_EL2_EC_CP10_ID      (0x08)
 227 #define ESR_EL2_EC_CP14_64      (0x0C)
 228 #define ESR_EL2_EC_ILL_ISS      (0x0E)
 229 #define ESR_EL2_EC_SVC32        (0x11)
 230 #define ESR_EL2_EC_HVC32        (0x12)
 231 #define ESR_EL2_EC_SMC32        (0x13)
 232 #define ESR_EL2_EC_SVC64        (0x15)
 233 #define ESR_EL2_EC_HVC64        (0x16)
 234 #define ESR_EL2_EC_SMC64        (0x17)
 235 #define ESR_EL2_EC_SYS64        (0x18)
 236 #define ESR_EL2_EC_IABT         (0x20)
 237 #define ESR_EL2_EC_IABT_HYP     (0x21)
 238 #define ESR_EL2_EC_PC_ALIGN     (0x22)
 239 #define ESR_EL2_EC_DABT         (0x24)
 240 #define ESR_EL2_EC_DABT_HYP     (0x25)
 241 #define ESR_EL2_EC_SP_ALIGN     (0x26)
 242 #define ESR_EL2_EC_FP_EXC32     (0x28)
 243 #define ESR_EL2_EC_FP_EXC64     (0x2C)
 244 #define ESR_EL2_EC_SERROR       (0x2F)
 245 #define ESR_EL2_EC_BREAKPT      (0x30)
 246 #define ESR_EL2_EC_BREAKPT_HYP  (0x31)
 247 #define ESR_EL2_EC_SOFTSTP      (0x32)
 248 #define ESR_EL2_EC_SOFTSTP_HYP  (0x33)
 249 #define ESR_EL2_EC_WATCHPT      (0x34)
 250 #define ESR_EL2_EC_WATCHPT_HYP  (0x35)
 251 #define ESR_EL2_EC_BKPT32       (0x38)
 252 #define ESR_EL2_EC_VECTOR32     (0x3A)
 253 #define ESR_EL2_EC_BRK64        (0x3C)
 254
 255 #define ESR_EL2_EC_xABT_xFSR_EXTABT     0x10
 256
 257 #define ESR_EL2_EC_WFI_ISS_WFE  (1 << 0)
 258
 259 #endif /* __ARM64_KVM_ARM_H__ */