arch/arm64/include/asm/kvm_host.h

   1 /*
   2  * Copyright (C) 2012,2013 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * Derived from arch/arm/include/asm/kvm_host.h:
   6  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   7  * Author: Christoffer Dall <c.dall@virtualopensystems.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #ifndef __ARM64_KVM_HOST_H__
  23 #define __ARM64_KVM_HOST_H__
  24
  25 #include <linux/types.h>
  26 #include <linux/kvm_types.h>
  27 #include <asm/kvm.h>
  28 #include <asm/kvm_asm.h>
  29 #include <asm/kvm_mmio.h>
  30
  31 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
  32
  33 #define KVM_USER_MEM_SLOTS 32
  34 #define KVM_PRIVATE_MEM_SLOTS 4
  35 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
  36 #define KVM_HALT_POLL_NS_DEFAULT 500000
  37
  38 #include <kvm/arm_vgic.h>
  39 #include <kvm/arm_arch_timer.h>
  40 #include <kvm/arm_pmu.h>
  41
  42 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
  43
  44 #define KVM_VCPU_MAX_FEATURES 4
  45
  46 int __attribute_const__ kvm_target_cpu(void);
  47 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
  48 int kvm_arch_dev_ioctl_check_extension(long ext);
  49
  50 struct kvm_arch {
  51         /* The VMID generation used for the virt. memory system */
  52         u64    vmid_gen;
  53         u32    vmid;
  54
  55         /* 1-level 2nd stage table and lock */
  56         spinlock_t pgd_lock;
  57         pgd_t *pgd;
  58
  59         /* VTTBR value associated with above pgd and vmid */
  60         u64    vttbr;
  61
  62         /* The maximum number of vCPUs depends on the used GIC model */
  63         int max_vcpus;
  64
  65         /* Interrupt controller */
  66         struct vgic_dist        vgic;
  67
  68         /* Timer */
  69         struct arch_timer_kvm   timer;
  70 };
  71
  72 #define KVM_NR_MEM_OBJS     40
  73
  74 /*
  75  * We don't want allocation failures within the mmu code, so we preallocate
  76  * enough memory for a single page fault in a cache.
  77  */
  78 struct kvm_mmu_memory_cache {
  79         int nobjs;
  80         void *objects[KVM_NR_MEM_OBJS];
  81 };
  82
  83 struct kvm_vcpu_fault_info {
  84         u32 esr_el2;            /* Hyp Syndrom Register */
  85         u64 far_el2;            /* Hyp Fault Address Register */
  86         u64 hpfar_el2;          /* Hyp IPA Fault Address Register */
  87 };
  88
  89 /*
  90  * 0 is reserved as an invalid value.
  91  * Order should be kept in sync with the save/restore code.
  92  */
  93 enum vcpu_sysreg {
  94         __INVALID_SYSREG__,
  95         MPIDR_EL1,      /* MultiProcessor Affinity Register */
  96         CSSELR_EL1,     /* Cache Size Selection Register */
  97         SCTLR_EL1,      /* System Control Register */
  98         ACTLR_EL1,      /* Auxiliary Control Register */
  99         CPACR_EL1,      /* Coprocessor Access Control */
 100         TTBR0_EL1,      /* Translation Table Base Register 0 */
 101         TTBR1_EL1,      /* Translation Table Base Register 1 */
 102         TCR_EL1,        /* Translation Control Register */
 103         ESR_EL1,        /* Exception Syndrome Register */
 104         AFSR0_EL1,      /* Auxiliary Fault Status Register 0 */
 105         AFSR1_EL1,      /* Auxiliary Fault Status Register 1 */
 106         FAR_EL1,        /* Fault Address Register */
 107         MAIR_EL1,       /* Memory Attribute Indirection Register */
 108         VBAR_EL1,       /* Vector Base Address Register */
 109         CONTEXTIDR_EL1, /* Context ID Register */
 110         TPIDR_EL0,      /* Thread ID, User R/W */
 111         TPIDRRO_EL0,    /* Thread ID, User R/O */
 112         TPIDR_EL1,      /* Thread ID, Privileged */
 113         AMAIR_EL1,      /* Aux Memory Attribute Indirection Register */
 114         CNTKCTL_EL1,    /* Timer Control Register (EL1) */
 115         PAR_EL1,        /* Physical Address Register */
 116         MDSCR_EL1,      /* Monitor Debug System Control Register */
 117         MDCCINT_EL1,    /* Monitor Debug Comms Channel Interrupt Enable Reg */
 118
 119         /* Performance Monitors Registers */
 120         PMCR_EL0,       /* Control Register */
 121         PMSELR_EL0,     /* Event Counter Selection Register */
 122         PMEVCNTR0_EL0,  /* Event Counter Register (0-30) */
 123         PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
 124         PMCCNTR_EL0,    /* Cycle Counter Register */
 125         PMEVTYPER0_EL0, /* Event Type Register (0-30) */
 126         PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
 127         PMCCFILTR_EL0,  /* Cycle Count Filter Register */
 128         PMCNTENSET_EL0, /* Count Enable Set Register */
 129         PMINTENSET_EL1, /* Interrupt Enable Set Register */
 130         PMOVSSET_EL0,   /* Overflow Flag Status Set Register */
 131         PMSWINC_EL0,    /* Software Increment Register */
 132         PMUSERENR_EL0,  /* User Enable Register */
 133
 134         /* 32bit specific registers. Keep them at the end of the range */
 135         DACR32_EL2,     /* Domain Access Control Register */
 136         IFSR32_EL2,     /* Instruction Fault Status Register */
 137         FPEXC32_EL2,    /* Floating-Point Exception Control Register */
 138         DBGVCR32_EL2,   /* Debug Vector Catch Register */
 139
 140         NR_SYS_REGS     /* Nothing after this line! */
 141 };
 142
 143 /* 32bit mapping */
 144 #define c0_MPIDR        (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
 145 #define c0_CSSELR       (CSSELR_EL1 * 2)/* Cache Size Selection Register */
 146 #define c1_SCTLR        (SCTLR_EL1 * 2) /* System Control Register */
 147 #define c1_ACTLR        (ACTLR_EL1 * 2) /* Auxiliary Control Register */
 148 #define c1_CPACR        (CPACR_EL1 * 2) /* Coprocessor Access Control */
 149 #define c2_TTBR0        (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
 150 #define c2_TTBR0_high   (c2_TTBR0 + 1)  /* TTBR0 top 32 bits */
 151 #define c2_TTBR1        (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
 152 #define c2_TTBR1_high   (c2_TTBR1 + 1)  /* TTBR1 top 32 bits */
 153 #define c2_TTBCR        (TCR_EL1 * 2)   /* Translation Table Base Control R. */
 154 #define c3_DACR         (DACR32_EL2 * 2)/* Domain Access Control Register */
 155 #define c5_DFSR         (ESR_EL1 * 2)   /* Data Fault Status Register */
 156 #define c5_IFSR         (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
 157 #define c5_ADFSR        (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
 158 #define c5_AIFSR        (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
 159 #define c6_DFAR         (FAR_EL1 * 2)   /* Data Fault Address Register */
 160 #define c6_IFAR         (c6_DFAR + 1)   /* Instruction Fault Address Register */
 161 #define c7_PAR          (PAR_EL1 * 2)   /* Physical Address Register */
 162 #define c7_PAR_high     (c7_PAR + 1)    /* PAR top 32 bits */
 163 #define c10_PRRR        (MAIR_EL1 * 2)  /* Primary Region Remap Register */
 164 #define c10_NMRR        (c10_PRRR + 1)  /* Normal Memory Remap Register */
 165 #define c12_VBAR        (VBAR_EL1 * 2)  /* Vector Base Address Register */
 166 #define c13_CID         (CONTEXTIDR_EL1 * 2)    /* Context ID Register */
 167 #define c13_TID_URW     (TPIDR_EL0 * 2) /* Thread ID, User R/W */
 168 #define c13_TID_URO     (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
 169 #define c13_TID_PRIV    (TPIDR_EL1 * 2) /* Thread ID, Privileged */
 170 #define c10_AMAIR0      (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
 171 #define c10_AMAIR1      (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
 172 #define c14_CNTKCTL     (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
 173
 174 #define cp14_DBGDSCRext (MDSCR_EL1 * 2)
 175 #define cp14_DBGBCR0    (DBGBCR0_EL1 * 2)
 176 #define cp14_DBGBVR0    (DBGBVR0_EL1 * 2)
 177 #define cp14_DBGBXVR0   (cp14_DBGBVR0 + 1)
 178 #define cp14_DBGWCR0    (DBGWCR0_EL1 * 2)
 179 #define cp14_DBGWVR0    (DBGWVR0_EL1 * 2)
 180 #define cp14_DBGDCCINT  (MDCCINT_EL1 * 2)
 181
 182 #define NR_COPRO_REGS   (NR_SYS_REGS * 2)
 183
 184 struct kvm_cpu_context {
 185         struct kvm_regs gp_regs;
 186         union {
 187                 u64 sys_regs[NR_SYS_REGS];
 188                 u32 copro[NR_COPRO_REGS];
 189         };
 190 };
 191
 192 typedef struct kvm_cpu_context kvm_cpu_context_t;
 193
 194 struct kvm_vcpu_arch {
 195         struct kvm_cpu_context ctxt;
 196
 197         /* HYP configuration */
 198         u64 hcr_el2;
 199         u32 mdcr_el2;
 200
 201         /* Exception Information */
 202         struct kvm_vcpu_fault_info fault;
 203
 204         /* Guest debug state */
 205         u64 debug_flags;
 206
 207         /*
 208          * We maintain more than a single set of debug registers to support
 209          * debugging the guest from the host and to maintain separate host and
 210          * guest state during world switches. vcpu_debug_state are the debug
 211          * registers of the vcpu as the guest sees them.  host_debug_state are
 212          * the host registers which are saved and restored during
 213          * world switches. external_debug_state contains the debug
 214          * values we want to debug the guest. This is set via the
 215          * KVM_SET_GUEST_DEBUG ioctl.
 216          *
 217          * debug_ptr points to the set of debug registers that should be loaded
 218          * onto the hardware when running the guest.
 219          */
 220         struct kvm_guest_debug_arch *debug_ptr;
 221         struct kvm_guest_debug_arch vcpu_debug_state;
 222         struct kvm_guest_debug_arch external_debug_state;
 223
 224         /* Pointer to host CPU context */
 225         kvm_cpu_context_t *host_cpu_context;
 226         struct kvm_guest_debug_arch host_debug_state;
 227
 228         /* VGIC state */
 229         struct vgic_cpu vgic_cpu;
 230         struct arch_timer_cpu timer_cpu;
 231         struct kvm_pmu pmu;
 232
 233         /*
 234          * Anything that is not used directly from assembly code goes
 235          * here.
 236          */
 237
 238         /*
 239          * Guest registers we preserve during guest debugging.
 240          *
 241          * These shadow registers are updated by the kvm_handle_sys_reg
 242          * trap handler if the guest accesses or updates them while we
 243          * are using guest debug.
 244          */
 245         struct {
 246                 u32     mdscr_el1;
 247         } guest_debug_preserved;
 248
 249         /* vcpu power-off state */
 250         bool power_off;
 251
 252         /* Don't run the guest (internal implementation need) */
 253         bool pause;
 254
 255         /* IO related fields */
 256         struct kvm_decode mmio_decode;
 257
 258         /* Interrupt related fields */
 259         u64 irq_lines;          /* IRQ and FIQ levels */
 260
 261         /* Cache some mmu pages needed inside spinlock regions */
 262         struct kvm_mmu_memory_cache mmu_page_cache;
 263
 264         /* Target CPU and feature flags */
 265         int target;
 266         DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
 267
 268         /* Detect first run of a vcpu */
 269         bool has_run_once;
 270 };
 271
 272 #define vcpu_gp_regs(v)         (&(v)->arch.ctxt.gp_regs)
 273 #define vcpu_sys_reg(v,r)       ((v)->arch.ctxt.sys_regs[(r)])
 274 /*
 275  * CP14 and CP15 live in the same array, as they are backed by the
 276  * same system registers.
 277  */
 278 #define vcpu_cp14(v,r)          ((v)->arch.ctxt.copro[(r)])
 279 #define vcpu_cp15(v,r)          ((v)->arch.ctxt.copro[(r)])
 280
 281 #ifdef CONFIG_CPU_BIG_ENDIAN
 282 #define vcpu_cp15_64_high(v,r)  vcpu_cp15((v),(r))
 283 #define vcpu_cp15_64_low(v,r)   vcpu_cp15((v),(r) + 1)
 284 #else
 285 #define vcpu_cp15_64_high(v,r)  vcpu_cp15((v),(r) + 1)
 286 #define vcpu_cp15_64_low(v,r)   vcpu_cp15((v),(r))
 287 #endif
 288
 289 struct kvm_vm_stat {
 290         u32 remote_tlb_flush;
 291 };
 292
 293 struct kvm_vcpu_stat {
 294         u32 halt_successful_poll;
 295         u32 halt_attempted_poll;
 296         u32 halt_wakeup;
 297         u32 hvc_exit_stat;
 298         u64 wfe_exit_stat;
 299         u64 wfi_exit_stat;
 300         u64 mmio_exit_user;
 301         u64 mmio_exit_kernel;
 302         u64 exits;
 303 };
 304
 305 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
 306 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
 307 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
 308 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
 309 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
 310
 311 #define KVM_ARCH_WANT_MMU_NOTIFIER
 312 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
 313 int kvm_unmap_hva_range(struct kvm *kvm,
 314                         unsigned long start, unsigned long end);
 315 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
 316 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
 317 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
 318
 319 /* We do not have shadow page tables, hence the empty hooks */
 320 static inline void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
 321                                                          unsigned long address)
 322 {
 323 }
 324
 325 struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
 326 struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void);
 327
 328 u64 __kvm_call_hyp(void *hypfn, ...);
 329 #define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__)
 330
 331 void force_vm_exit(const cpumask_t *mask);
 332 void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);
 333
 334 int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
 335                 int exception_index);
 336
 337 int kvm_perf_init(void);
 338 int kvm_perf_teardown(void);
 339
 340 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
 341
 342 static inline void __cpu_init_hyp_mode(phys_addr_t boot_pgd_ptr,
 343                                        phys_addr_t pgd_ptr,
 344                                        unsigned long hyp_stack_ptr,
 345                                        unsigned long vector_ptr)
 346 {
 347         /*
 348          * Call initialization code, and switch to the full blown
 349          * HYP code.
 350          */
 351         __kvm_call_hyp((void *)boot_pgd_ptr, pgd_ptr,
 352                        hyp_stack_ptr, vector_ptr);
 353 }
 354
 355 static inline void kvm_arch_hardware_disable(void) {}
 356 static inline void kvm_arch_hardware_unsetup(void) {}
 357 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
 358 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
 359 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
 360
 361 void kvm_arm_init_debug(void);
 362 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
 363 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
 364 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
 365 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
 366                                struct kvm_device_attr *attr);
 367 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
 368                                struct kvm_device_attr *attr);
 369 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
 370                                struct kvm_device_attr *attr);
 371
 372 static inline void __cpu_init_stage2(void)
 373 {
 374         u32 parange = kvm_call_hyp(__init_stage2_translation);
 375
 376         WARN_ONCE(parange < 40,
 377                   "PARange is %d bits, unsupported configuration!", parange);
 378 }
 379
 380 #endif /* __ARM64_KVM_HOST_H__ */