arch/arm64/include/asm/mmu_context.h

   1 /*
   2  * Based on arch/arm/include/asm/mmu_context.h
   3  *
   4  * Copyright (C) 1996 Russell King.
   5  * Copyright (C) 2012 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef __ASM_MMU_CONTEXT_H
  20 #define __ASM_MMU_CONTEXT_H
  21
  22 #define FALKOR_RESERVED_ASID    1
  23
  24 #ifndef __ASSEMBLY__
  25
  26 #include <linux/compiler.h>
  27 #include <linux/sched.h>
  28
  29 #include <asm/cacheflush.h>
  30 #include <asm/cpufeature.h>
  31 #include <asm/proc-fns.h>
  32 #include <asm-generic/mm_hooks.h>
  33 #include <asm/cputype.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/sysreg.h>
  36 #include <asm/tlbflush.h>
  37
  38 static inline void contextidr_thread_switch(struct task_struct *next)
  39 {
  40         if (!IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR))
  41                 return;
  42
  43         write_sysreg(task_pid_nr(next), contextidr_el1);
  44         isb();
  45 }
  46
  47 /*
  48  * Set TTBR0 to empty_zero_page. No translations will be possible via TTBR0.
  49  */
  50 static inline void cpu_set_reserved_ttbr0(void)
  51 {
  52         unsigned long ttbr = __pa_symbol(empty_zero_page);
  53
  54         write_sysreg(ttbr, ttbr0_el1);
  55         isb();
  56 }
  57
  58 /*
  59  * TCR.T0SZ value to use when the ID map is active. Usually equals
  60  * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in
  61  * physical memory, in which case it will be smaller.
  62  */
  63 extern u64 idmap_t0sz;
  64
  65 static inline bool __cpu_uses_extended_idmap(void)
  66 {
  67         return (!IS_ENABLED(CONFIG_ARM64_VA_BITS_48) &&
  68                 unlikely(idmap_t0sz != TCR_T0SZ(VA_BITS)));
  69 }
  70
  71 /*
  72  * Set TCR.T0SZ to its default value (based on VA_BITS)
  73  */
  74 static inline void __cpu_set_tcr_t0sz(unsigned long t0sz)
  75 {
  76         unsigned long tcr;
  77
  78         if (!__cpu_uses_extended_idmap())
  79                 return;
  80
  81         tcr = read_sysreg(tcr_el1);
  82         tcr &= ~TCR_T0SZ_MASK;
  83         tcr |= t0sz << TCR_T0SZ_OFFSET;
  84         write_sysreg(tcr, tcr_el1);
  85         isb();
  86 }
  87
  88 #define cpu_set_default_tcr_t0sz()      __cpu_set_tcr_t0sz(TCR_T0SZ(VA_BITS))
  89 #define cpu_set_idmap_tcr_t0sz()        __cpu_set_tcr_t0sz(idmap_t0sz)
  90
  91 /*
  92  * Remove the idmap from TTBR0_EL1 and install the pgd of the active mm.
  93  *
  94  * The idmap lives in the same VA range as userspace, but uses global entries
  95  * and may use a different TCR_EL1.T0SZ. To avoid issues resulting from
  96  * speculative TLB fetches, we must temporarily install the reserved page
  97  * tables while we invalidate the TLBs and set up the correct TCR_EL1.T0SZ.
  98  *
  99  * If current is a not a user task, the mm covers the TTBR1_EL1 page tables,
 100  * which should not be installed in TTBR0_EL1. In this case we can leave the
 101  * reserved page tables in place.
 102  */
 103 static inline void cpu_uninstall_idmap(void)
 104 {
 105         struct mm_struct *mm = current->active_mm;
 106
 107         cpu_set_reserved_ttbr0();
 108         local_flush_tlb_all();
 109         cpu_set_default_tcr_t0sz();
 110
 111         if (mm != &init_mm && !system_uses_ttbr0_pan())
 112                 cpu_switch_mm(mm->pgd, mm);
 113 }
 114
 115 static inline void cpu_install_idmap(void)
 116 {
 117         cpu_set_reserved_ttbr0();
 118         local_flush_tlb_all();
 119         cpu_set_idmap_tcr_t0sz();
 120
 121         cpu_switch_mm(lm_alias(idmap_pg_dir), &init_mm);
 122 }
 123
 124 /*
 125  * Atomically replaces the active TTBR1_EL1 PGD with a new VA-compatible PGD,
 126  * avoiding the possibility of conflicting TLB entries being allocated.
 127  */
 128 static inline void cpu_replace_ttbr1(pgd_t *pgd)
 129 {
 130         typedef void (ttbr_replace_func)(phys_addr_t);
 131         extern ttbr_replace_func idmap_cpu_replace_ttbr1;
 132         ttbr_replace_func *replace_phys;
 133
 134         phys_addr_t pgd_phys = virt_to_phys(pgd);
 135
 136         replace_phys = (void *)__pa_symbol(idmap_cpu_replace_ttbr1);
 137
 138         cpu_install_idmap();
 139         replace_phys(pgd_phys);
 140         cpu_uninstall_idmap();
 141 }
 142
 143 /*
 144  * It would be nice to return ASIDs back to the allocator, but unfortunately
 145  * that introduces a race with a generation rollover where we could erroneously
 146  * free an ASID allocated in a future generation. We could workaround this by
 147  * freeing the ASID from the context of the dying mm (e.g. in arch_exit_mmap),
 148  * but we'd then need to make sure that we didn't dirty any TLBs afterwards.
 149  * Setting a reserved TTBR0 or EPD0 would work, but it all gets ugly when you
 150  * take CPU migration into account.
 151  */
 152 #define destroy_context(mm)             do { } while(0)
 153 void check_and_switch_context(struct mm_struct *mm, unsigned int cpu);
 154
 155 #define init_new_context(tsk,mm)        ({ atomic64_set(&(mm)->context.id, 0); 0; })
 156
 157 /*
 158  * This is called when "tsk" is about to enter lazy TLB mode.
 159  *
 160  * mm:  describes the currently active mm context
 161  * tsk: task which is entering lazy tlb
 162  * cpu: cpu number which is entering lazy tlb
 163  *
 164  * tsk->mm will be NULL
 165  */
 166 static inline void
 167 enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 168 {
 169 }
 170
 171 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
 172 static inline void update_saved_ttbr0(struct task_struct *tsk,
 173                                       struct mm_struct *mm)
 174 {
 175         if (system_uses_ttbr0_pan()) {
 176                 BUG_ON(mm->pgd == swapper_pg_dir);
 177                 task_thread_info(tsk)->ttbr0 =
 178                         virt_to_phys(mm->pgd) | ASID(mm) << 48;
 179         }
 180 }
 181 #else
 182 static inline void update_saved_ttbr0(struct task_struct *tsk,
 183                                       struct mm_struct *mm)
 184 {
 185 }
 186 #endif
 187
 188 static inline void __switch_mm(struct mm_struct *next)
 189 {
 190         unsigned int cpu = smp_processor_id();
 191
 192         /*
 193          * init_mm.pgd does not contain any user mappings and it is always
 194          * active for kernel addresses in TTBR1. Just set the reserved TTBR0.
 195          */
 196         if (next == &init_mm) {
 197                 cpu_set_reserved_ttbr0();
 198                 return;
 199         }
 200
 201         check_and_switch_context(next, cpu);
 202 }
 203
 204 static inline void
 205 switch_mm(struct mm_struct *prev, struct mm_struct *next,
 206           struct task_struct *tsk)
 207 {
 208         if (prev != next)
 209                 __switch_mm(next);
 210
 211         /*
 212          * Update the saved TTBR0_EL1 of the scheduled-in task as the previous
 213          * value may have not been initialised yet (activate_mm caller) or the
 214          * ASID has changed since the last run (following the context switch
 215          * of another thread of the same process). Avoid setting the reserved
 216          * TTBR0_EL1 to swapper_pg_dir (init_mm; e.g. via idle_task_exit).
 217          */
 218         if (next != &init_mm)
 219                 update_saved_ttbr0(tsk, next);
 220 }
 221
 222 #define deactivate_mm(tsk,mm)   do { } while (0)
 223 #define activate_mm(prev,next)  switch_mm(prev, next, current)
 224
 225 void verify_cpu_asid_bits(void);
 226
 227 #endif /* !__ASSEMBLY__ */
 228
 229 #endif /* !__ASM_MMU_CONTEXT_H */