arch/arm64/include/asm/pgtable.h

   1 /*
   2  * Copyright (C) 2012 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __ASM_PGTABLE_H
  17 #define __ASM_PGTABLE_H
  18
  19 #include <asm/bug.h>
  20 #include <asm/proc-fns.h>
  21
  22 #include <asm/memory.h>
  23 #include <asm/pgtable-hwdef.h>
  24
  25 /*
  26  * Software defined PTE bits definition.
  27  */
  28 #define PTE_VALID               (_AT(pteval_t, 1) << 0)
  29 #define PTE_WRITE               (PTE_DBM)                /* same as DBM (51) */
  30 #define PTE_DIRTY               (_AT(pteval_t, 1) << 55)
  31 #define PTE_SPECIAL             (_AT(pteval_t, 1) << 56)
  32 #define PTE_PROT_NONE           (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
  33
  34 /*
  35  * VMALLOC and SPARSEMEM_VMEMMAP ranges.
  36  *
  37  * VMEMAP_SIZE: allows the whole VA space to be covered by a struct page array
  38  *      (rounded up to PUD_SIZE).
  39  * VMALLOC_START: beginning of the kernel VA space
  40  * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space,
  41  *      fixed mappings and modules
  42  */
  43 #define VMEMMAP_SIZE            ALIGN((1UL << (VA_BITS - PAGE_SHIFT)) * sizeof(struct page), PUD_SIZE)
  44 #define VMALLOC_START           (UL(0xffffffffffffffff) << VA_BITS)
  45 #define VMALLOC_END             (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K)
  46
  47 #define vmemmap                 ((struct page *)(VMALLOC_END + SZ_64K))
  48
  49 #define FIRST_USER_ADDRESS      0UL
  50
  51 #ifndef __ASSEMBLY__
  52
  53 #include <linux/mmdebug.h>
  54
  55 extern void __pte_error(const char *file, int line, unsigned long val);
  56 extern void __pmd_error(const char *file, int line, unsigned long val);
  57 extern void __pud_error(const char *file, int line, unsigned long val);
  58 extern void __pgd_error(const char *file, int line, unsigned long val);
  59
  60 #define PROT_DEFAULT            (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
  61 #define PROT_SECT_DEFAULT       (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
  62
  63 #define PROT_DEVICE_nGnRnE      (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
  64 #define PROT_DEVICE_nGnRE       (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
  65 #define PROT_NORMAL_NC          (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_NC))
  66 #define PROT_NORMAL_WT          (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_WT))
  67 #define PROT_NORMAL             (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL))
  68
  69 #define PROT_SECT_DEVICE_nGnRE  (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
  70 #define PROT_SECT_NORMAL        (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
  71 #define PROT_SECT_NORMAL_EXEC   (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
  72
  73 #define _PAGE_DEFAULT           (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
  74
  75 #define PAGE_KERNEL             __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE)
  76 #define PAGE_KERNEL_EXEC        __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE)
  77
  78 #define PAGE_HYP                __pgprot(_PAGE_DEFAULT | PTE_HYP)
  79 #define PAGE_HYP_DEVICE         __pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
  80
  81 #define PAGE_S2                 __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
  82 #define PAGE_S2_DEVICE          __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN)
  83
  84 #define PAGE_NONE               __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_PXN | PTE_UXN)
  85 #define PAGE_SHARED             __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
  86 #define PAGE_SHARED_EXEC        __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
  87 #define PAGE_COPY               __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
  88 #define PAGE_COPY_EXEC          __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
  89 #define PAGE_READONLY           __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
  90 #define PAGE_READONLY_EXEC      __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
  91
  92 #define __P000  PAGE_NONE
  93 #define __P001  PAGE_READONLY
  94 #define __P010  PAGE_COPY
  95 #define __P011  PAGE_COPY
  96 #define __P100  PAGE_READONLY_EXEC
  97 #define __P101  PAGE_READONLY_EXEC
  98 #define __P110  PAGE_COPY_EXEC
  99 #define __P111  PAGE_COPY_EXEC
 100
 101 #define __S000  PAGE_NONE
 102 #define __S001  PAGE_READONLY
 103 #define __S010  PAGE_SHARED
 104 #define __S011  PAGE_SHARED
 105 #define __S100  PAGE_READONLY_EXEC
 106 #define __S101  PAGE_READONLY_EXEC
 107 #define __S110  PAGE_SHARED_EXEC
 108 #define __S111  PAGE_SHARED_EXEC
 109
 110 /*
 111  * ZERO_PAGE is a global shared page that is always zero: used
 112  * for zero-mapped memory areas etc..
 113  */
 114 extern struct page *empty_zero_page;
 115 #define ZERO_PAGE(vaddr)        (empty_zero_page)
 116
 117 #define pte_ERROR(pte)          __pte_error(__FILE__, __LINE__, pte_val(pte))
 118
 119 #define pte_pfn(pte)            ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
 120
 121 #define pfn_pte(pfn,prot)       (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
 122
 123 #define pte_none(pte)           (!pte_val(pte))
 124 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
 125 #define pte_page(pte)           (pfn_to_page(pte_pfn(pte)))
 126
 127 /* Find an entry in the third-level page table. */
 128 #define pte_index(addr)         (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 129
 130 #define pte_offset_kernel(dir,addr)     (pmd_page_vaddr(*(dir)) + pte_index(addr))
 131
 132 #define pte_offset_map(dir,addr)        pte_offset_kernel((dir), (addr))
 133 #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
 134 #define pte_unmap(pte)                  do { } while (0)
 135 #define pte_unmap_nested(pte)           do { } while (0)
 136
 137 /*
 138  * The following only work if pte_present(). Undefined behaviour otherwise.
 139  */
 140 #define pte_present(pte)        (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
 141 #define pte_young(pte)          (!!(pte_val(pte) & PTE_AF))
 142 #define pte_special(pte)        (!!(pte_val(pte) & PTE_SPECIAL))
 143 #define pte_write(pte)          (!!(pte_val(pte) & PTE_WRITE))
 144 #define pte_exec(pte)           (!(pte_val(pte) & PTE_UXN))
 145
 146 #ifdef CONFIG_ARM64_HW_AFDBM
 147 #define pte_hw_dirty(pte)       (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
 148 #else
 149 #define pte_hw_dirty(pte)       (0)
 150 #endif
 151 #define pte_sw_dirty(pte)       (!!(pte_val(pte) & PTE_DIRTY))
 152 #define pte_dirty(pte)          (pte_sw_dirty(pte) || pte_hw_dirty(pte))
 153
 154 #define pte_valid(pte)          (!!(pte_val(pte) & PTE_VALID))
 155 #define pte_valid_user(pte) \
 156         ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
 157 #define pte_valid_not_user(pte) \
 158         ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID)
 159
 160 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
 161 {
 162         pte_val(pte) &= ~pgprot_val(prot);
 163         return pte;
 164 }
 165
 166 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
 167 {
 168         pte_val(pte) |= pgprot_val(prot);
 169         return pte;
 170 }
 171
 172 static inline pte_t pte_wrprotect(pte_t pte)
 173 {
 174         return clear_pte_bit(pte, __pgprot(PTE_WRITE));
 175 }
 176
 177 static inline pte_t pte_mkwrite(pte_t pte)
 178 {
 179         return set_pte_bit(pte, __pgprot(PTE_WRITE));
 180 }
 181
 182 static inline pte_t pte_mkclean(pte_t pte)
 183 {
 184         return clear_pte_bit(pte, __pgprot(PTE_DIRTY));
 185 }
 186
 187 static inline pte_t pte_mkdirty(pte_t pte)
 188 {
 189         return set_pte_bit(pte, __pgprot(PTE_DIRTY));
 190 }
 191
 192 static inline pte_t pte_mkold(pte_t pte)
 193 {
 194         return clear_pte_bit(pte, __pgprot(PTE_AF));
 195 }
 196
 197 static inline pte_t pte_mkyoung(pte_t pte)
 198 {
 199         return set_pte_bit(pte, __pgprot(PTE_AF));
 200 }
 201
 202 static inline pte_t pte_mkspecial(pte_t pte)
 203 {
 204         return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
 205 }
 206
 207 static inline void set_pte(pte_t *ptep, pte_t pte)
 208 {
 209         *ptep = pte;
 210
 211         /*
 212          * Only if the new pte is valid and kernel, otherwise TLB maintenance
 213          * or update_mmu_cache() have the necessary barriers.
 214          */
 215         if (pte_valid_not_user(pte)) {
 216                 dsb(ishst);
 217                 isb();
 218         }
 219 }
 220
 221 struct mm_struct;
 222 struct vm_area_struct;
 223
 224 extern void __sync_icache_dcache(pte_t pteval, unsigned long addr);
 225
 226 /*
 227  * PTE bits configuration in the presence of hardware Dirty Bit Management
 228  * (PTE_WRITE == PTE_DBM):
 229  *
 230  * Dirty  Writable | PTE_RDONLY  PTE_WRITE  PTE_DIRTY (sw)
 231  *   0      0      |   1           0          0
 232  *   0      1      |   1           1          0
 233  *   1      0      |   1           0          1
 234  *   1      1      |   0           1          x
 235  *
 236  * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
 237  * the page fault mechanism. Checking the dirty status of a pte becomes:
 238  *
 239  *   PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
 240  */
 241 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 242                               pte_t *ptep, pte_t pte)
 243 {
 244         if (pte_valid_user(pte)) {
 245                 if (!pte_special(pte) && pte_exec(pte))
 246                         __sync_icache_dcache(pte, addr);
 247                 if (pte_sw_dirty(pte) && pte_write(pte))
 248                         pte_val(pte) &= ~PTE_RDONLY;
 249                 else
 250                         pte_val(pte) |= PTE_RDONLY;
 251         }
 252
 253         /*
 254          * If the existing pte is valid, check for potential race with
 255          * hardware updates of the pte (ptep_set_access_flags safely changes
 256          * valid ptes without going through an invalid entry).
 257          */
 258         if (IS_ENABLED(CONFIG_DEBUG_VM) && IS_ENABLED(CONFIG_ARM64_HW_AFDBM) &&
 259             pte_valid(*ptep)) {
 260                 BUG_ON(!pte_young(pte));
 261                 BUG_ON(pte_write(*ptep) && !pte_dirty(pte));
 262         }
 263
 264         set_pte(ptep, pte);
 265 }
 266
 267 /*
 268  * Huge pte definitions.
 269  */
 270 #define pte_huge(pte)           (!(pte_val(pte) & PTE_TABLE_BIT))
 271 #define pte_mkhuge(pte)         (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
 272
 273 /*
 274  * Hugetlb definitions.
 275  */
 276 #define HUGE_MAX_HSTATE         2
 277 #define HPAGE_SHIFT             PMD_SHIFT
 278 #define HPAGE_SIZE              (_AC(1, UL) << HPAGE_SHIFT)
 279 #define HPAGE_MASK              (~(HPAGE_SIZE - 1))
 280 #define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
 281
 282 #define __HAVE_ARCH_PTE_SPECIAL
 283
 284 static inline pte_t pud_pte(pud_t pud)
 285 {
 286         return __pte(pud_val(pud));
 287 }
 288
 289 static inline pmd_t pud_pmd(pud_t pud)
 290 {
 291         return __pmd(pud_val(pud));
 292 }
 293
 294 static inline pte_t pmd_pte(pmd_t pmd)
 295 {
 296         return __pte(pmd_val(pmd));
 297 }
 298
 299 static inline pmd_t pte_pmd(pte_t pte)
 300 {
 301         return __pmd(pte_val(pte));
 302 }
 303
 304 static inline pgprot_t mk_sect_prot(pgprot_t prot)
 305 {
 306         return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT);
 307 }
 308
 309 /*
 310  * THP definitions.
 311  */
 312
 313 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 314 #define pmd_trans_huge(pmd)     (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
 315 #define pmd_trans_splitting(pmd)        pte_special(pmd_pte(pmd))
 316 #ifdef CONFIG_HAVE_RCU_TABLE_FREE
 317 #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
 318 struct vm_area_struct;
 319 void pmdp_splitting_flush(struct vm_area_struct *vma, unsigned long address,
 320                           pmd_t *pmdp);
 321 #endif /* CONFIG_HAVE_RCU_TABLE_FREE */
 322 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
 323
 324 #define pmd_dirty(pmd)          pte_dirty(pmd_pte(pmd))
 325 #define pmd_young(pmd)          pte_young(pmd_pte(pmd))
 326 #define pmd_wrprotect(pmd)      pte_pmd(pte_wrprotect(pmd_pte(pmd)))
 327 #define pmd_mksplitting(pmd)    pte_pmd(pte_mkspecial(pmd_pte(pmd)))
 328 #define pmd_mkold(pmd)          pte_pmd(pte_mkold(pmd_pte(pmd)))
 329 #define pmd_mkwrite(pmd)        pte_pmd(pte_mkwrite(pmd_pte(pmd)))
 330 #define pmd_mkdirty(pmd)        pte_pmd(pte_mkdirty(pmd_pte(pmd)))
 331 #define pmd_mkyoung(pmd)        pte_pmd(pte_mkyoung(pmd_pte(pmd)))
 332 #define pmd_mknotpresent(pmd)   (__pmd(pmd_val(pmd) & ~PMD_TYPE_MASK))
 333
 334 #define __HAVE_ARCH_PMD_WRITE
 335 #define pmd_write(pmd)          pte_write(pmd_pte(pmd))
 336
 337 #define pmd_mkhuge(pmd)         (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
 338
 339 #define pmd_pfn(pmd)            (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
 340 #define pfn_pmd(pfn,prot)       (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
 341 #define mk_pmd(page,prot)       pfn_pmd(page_to_pfn(page),prot)
 342
 343 #define pud_write(pud)          pte_write(pud_pte(pud))
 344 #define pud_pfn(pud)            (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
 345
 346 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
 347
 348 static inline int has_transparent_hugepage(void)
 349 {
 350         return 1;
 351 }
 352
 353 #define __pgprot_modify(prot,mask,bits) \
 354         __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
 355
 356 /*
 357  * Mark the prot value as uncacheable and unbufferable.
 358  */
 359 #define pgprot_noncached(prot) \
 360         __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
 361 #define pgprot_writecombine(prot) \
 362         __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
 363 #define pgprot_device(prot) \
 364         __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
 365 #define __HAVE_PHYS_MEM_ACCESS_PROT
 366 struct file;
 367 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 368                                      unsigned long size, pgprot_t vma_prot);
 369
 370 #define pmd_none(pmd)           (!pmd_val(pmd))
 371 #define pmd_present(pmd)        (pmd_val(pmd))
 372
 373 #define pmd_bad(pmd)            (!(pmd_val(pmd) & 2))
 374
 375 #define pmd_table(pmd)          ((pmd_val(pmd) & PMD_TYPE_MASK) == \
 376                                  PMD_TYPE_TABLE)
 377 #define pmd_sect(pmd)           ((pmd_val(pmd) & PMD_TYPE_MASK) == \
 378                                  PMD_TYPE_SECT)
 379
 380 #ifdef CONFIG_ARM64_64K_PAGES
 381 #define pud_sect(pud)           (0)
 382 #define pud_table(pud)          (1)
 383 #else
 384 #define pud_sect(pud)           ((pud_val(pud) & PUD_TYPE_MASK) == \
 385                                  PUD_TYPE_SECT)
 386 #define pud_table(pud)          ((pud_val(pud) & PUD_TYPE_MASK) == \
 387                                  PUD_TYPE_TABLE)
 388 #endif
 389
 390 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
 391 {
 392         *pmdp = pmd;
 393         dsb(ishst);
 394         isb();
 395 }
 396
 397 static inline void pmd_clear(pmd_t *pmdp)
 398 {
 399         set_pmd(pmdp, __pmd(0));
 400 }
 401
 402 static inline pte_t *pmd_page_vaddr(pmd_t pmd)
 403 {
 404         return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK);
 405 }
 406
 407 #define pmd_page(pmd)           pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
 408
 409 /*
 410  * Conversion functions: convert a page and protection to a page entry,
 411  * and a page entry and page directory to the page they refer to.
 412  */
 413 #define mk_pte(page,prot)       pfn_pte(page_to_pfn(page),prot)
 414
 415 #if CONFIG_PGTABLE_LEVELS > 2
 416
 417 #define pmd_ERROR(pmd)          __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
 418
 419 #define pud_none(pud)           (!pud_val(pud))
 420 #define pud_bad(pud)            (!(pud_val(pud) & 2))
 421 #define pud_present(pud)        (pud_val(pud))
 422
 423 static inline void set_pud(pud_t *pudp, pud_t pud)
 424 {
 425         *pudp = pud;
 426         dsb(ishst);
 427         isb();
 428 }
 429
 430 static inline void pud_clear(pud_t *pudp)
 431 {
 432         set_pud(pudp, __pud(0));
 433 }
 434
 435 static inline pmd_t *pud_page_vaddr(pud_t pud)
 436 {
 437         return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
 438 }
 439
 440 /* Find an entry in the second-level page table. */
 441 #define pmd_index(addr)         (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
 442
 443 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
 444 {
 445         return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
 446 }
 447
 448 #define pud_page(pud)           pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK))
 449
 450 #endif  /* CONFIG_PGTABLE_LEVELS > 2 */
 451
 452 #if CONFIG_PGTABLE_LEVELS > 3
 453
 454 #define pud_ERROR(pud)          __pud_error(__FILE__, __LINE__, pud_val(pud))
 455
 456 #define pgd_none(pgd)           (!pgd_val(pgd))
 457 #define pgd_bad(pgd)            (!(pgd_val(pgd) & 2))
 458 #define pgd_present(pgd)        (pgd_val(pgd))
 459
 460 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
 461 {
 462         *pgdp = pgd;
 463         dsb(ishst);
 464 }
 465
 466 static inline void pgd_clear(pgd_t *pgdp)
 467 {
 468         set_pgd(pgdp, __pgd(0));
 469 }
 470
 471 static inline pud_t *pgd_page_vaddr(pgd_t pgd)
 472 {
 473         return __va(pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK);
 474 }
 475
 476 /* Find an entry in the frst-level page table. */
 477 #define pud_index(addr)         (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
 478
 479 static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr)
 480 {
 481         return (pud_t *)pgd_page_vaddr(*pgd) + pud_index(addr);
 482 }
 483
 484 #define pgd_page(pgd)           pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK))
 485
 486 #endif  /* CONFIG_PGTABLE_LEVELS > 3 */
 487
 488 #define pgd_ERROR(pgd)          __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
 489
 490 /* to find an entry in a page-table-directory */
 491 #define pgd_index(addr)         (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
 492
 493 #define pgd_offset(mm, addr)    ((mm)->pgd+pgd_index(addr))
 494
 495 /* to find an entry in a kernel page-table-directory */
 496 #define pgd_offset_k(addr)      pgd_offset(&init_mm, addr)
 497
 498 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 499 {
 500         const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
 501                               PTE_PROT_NONE | PTE_VALID | PTE_WRITE;
 502         /* preserve the hardware dirty information */
 503         if (pte_hw_dirty(pte))
 504                 pte = pte_mkdirty(pte);
 505         pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
 506         return pte;
 507 }
 508
 509 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
 510 {
 511         return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
 512 }
 513
 514 #ifdef CONFIG_ARM64_HW_AFDBM
 515 /*
 516  * Atomic pte/pmd modifications.
 517  */
 518 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 519 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
 520                                             unsigned long address,
 521                                             pte_t *ptep)
 522 {
 523         pteval_t pteval;
 524         unsigned int tmp, res;
 525
 526         asm volatile("//        ptep_test_and_clear_young\n"
 527         "       prfm    pstl1strm, %2\n"
 528         "1:     ldxr    %0, %2\n"
 529         "       ubfx    %w3, %w0, %5, #1        // extract PTE_AF (young)\n"
 530         "       and     %0, %0, %4              // clear PTE_AF\n"
 531         "       stxr    %w1, %0, %2\n"
 532         "       cbnz    %w1, 1b\n"
 533         : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)), "=&r" (res)
 534         : "L" (~PTE_AF), "I" (ilog2(PTE_AF)));
 535
 536         return res;
 537 }
 538
 539 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 540 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
 541 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
 542                                             unsigned long address,
 543                                             pmd_t *pmdp)
 544 {
 545         return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
 546 }
 547 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
 548
 549 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 550 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
 551                                        unsigned long address, pte_t *ptep)
 552 {
 553         pteval_t old_pteval;
 554         unsigned int tmp;
 555
 556         asm volatile("//        ptep_get_and_clear\n"
 557         "       prfm    pstl1strm, %2\n"
 558         "1:     ldxr    %0, %2\n"
 559         "       stxr    %w1, xzr, %2\n"
 560         "       cbnz    %w1, 1b\n"
 561         : "=&r" (old_pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)));
 562
 563         return __pte(old_pteval);
 564 }
 565
 566 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 567 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR
 568 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
 569                                        unsigned long address, pmd_t *pmdp)
 570 {
 571         return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp));
 572 }
 573 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
 574
 575 /*
 576  * ptep_set_wrprotect - mark read-only while trasferring potential hardware
 577  * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
 578  */
 579 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 580 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
 581 {
 582         pteval_t pteval;
 583         unsigned long tmp;
 584
 585         asm volatile("//        ptep_set_wrprotect\n"
 586         "       prfm    pstl1strm, %2\n"
 587         "1:     ldxr    %0, %2\n"
 588         "       tst     %0, %4                  // check for hw dirty (!PTE_RDONLY)\n"
 589         "       csel    %1, %3, xzr, eq         // set PTE_DIRTY|PTE_RDONLY if dirty\n"
 590         "       orr     %0, %0, %1              // if !dirty, PTE_RDONLY is already set\n"
 591         "       and     %0, %0, %5              // clear PTE_WRITE/PTE_DBM\n"
 592         "       stxr    %w1, %0, %2\n"
 593         "       cbnz    %w1, 1b\n"
 594         : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep))
 595         : "r" (PTE_DIRTY|PTE_RDONLY), "L" (PTE_RDONLY), "L" (~PTE_WRITE)
 596         : "cc");
 597 }
 598
 599 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 600 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
 601 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
 602                                       unsigned long address, pmd_t *pmdp)
 603 {
 604         ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
 605 }
 606 #endif
 607 #endif  /* CONFIG_ARM64_HW_AFDBM */
 608
 609 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 610 extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
 611
 612 /*
 613  * Encode and decode a swap entry:
 614  *      bits 0-1:       present (must be zero)
 615  *      bits 2-7:       swap type
 616  *      bits 8-57:      swap offset
 617  */
 618 #define __SWP_TYPE_SHIFT        2
 619 #define __SWP_TYPE_BITS         6
 620 #define __SWP_OFFSET_BITS       50
 621 #define __SWP_TYPE_MASK         ((1 << __SWP_TYPE_BITS) - 1)
 622 #define __SWP_OFFSET_SHIFT      (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
 623 #define __SWP_OFFSET_MASK       ((1UL << __SWP_OFFSET_BITS) - 1)
 624
 625 #define __swp_type(x)           (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
 626 #define __swp_offset(x)         (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
 627 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
 628
 629 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
 630 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
 631
 632 /*
 633  * Ensure that there are not more swap files than can be encoded in the kernel
 634  * PTEs.
 635  */
 636 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
 637
 638 extern int kern_addr_valid(unsigned long addr);
 639
 640 #include <asm-generic/pgtable.h>
 641
 642 #define pgtable_cache_init() do { } while (0)
 643
 644 /*
 645  * On AArch64, the cache coherency is handled via the set_pte_at() function.
 646  */
 647 static inline void update_mmu_cache(struct vm_area_struct *vma,
 648                                     unsigned long addr, pte_t *ptep)
 649 {
 650         /*
 651          * set_pte() does not have a DSB for user mappings, so make sure that
 652          * the page table write is visible.
 653          */
 654         dsb(ishst);
 655 }
 656
 657 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
 658
 659 #endif /* !__ASSEMBLY__ */
 660
 661 #endif /* __ASM_PGTABLE_H */