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2 * Based on arch/arm/include/asm/ptrace.h
4 * Copyright (C) 1996-2003 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #ifndef __ASM_PTRACE_H
20 #define __ASM_PTRACE_H
22 #include <asm/cpufeature.h>
24 #include <uapi/asm/ptrace.h>
26 /* Current Exception Level values, as contained in CurrentEL */
27 #define CurrentEL_EL1 (1 << 2)
28 #define CurrentEL_EL2 (2 << 2)
31 * PMR values used to mask/unmask interrupts.
33 * GIC priority masking works as follows: if an IRQ's priority is a higher value
34 * than the value held in PMR, that IRQ is masked. Lowering the value of PMR
35 * means masking more IRQs (or at least that the same IRQs remain masked).
37 * To mask interrupts, we clear the most significant bit of PMR.
39 #define GIC_PRIO_IRQON 0xf0
40 #define GIC_PRIO_IRQOFF (GIC_PRIO_IRQON & ~0x80)
42 /* Additional SPSR bits not exposed in the UABI */
43 #define PSR_IL_BIT (1 << 20)
45 /* AArch32-specific ptrace requests */
46 #define COMPAT_PTRACE_GETREGS 12
47 #define COMPAT_PTRACE_SETREGS 13
48 #define COMPAT_PTRACE_GET_THREAD_AREA 22
49 #define COMPAT_PTRACE_SET_SYSCALL 23
50 #define COMPAT_PTRACE_GETVFPREGS 27
51 #define COMPAT_PTRACE_SETVFPREGS 28
52 #define COMPAT_PTRACE_GETHBPREGS 29
53 #define COMPAT_PTRACE_SETHBPREGS 30
55 /* SPSR_ELx bits for exceptions taken from AArch32 */
56 #define PSR_AA32_MODE_MASK 0x0000001f
57 #define PSR_AA32_MODE_USR 0x00000010
58 #define PSR_AA32_MODE_FIQ 0x00000011
59 #define PSR_AA32_MODE_IRQ 0x00000012
60 #define PSR_AA32_MODE_SVC 0x00000013
61 #define PSR_AA32_MODE_ABT 0x00000017
62 #define PSR_AA32_MODE_HYP 0x0000001a
63 #define PSR_AA32_MODE_UND 0x0000001b
64 #define PSR_AA32_MODE_SYS 0x0000001f
65 #define PSR_AA32_T_BIT 0x00000020
66 #define PSR_AA32_F_BIT 0x00000040
67 #define PSR_AA32_I_BIT 0x00000080
68 #define PSR_AA32_A_BIT 0x00000100
69 #define PSR_AA32_E_BIT 0x00000200
70 #define PSR_AA32_SSBS_BIT 0x00800000
71 #define PSR_AA32_DIT_BIT 0x01000000
72 #define PSR_AA32_Q_BIT 0x08000000
73 #define PSR_AA32_V_BIT 0x10000000
74 #define PSR_AA32_C_BIT 0x20000000
75 #define PSR_AA32_Z_BIT 0x40000000
76 #define PSR_AA32_N_BIT 0x80000000
77 #define PSR_AA32_IT_MASK 0x0600fc00 /* If-Then execution state mask */
78 #define PSR_AA32_GE_MASK 0x000f0000
80 #ifdef CONFIG_CPU_BIG_ENDIAN
81 #define PSR_AA32_ENDSTATE PSR_AA32_E_BIT
83 #define PSR_AA32_ENDSTATE 0
86 /* AArch32 CPSR bits, as seen in AArch32 */
87 #define COMPAT_PSR_DIT_BIT 0x00200000
90 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
91 * process is located in memory.
93 #define COMPAT_PT_TEXT_ADDR 0x10000
94 #define COMPAT_PT_DATA_ADDR 0x10004
95 #define COMPAT_PT_TEXT_END_ADDR 0x10008
98 * If pt_regs.syscallno == NO_SYSCALL, then the thread is not executing
99 * a syscall -- i.e., its most recent entry into the kernel from
100 * userspace was not via SVC, or otherwise a tracer cancelled the syscall.
102 * This must have the value -1, for ABI compatibility with ptrace etc.
104 #define NO_SYSCALL (-1)
107 #include <linux/bug.h>
108 #include <linux/types.h>
110 /* sizeof(struct user) for AArch32 */
111 #define COMPAT_USER_SZ 296
113 /* Architecturally defined mapping between AArch32 and AArch64 registers */
114 #define compat_usr(x) regs[(x)]
115 #define compat_fp regs[11]
116 #define compat_sp regs[13]
117 #define compat_lr regs[14]
118 #define compat_sp_hyp regs[15]
119 #define compat_lr_irq regs[16]
120 #define compat_sp_irq regs[17]
121 #define compat_lr_svc regs[18]
122 #define compat_sp_svc regs[19]
123 #define compat_lr_abt regs[20]
124 #define compat_sp_abt regs[21]
125 #define compat_lr_und regs[22]
126 #define compat_sp_und regs[23]
127 #define compat_r8_fiq regs[24]
128 #define compat_r9_fiq regs[25]
129 #define compat_r10_fiq regs[26]
130 #define compat_r11_fiq regs[27]
131 #define compat_r12_fiq regs[28]
132 #define compat_sp_fiq regs[29]
133 #define compat_lr_fiq regs[30]
135 static inline unsigned long compat_psr_to_pstate(const unsigned long psr
)
137 unsigned long pstate
;
139 pstate
= psr
& ~COMPAT_PSR_DIT_BIT
;
141 if (psr
& COMPAT_PSR_DIT_BIT
)
142 pstate
|= PSR_AA32_DIT_BIT
;
147 static inline unsigned long pstate_to_compat_psr(const unsigned long pstate
)
151 psr
= pstate
& ~PSR_AA32_DIT_BIT
;
153 if (pstate
& PSR_AA32_DIT_BIT
)
154 psr
|= COMPAT_PSR_DIT_BIT
;
160 * This struct defines the way the registers are stored on the stack during an
161 * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for
162 * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs.
166 struct user_pt_regs user_regs
;
184 /* Only valid when ARM64_HAS_IRQ_PRIO_MASKING is enabled. */
189 static inline bool in_syscall(struct pt_regs
const *regs
)
191 return regs
->syscallno
!= NO_SYSCALL
;
194 static inline void forget_syscall(struct pt_regs
*regs
)
196 regs
->syscallno
= NO_SYSCALL
;
199 #define MAX_REG_OFFSET offsetof(struct pt_regs, pstate)
201 #define arch_has_single_step() (1)
204 #define compat_thumb_mode(regs) \
205 (((regs)->pstate & PSR_AA32_T_BIT))
207 #define compat_thumb_mode(regs) (0)
210 #define user_mode(regs) \
211 (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)
213 #define compat_user_mode(regs) \
214 (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \
215 (PSR_MODE32_BIT | PSR_MODE_EL0t))
217 #define processor_mode(regs) \
218 ((regs)->pstate & PSR_MODE_MASK)
220 #define irqs_priority_unmasked(regs) \
221 (system_uses_irq_prio_masking() ? \
222 (regs)->pmr_save == GIC_PRIO_IRQON : \
225 #define interrupts_enabled(regs) \
226 (!((regs)->pstate & PSR_I_BIT) && irqs_priority_unmasked(regs))
228 #define fast_interrupts_enabled(regs) \
229 (!((regs)->pstate & PSR_F_BIT))
231 #define GET_USP(regs) \
232 (!compat_user_mode(regs) ? (regs)->sp : (regs)->compat_sp)
234 #define SET_USP(ptregs, value) \
235 (!compat_user_mode(regs) ? ((regs)->sp = value) : ((regs)->compat_sp = value))
237 extern int regs_query_register_offset(const char *name
);
238 extern unsigned long regs_get_kernel_stack_nth(struct pt_regs
*regs
,
242 * regs_get_register() - get register value from its offset
243 * @regs: pt_regs from which register value is gotten
244 * @offset: offset of the register.
246 * regs_get_register returns the value of a register whose offset from @regs.
247 * The @offset is the offset of the register in struct pt_regs.
248 * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
250 static inline u64
regs_get_register(struct pt_regs
*regs
, unsigned int offset
)
259 val
= regs
->regs
[offset
];
261 case offsetof(struct pt_regs
, sp
) >> 3:
264 case offsetof(struct pt_regs
, pc
) >> 3:
267 case offsetof(struct pt_regs
, pstate
) >> 3:
278 * Read a register given an architectural register index r.
279 * This handles the common case where 31 means XZR, not SP.
281 static inline unsigned long pt_regs_read_reg(const struct pt_regs
*regs
, int r
)
283 return (r
== 31) ? 0 : regs
->regs
[r
];
287 * Write a register given an architectural register index r.
288 * This handles the common case where 31 means XZR, not SP.
290 static inline void pt_regs_write_reg(struct pt_regs
*regs
, int r
,
297 /* Valid only for Kernel mode traps. */
298 static inline unsigned long kernel_stack_pointer(struct pt_regs
*regs
)
303 static inline unsigned long regs_return_value(struct pt_regs
*regs
)
305 return regs
->regs
[0];
309 * regs_get_kernel_argument() - get Nth function argument in kernel
310 * @regs: pt_regs of that context
311 * @n: function argument number (start from 0)
313 * regs_get_argument() returns @n th argument of the function call.
315 * Note that this chooses the most likely register mapping. In very rare
316 * cases this may not return correct data, for example, if one of the
317 * function parameters is 16 bytes or bigger. In such cases, we cannot
318 * get access the parameter correctly and the register assignment of
319 * subsequent parameters will be shifted.
321 static inline unsigned long regs_get_kernel_argument(struct pt_regs
*regs
,
324 #define NR_REG_ARGUMENTS 8
325 if (n
< NR_REG_ARGUMENTS
)
326 return pt_regs_read_reg(regs
, n
);
330 /* We must avoid circular header include via sched.h */
332 int valid_user_regs(struct user_pt_regs
*regs
, struct task_struct
*task
);
334 #define GET_IP(regs) ((unsigned long)(regs)->pc)
335 #define SET_IP(regs, value) ((regs)->pc = ((u64) (value)))
337 #define GET_FP(ptregs) ((unsigned long)(ptregs)->regs[29])
338 #define SET_FP(ptregs, value) ((ptregs)->regs[29] = ((u64) (value)))
340 #include <asm-generic/ptrace.h>
342 #define procedure_link_pointer(regs) ((regs)->regs[30])
344 static inline void procedure_link_pointer_set(struct pt_regs
*regs
,
347 procedure_link_pointer(regs
) = val
;
351 extern unsigned long profile_pc(struct pt_regs
*regs
);
353 #endif /* __ASSEMBLY__ */