arch/arm64/kernel/armv8_deprecated.c

   1 /*
   2  *  Copyright (C) 2014 ARM Limited
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/cpu.h>
  10 #include <linux/init.h>
  11 #include <linux/list.h>
  12 #include <linux/perf_event.h>
  13 #include <linux/sched.h>
  14 #include <linux/slab.h>
  15 #include <linux/sysctl.h>
  16
  17 #include <asm/cpufeature.h>
  18 #include <asm/insn.h>
  19 #include <asm/sysreg.h>
  20 #include <asm/system_misc.h>
  21 #include <asm/traps.h>
  22 #include <asm/kprobes.h>
  23 #include <linux/uaccess.h>
  24 #include <asm/cpufeature.h>
  25
  26 #define CREATE_TRACE_POINTS
  27 #include "trace-events-emulation.h"
  28
  29 /*
  30  * The runtime support for deprecated instruction support can be in one of
  31  * following three states -
  32  *
  33  * 0 = undef
  34  * 1 = emulate (software emulation)
  35  * 2 = hw (supported in hardware)
  36  */
  37 enum insn_emulation_mode {
  38         INSN_UNDEF,
  39         INSN_EMULATE,
  40         INSN_HW,
  41 };
  42
  43 enum legacy_insn_status {
  44         INSN_DEPRECATED,
  45         INSN_OBSOLETE,
  46 };
  47
  48 struct insn_emulation_ops {
  49         const char              *name;
  50         enum legacy_insn_status status;
  51         struct undef_hook       *hooks;
  52         int                     (*set_hw_mode)(bool enable);
  53 };
  54
  55 struct insn_emulation {
  56         struct list_head node;
  57         struct insn_emulation_ops *ops;
  58         int current_mode;
  59         int min;
  60         int max;
  61 };
  62
  63 static LIST_HEAD(insn_emulation);
  64 static int nr_insn_emulated __initdata;
  65 static DEFINE_RAW_SPINLOCK(insn_emulation_lock);
  66
  67 static void register_emulation_hooks(struct insn_emulation_ops *ops)
  68 {
  69         struct undef_hook *hook;
  70
  71         BUG_ON(!ops->hooks);
  72
  73         for (hook = ops->hooks; hook->instr_mask; hook++)
  74                 register_undef_hook(hook);
  75
  76         pr_notice("Registered %s emulation handler\n", ops->name);
  77 }
  78
  79 static void remove_emulation_hooks(struct insn_emulation_ops *ops)
  80 {
  81         struct undef_hook *hook;
  82
  83         BUG_ON(!ops->hooks);
  84
  85         for (hook = ops->hooks; hook->instr_mask; hook++)
  86                 unregister_undef_hook(hook);
  87
  88         pr_notice("Removed %s emulation handler\n", ops->name);
  89 }
  90
  91 static void enable_insn_hw_mode(void *data)
  92 {
  93         struct insn_emulation *insn = (struct insn_emulation *)data;
  94         if (insn->ops->set_hw_mode)
  95                 insn->ops->set_hw_mode(true);
  96 }
  97
  98 static void disable_insn_hw_mode(void *data)
  99 {
 100         struct insn_emulation *insn = (struct insn_emulation *)data;
 101         if (insn->ops->set_hw_mode)
 102                 insn->ops->set_hw_mode(false);
 103 }
 104
 105 /* Run set_hw_mode(mode) on all active CPUs */
 106 static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable)
 107 {
 108         if (!insn->ops->set_hw_mode)
 109                 return -EINVAL;
 110         if (enable)
 111                 on_each_cpu(enable_insn_hw_mode, (void *)insn, true);
 112         else
 113                 on_each_cpu(disable_insn_hw_mode, (void *)insn, true);
 114         return 0;
 115 }
 116
 117 /*
 118  * Run set_hw_mode for all insns on a starting CPU.
 119  * Returns:
 120  *  0           - If all the hooks ran successfully.
 121  * -EINVAL      - At least one hook is not supported by the CPU.
 122  */
 123 static int run_all_insn_set_hw_mode(unsigned int cpu)
 124 {
 125         int rc = 0;
 126         unsigned long flags;
 127         struct insn_emulation *insn;
 128
 129         raw_spin_lock_irqsave(&insn_emulation_lock, flags);
 130         list_for_each_entry(insn, &insn_emulation, node) {
 131                 bool enable = (insn->current_mode == INSN_HW);
 132                 if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(enable)) {
 133                         pr_warn("CPU[%u] cannot support the emulation of %s",
 134                                 cpu, insn->ops->name);
 135                         rc = -EINVAL;
 136                 }
 137         }
 138         raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
 139         return rc;
 140 }
 141
 142 static int update_insn_emulation_mode(struct insn_emulation *insn,
 143                                        enum insn_emulation_mode prev)
 144 {
 145         int ret = 0;
 146
 147         switch (prev) {
 148         case INSN_UNDEF: /* Nothing to be done */
 149                 break;
 150         case INSN_EMULATE:
 151                 remove_emulation_hooks(insn->ops);
 152                 break;
 153         case INSN_HW:
 154                 if (!run_all_cpu_set_hw_mode(insn, false))
 155                         pr_notice("Disabled %s support\n", insn->ops->name);
 156                 break;
 157         }
 158
 159         switch (insn->current_mode) {
 160         case INSN_UNDEF:
 161                 break;
 162         case INSN_EMULATE:
 163                 register_emulation_hooks(insn->ops);
 164                 break;
 165         case INSN_HW:
 166                 ret = run_all_cpu_set_hw_mode(insn, true);
 167                 if (!ret)
 168                         pr_notice("Enabled %s support\n", insn->ops->name);
 169                 break;
 170         }
 171
 172         return ret;
 173 }
 174
 175 static void __init register_insn_emulation(struct insn_emulation_ops *ops)
 176 {
 177         unsigned long flags;
 178         struct insn_emulation *insn;
 179
 180         insn = kzalloc(sizeof(*insn), GFP_KERNEL);
 181         insn->ops = ops;
 182         insn->min = INSN_UNDEF;
 183
 184         switch (ops->status) {
 185         case INSN_DEPRECATED:
 186 #if 0
 187                 insn->current_mode = INSN_EMULATE;
 188                 /* Disable the HW mode if it was turned on at early boot time */
 189                 run_all_cpu_set_hw_mode(insn, false);
 190 #else
 191                 insn->current_mode = INSN_HW;
 192                 run_all_cpu_set_hw_mode(insn, true);
 193                 insn->max = INSN_HW;
 194 #endif
 195                 break;
 196         case INSN_OBSOLETE:
 197                 insn->current_mode = INSN_UNDEF;
 198                 insn->max = INSN_EMULATE;
 199                 break;
 200         }
 201
 202         raw_spin_lock_irqsave(&insn_emulation_lock, flags);
 203         list_add(&insn->node, &insn_emulation);
 204         nr_insn_emulated++;
 205         raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
 206
 207         /* Register any handlers if required */
 208         update_insn_emulation_mode(insn, INSN_UNDEF);
 209 }
 210
 211 static int emulation_proc_handler(struct ctl_table *table, int write,
 212                                   void __user *buffer, size_t *lenp,
 213                                   loff_t *ppos)
 214 {
 215         int ret = 0;
 216         struct insn_emulation *insn = (struct insn_emulation *) table->data;
 217         enum insn_emulation_mode prev_mode = insn->current_mode;
 218
 219         table->data = &insn->current_mode;
 220         ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
 221
 222         if (ret || !write || prev_mode == insn->current_mode)
 223                 goto ret;
 224
 225         ret = update_insn_emulation_mode(insn, prev_mode);
 226         if (ret) {
 227                 /* Mode change failed, revert to previous mode. */
 228                 insn->current_mode = prev_mode;
 229                 update_insn_emulation_mode(insn, INSN_UNDEF);
 230         }
 231 ret:
 232         table->data = insn;
 233         return ret;
 234 }
 235
 236 static struct ctl_table ctl_abi[] = {
 237         {
 238                 .procname = "abi",
 239                 .mode = 0555,
 240         },
 241         { }
 242 };
 243
 244 static void __init register_insn_emulation_sysctl(struct ctl_table *table)
 245 {
 246         unsigned long flags;
 247         int i = 0;
 248         struct insn_emulation *insn;
 249         struct ctl_table *insns_sysctl, *sysctl;
 250
 251         insns_sysctl = kzalloc(sizeof(*sysctl) * (nr_insn_emulated + 1),
 252                               GFP_KERNEL);
 253
 254         raw_spin_lock_irqsave(&insn_emulation_lock, flags);
 255         list_for_each_entry(insn, &insn_emulation, node) {
 256                 sysctl = &insns_sysctl[i];
 257
 258                 sysctl->mode = 0644;
 259                 sysctl->maxlen = sizeof(int);
 260
 261                 sysctl->procname = insn->ops->name;
 262                 sysctl->data = insn;
 263                 sysctl->extra1 = &insn->min;
 264                 sysctl->extra2 = &insn->max;
 265                 sysctl->proc_handler = emulation_proc_handler;
 266                 i++;
 267         }
 268         raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
 269
 270         table->child = insns_sysctl;
 271         register_sysctl_table(table);
 272 }
 273
 274 /*
 275  *  Implement emulation of the SWP/SWPB instructions using load-exclusive and
 276  *  store-exclusive.
 277  *
 278  *  Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
 279  *  Where: Rt  = destination
 280  *         Rt2 = source
 281  *         Rn  = address
 282  */
 283
 284 /*
 285  * Error-checking SWP macros implemented using ldxr{b}/stxr{b}
 286  */
 287
 288 /* Arbitrary constant to ensure forward-progress of the LL/SC loop */
 289 #define __SWP_LL_SC_LOOPS       4
 290
 291 #define __user_swpX_asm(data, addr, res, temp, temp2, B)        \
 292 do {                                                            \
 293         uaccess_enable();                                       \
 294         __asm__ __volatile__(                                   \
 295         "       mov             %w3, %w7\n"                     \
 296         "0:     ldxr"B"         %w2, [%4]\n"                    \
 297         "1:     stxr"B"         %w0, %w1, [%4]\n"               \
 298         "       cbz             %w0, 2f\n"                      \
 299         "       sub             %w3, %w3, #1\n"                 \
 300         "       cbnz            %w3, 0b\n"                      \
 301         "       mov             %w0, %w5\n"                     \
 302         "       b               3f\n"                           \
 303         "2:\n"                                                  \
 304         "       mov             %w1, %w2\n"                     \
 305         "3:\n"                                                  \
 306         "       .pushsection     .fixup,\"ax\"\n"               \
 307         "       .align          2\n"                            \
 308         "4:     mov             %w0, %w6\n"                     \
 309         "       b               3b\n"                           \
 310         "       .popsection"                                    \
 311         _ASM_EXTABLE(0b, 4b)                                    \
 312         _ASM_EXTABLE(1b, 4b)                                    \
 313         : "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2) \
 314         : "r" ((unsigned long)addr), "i" (-EAGAIN),             \
 315           "i" (-EFAULT),                                        \
 316           "i" (__SWP_LL_SC_LOOPS)                               \
 317         : "memory");                                            \
 318         uaccess_disable();                                      \
 319 } while (0)
 320
 321 #define __user_swp_asm(data, addr, res, temp, temp2) \
 322         __user_swpX_asm(data, addr, res, temp, temp2, "")
 323 #define __user_swpb_asm(data, addr, res, temp, temp2) \
 324         __user_swpX_asm(data, addr, res, temp, temp2, "b")
 325
 326 /*
 327  * Bit 22 of the instruction encoding distinguishes between
 328  * the SWP and SWPB variants (bit set means SWPB).
 329  */
 330 #define TYPE_SWPB (1 << 22)
 331
 332 static int emulate_swpX(unsigned int address, unsigned int *data,
 333                         unsigned int type)
 334 {
 335         unsigned int res = 0;
 336
 337         if ((type != TYPE_SWPB) && (address & 0x3)) {
 338                 /* SWP to unaligned address not permitted */
 339                 pr_debug("SWP instruction on unaligned pointer!\n");
 340                 return -EFAULT;
 341         }
 342
 343         while (1) {
 344                 unsigned long temp, temp2;
 345
 346                 if (type == TYPE_SWPB)
 347                         __user_swpb_asm(*data, address, res, temp, temp2);
 348                 else
 349                         __user_swp_asm(*data, address, res, temp, temp2);
 350
 351                 if (likely(res != -EAGAIN) || signal_pending(current))
 352                         break;
 353
 354                 cond_resched();
 355         }
 356
 357         return res;
 358 }
 359
 360 #define ARM_OPCODE_CONDTEST_FAIL   0
 361 #define ARM_OPCODE_CONDTEST_PASS   1
 362 #define ARM_OPCODE_CONDTEST_UNCOND 2
 363
 364 #define ARM_OPCODE_CONDITION_UNCOND     0xf
 365
 366 static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr)
 367 {
 368         u32 cc_bits  = opcode >> 28;
 369
 370         if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
 371                 if ((*aarch32_opcode_cond_checks[cc_bits])(psr))
 372                         return ARM_OPCODE_CONDTEST_PASS;
 373                 else
 374                         return ARM_OPCODE_CONDTEST_FAIL;
 375         }
 376         return ARM_OPCODE_CONDTEST_UNCOND;
 377 }
 378
 379 /*
 380  * swp_handler logs the id of calling process, dissects the instruction, sanity
 381  * checks the memory location, calls emulate_swpX for the actual operation and
 382  * deals with fixup/error handling before returning
 383  */
 384 static int swp_handler(struct pt_regs *regs, u32 instr)
 385 {
 386         u32 destreg, data, type, address = 0;
 387         int rn, rt2, res = 0;
 388
 389         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
 390
 391         type = instr & TYPE_SWPB;
 392
 393         switch (aarch32_check_condition(instr, regs->pstate)) {
 394         case ARM_OPCODE_CONDTEST_PASS:
 395                 break;
 396         case ARM_OPCODE_CONDTEST_FAIL:
 397                 /* Condition failed - return to next instruction */
 398                 goto ret;
 399         case ARM_OPCODE_CONDTEST_UNCOND:
 400                 /* If unconditional encoding - not a SWP, undef */
 401                 return -EFAULT;
 402         default:
 403                 return -EINVAL;
 404         }
 405
 406         rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET);
 407         rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET);
 408
 409         address = (u32)regs->user_regs.regs[rn];
 410         data    = (u32)regs->user_regs.regs[rt2];
 411         destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET);
 412
 413         pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
 414                 rn, address, destreg,
 415                 aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data);
 416
 417         /* Check access in reasonable access range for both SWP and SWPB */
 418         if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) {
 419                 pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n",
 420                         address);
 421                 goto fault;
 422         }
 423
 424         res = emulate_swpX(address, &data, type);
 425         if (res == -EFAULT)
 426                 goto fault;
 427         else if (res == 0)
 428                 regs->user_regs.regs[destreg] = data;
 429
 430 ret:
 431         if (type == TYPE_SWPB)
 432                 trace_instruction_emulation("swpb", regs->pc);
 433         else
 434                 trace_instruction_emulation("swp", regs->pc);
 435
 436         pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",
 437                         current->comm, (unsigned long)current->pid, regs->pc);
 438
 439         regs->pc += 4;
 440         return 0;
 441
 442 fault:
 443         pr_debug("SWP{B} emulation: access caused memory abort!\n");
 444         arm64_notify_segfault(regs, address);
 445
 446         return 0;
 447 }
 448
 449 /*
 450  * Only emulate SWP/SWPB executed in ARM state/User mode.
 451  * The kernel must be SWP free and SWP{B} does not exist in Thumb.
 452  */
 453 static struct undef_hook swp_hooks[] = {
 454         {
 455                 .instr_mask     = 0x0fb00ff0,
 456                 .instr_val      = 0x01000090,
 457                 .pstate_mask    = COMPAT_PSR_MODE_MASK,
 458                 .pstate_val     = COMPAT_PSR_MODE_USR,
 459                 .fn             = swp_handler
 460         },
 461         { }
 462 };
 463
 464 static struct insn_emulation_ops swp_ops = {
 465         .name = "swp",
 466         .status = INSN_OBSOLETE,
 467         .hooks = swp_hooks,
 468         .set_hw_mode = NULL,
 469 };
 470
 471 static int cp15barrier_handler(struct pt_regs *regs, u32 instr)
 472 {
 473         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
 474
 475         switch (aarch32_check_condition(instr, regs->pstate)) {
 476         case ARM_OPCODE_CONDTEST_PASS:
 477                 break;
 478         case ARM_OPCODE_CONDTEST_FAIL:
 479                 /* Condition failed - return to next instruction */
 480                 goto ret;
 481         case ARM_OPCODE_CONDTEST_UNCOND:
 482                 /* If unconditional encoding - not a barrier instruction */
 483                 return -EFAULT;
 484         default:
 485                 return -EINVAL;
 486         }
 487
 488         switch (aarch32_insn_mcr_extract_crm(instr)) {
 489         case 10:
 490                 /*
 491                  * dmb - mcr p15, 0, Rt, c7, c10, 5
 492                  * dsb - mcr p15, 0, Rt, c7, c10, 4
 493                  */
 494                 if (aarch32_insn_mcr_extract_opc2(instr) == 5) {
 495                         dmb(sy);
 496                         trace_instruction_emulation(
 497                                 "mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc);
 498                 } else {
 499                         dsb(sy);
 500                         trace_instruction_emulation(
 501                                 "mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc);
 502                 }
 503                 break;
 504         case 5:
 505                 /*
 506                  * isb - mcr p15, 0, Rt, c7, c5, 4
 507                  *
 508                  * Taking an exception or returning from one acts as an
 509                  * instruction barrier. So no explicit barrier needed here.
 510                  */
 511                 trace_instruction_emulation(
 512                         "mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc);
 513                 break;
 514         }
 515
 516 ret:
 517         pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",
 518                         current->comm, (unsigned long)current->pid, regs->pc);
 519
 520         regs->pc += 4;
 521         return 0;
 522 }
 523
 524 static int cp15_barrier_set_hw_mode(bool enable)
 525 {
 526         if (enable)
 527                 config_sctlr_el1(0, SCTLR_EL1_CP15BEN);
 528         else
 529                 config_sctlr_el1(SCTLR_EL1_CP15BEN, 0);
 530         return 0;
 531 }
 532
 533 static struct undef_hook cp15_barrier_hooks[] = {
 534         {
 535                 .instr_mask     = 0x0fff0fdf,
 536                 .instr_val      = 0x0e070f9a,
 537                 .pstate_mask    = COMPAT_PSR_MODE_MASK,
 538                 .pstate_val     = COMPAT_PSR_MODE_USR,
 539                 .fn             = cp15barrier_handler,
 540         },
 541         {
 542                 .instr_mask     = 0x0fff0fff,
 543                 .instr_val      = 0x0e070f95,
 544                 .pstate_mask    = COMPAT_PSR_MODE_MASK,
 545                 .pstate_val     = COMPAT_PSR_MODE_USR,
 546                 .fn             = cp15barrier_handler,
 547         },
 548         { }
 549 };
 550
 551 static struct insn_emulation_ops cp15_barrier_ops = {
 552         .name = "cp15_barrier",
 553         .status = INSN_DEPRECATED,
 554         .hooks = cp15_barrier_hooks,
 555         .set_hw_mode = cp15_barrier_set_hw_mode,
 556 };
 557
 558 static int setend_set_hw_mode(bool enable)
 559 {
 560         if (!cpu_supports_mixed_endian_el0())
 561                 return -EINVAL;
 562
 563         if (enable)
 564                 config_sctlr_el1(SCTLR_EL1_SED, 0);
 565         else
 566                 config_sctlr_el1(0, SCTLR_EL1_SED);
 567         return 0;
 568 }
 569
 570 static int compat_setend_handler(struct pt_regs *regs, u32 big_endian)
 571 {
 572         char *insn;
 573
 574         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
 575
 576         if (big_endian) {
 577                 insn = "setend be";
 578                 regs->pstate |= COMPAT_PSR_E_BIT;
 579         } else {
 580                 insn = "setend le";
 581                 regs->pstate &= ~COMPAT_PSR_E_BIT;
 582         }
 583
 584         trace_instruction_emulation(insn, regs->pc);
 585         pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n",
 586                         current->comm, (unsigned long)current->pid, regs->pc);
 587
 588         return 0;
 589 }
 590
 591 static int a32_setend_handler(struct pt_regs *regs, u32 instr)
 592 {
 593         int rc = compat_setend_handler(regs, (instr >> 9) & 1);
 594         regs->pc += 4;
 595         return rc;
 596 }
 597
 598 static int t16_setend_handler(struct pt_regs *regs, u32 instr)
 599 {
 600         int rc = compat_setend_handler(regs, (instr >> 3) & 1);
 601         regs->pc += 2;
 602         return rc;
 603 }
 604
 605 static struct undef_hook setend_hooks[] = {
 606         {
 607                 .instr_mask     = 0xfffffdff,
 608                 .instr_val      = 0xf1010000,
 609                 .pstate_mask    = COMPAT_PSR_MODE_MASK,
 610                 .pstate_val     = COMPAT_PSR_MODE_USR,
 611                 .fn             = a32_setend_handler,
 612         },
 613         {
 614                 /* Thumb mode */
 615                 .instr_mask     = 0x0000fff7,
 616                 .instr_val      = 0x0000b650,
 617                 .pstate_mask    = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_MASK),
 618                 .pstate_val     = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_USR),
 619                 .fn             = t16_setend_handler,
 620         },
 621         {}
 622 };
 623
 624 static struct insn_emulation_ops setend_ops = {
 625         .name = "setend",
 626         .status = INSN_DEPRECATED,
 627         .hooks = setend_hooks,
 628         .set_hw_mode = setend_set_hw_mode,
 629 };
 630
 631 /*
 632  * Invoked as late_initcall, since not needed before init spawned.
 633  */
 634 static int __init armv8_deprecated_init(void)
 635 {
 636         if (IS_ENABLED(CONFIG_SWP_EMULATION))
 637                 register_insn_emulation(&swp_ops);
 638
 639         if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION))
 640                 register_insn_emulation(&cp15_barrier_ops);
 641
 642         if (IS_ENABLED(CONFIG_SETEND_EMULATION)) {
 643                 if(system_supports_mixed_endian_el0())
 644                         register_insn_emulation(&setend_ops);
 645                 else
 646                         pr_info("setend instruction emulation is not supported on this system\n");
 647         }
 648
 649         cpuhp_setup_state_nocalls(CPUHP_AP_ARM64_ISNDEP_STARTING,
 650                                   "arm64/isndep:starting",
 651                                   run_all_insn_set_hw_mode, NULL);
 652         register_insn_emulation_sysctl(ctl_abi);
 653
 654         return 0;
 655 }
 656
 657 late_initcall(armv8_deprecated_init);