2 * Contains CPU feature definitions
4 * Copyright (C) 2015 ARM Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) "CPU features: " fmt
21 #include <linux/bsearch.h>
22 #include <linux/cpumask.h>
23 #include <linux/crash_dump.h>
24 #include <linux/sort.h>
25 #include <linux/stop_machine.h>
26 #include <linux/types.h>
29 #include <asm/cpufeature.h>
30 #include <asm/cpu_ops.h>
31 #include <asm/fpsimd.h>
32 #include <asm/mmu_context.h>
33 #include <asm/processor.h>
34 #include <asm/sysreg.h>
35 #include <asm/traps.h>
38 unsigned long elf_hwcap __read_mostly
;
39 EXPORT_SYMBOL_GPL(elf_hwcap
);
42 #define COMPAT_ELF_HWCAP_DEFAULT \
43 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
44 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
45 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
46 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
47 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
49 unsigned int compat_elf_hwcap __read_mostly
= COMPAT_ELF_HWCAP_DEFAULT
;
50 unsigned int compat_elf_hwcap2 __read_mostly
;
53 DECLARE_BITMAP(cpu_hwcaps
, ARM64_NCAPS
);
54 EXPORT_SYMBOL(cpu_hwcaps
);
55 static struct arm64_cpu_capabilities
const __ro_after_init
*cpu_hwcaps_ptrs
[ARM64_NCAPS
];
58 * Flag to indicate if we have computed the system wide
59 * capabilities based on the boot time active CPUs. This
60 * will be used to determine if a new booting CPU should
61 * go through the verification process to make sure that it
62 * supports the system capabilities, without using a hotplug
65 static bool sys_caps_initialised
;
67 static inline void set_sys_caps_initialised(void)
69 sys_caps_initialised
= true;
72 static int dump_cpu_hwcaps(struct notifier_block
*self
, unsigned long v
, void *p
)
74 /* file-wide pr_fmt adds "CPU features: " prefix */
75 pr_emerg("0x%*pb\n", ARM64_NCAPS
, &cpu_hwcaps
);
79 static struct notifier_block cpu_hwcaps_notifier
= {
80 .notifier_call
= dump_cpu_hwcaps
83 static int __init
register_cpu_hwcaps_dumper(void)
85 atomic_notifier_chain_register(&panic_notifier_list
,
86 &cpu_hwcaps_notifier
);
89 __initcall(register_cpu_hwcaps_dumper
);
91 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys
, ARM64_NCAPS
);
92 EXPORT_SYMBOL(cpu_hwcap_keys
);
94 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
102 .safe_val = SAFE_VAL, \
105 /* Define a feature with unsigned values */
106 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
107 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
109 /* Define a feature with a signed value */
110 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
111 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
113 #define ARM64_FTR_END \
118 /* meta feature for alternatives */
119 static bool __maybe_unused
120 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities
*entry
, int __unused
);
122 static void cpu_enable_cnp(struct arm64_cpu_capabilities
const *cap
);
125 * NOTE: Any changes to the visibility of features should be kept in
126 * sync with the documentation of the CPU feature register ABI.
128 static const struct arm64_ftr_bits ftr_id_aa64isar0
[] = {
129 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_TS_SHIFT
, 4, 0),
130 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_FHM_SHIFT
, 4, 0),
131 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_DP_SHIFT
, 4, 0),
132 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_SM4_SHIFT
, 4, 0),
133 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_SM3_SHIFT
, 4, 0),
134 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_SHA3_SHIFT
, 4, 0),
135 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_RDM_SHIFT
, 4, 0),
136 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_ATOMICS_SHIFT
, 4, 0),
137 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_CRC32_SHIFT
, 4, 0),
138 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_SHA2_SHIFT
, 4, 0),
139 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_SHA1_SHIFT
, 4, 0),
140 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_AES_SHIFT
, 4, 0),
144 static const struct arm64_ftr_bits ftr_id_aa64isar1
[] = {
145 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR1_SB_SHIFT
, 4, 0),
146 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH
),
147 FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR1_GPI_SHIFT
, 4, 0),
148 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH
),
149 FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR1_GPA_SHIFT
, 4, 0),
150 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR1_LRCPC_SHIFT
, 4, 0),
151 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR1_FCMA_SHIFT
, 4, 0),
152 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR1_JSCVT_SHIFT
, 4, 0),
153 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH
),
154 FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR1_API_SHIFT
, 4, 0),
155 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH
),
156 FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR1_APA_SHIFT
, 4, 0),
157 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR1_DPB_SHIFT
, 4, 0),
161 static const struct arm64_ftr_bits ftr_id_aa64pfr0
[] = {
162 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_CSV3_SHIFT
, 4, 0),
163 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_CSV2_SHIFT
, 4, 0),
164 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_DIT_SHIFT
, 4, 0),
165 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE
),
166 FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_SVE_SHIFT
, 4, 0),
167 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_RAS_SHIFT
, 4, 0),
168 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_GIC_SHIFT
, 4, 0),
169 S_ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_ASIMD_SHIFT
, 4, ID_AA64PFR0_ASIMD_NI
),
170 S_ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_FP_SHIFT
, 4, ID_AA64PFR0_FP_NI
),
171 /* Linux doesn't care about the EL3 */
172 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_EL3_SHIFT
, 4, 0),
173 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_EL2_SHIFT
, 4, 0),
174 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_EL1_SHIFT
, 4, ID_AA64PFR0_EL1_64BIT_ONLY
),
175 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_EL0_SHIFT
, 4, ID_AA64PFR0_EL0_64BIT_ONLY
),
179 static const struct arm64_ftr_bits ftr_id_aa64pfr1
[] = {
180 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR1_SSBS_SHIFT
, 4, ID_AA64PFR1_SSBS_PSTATE_NI
),
184 static const struct arm64_ftr_bits ftr_id_aa64mmfr0
[] = {
185 S_ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_TGRAN4_SHIFT
, 4, ID_AA64MMFR0_TGRAN4_NI
),
186 S_ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_TGRAN64_SHIFT
, 4, ID_AA64MMFR0_TGRAN64_NI
),
187 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_TGRAN16_SHIFT
, 4, ID_AA64MMFR0_TGRAN16_NI
),
188 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_BIGENDEL0_SHIFT
, 4, 0),
189 /* Linux shouldn't care about secure memory */
190 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_SNSMEM_SHIFT
, 4, 0),
191 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_BIGENDEL_SHIFT
, 4, 0),
192 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_ASID_SHIFT
, 4, 0),
194 * Differing PARange is fine as long as all peripherals and memory are mapped
195 * within the minimum PARange of all CPUs
197 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_PARANGE_SHIFT
, 4, 0),
201 static const struct arm64_ftr_bits ftr_id_aa64mmfr1
[] = {
202 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR1_PAN_SHIFT
, 4, 0),
203 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR1_LOR_SHIFT
, 4, 0),
204 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR1_HPD_SHIFT
, 4, 0),
205 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR1_VHE_SHIFT
, 4, 0),
206 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR1_VMIDBITS_SHIFT
, 4, 0),
207 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR1_HADBS_SHIFT
, 4, 0),
211 static const struct arm64_ftr_bits ftr_id_aa64mmfr2
[] = {
212 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR2_FWB_SHIFT
, 4, 0),
213 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR2_AT_SHIFT
, 4, 0),
214 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR2_LVA_SHIFT
, 4, 0),
215 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR2_IESB_SHIFT
, 4, 0),
216 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR2_LSM_SHIFT
, 4, 0),
217 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR2_UAO_SHIFT
, 4, 0),
218 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR2_CNP_SHIFT
, 4, 0),
222 static const struct arm64_ftr_bits ftr_ctr
[] = {
223 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_EXACT
, 31, 1, 1), /* RES1 */
224 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, CTR_DIC_SHIFT
, 1, 1),
225 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, CTR_IDC_SHIFT
, 1, 1),
226 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_HIGHER_SAFE
, CTR_CWG_SHIFT
, 4, 0),
227 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_HIGHER_SAFE
, CTR_ERG_SHIFT
, 4, 0),
228 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, CTR_DMINLINE_SHIFT
, 4, 1),
230 * Linux can handle differing I-cache policies. Userspace JITs will
231 * make use of *minLine.
232 * If we have differing I-cache policies, report it as the weakest - VIPT.
234 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_NONSTRICT
, FTR_EXACT
, 14, 2, ICACHE_POLICY_VIPT
), /* L1Ip */
235 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, CTR_IMINLINE_SHIFT
, 4, 0),
239 struct arm64_ftr_reg arm64_ftr_reg_ctrel0
= {
240 .name
= "SYS_CTR_EL0",
244 static const struct arm64_ftr_bits ftr_id_mmfr0
[] = {
245 S_ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 28, 4, 0xf), /* InnerShr */
246 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 24, 4, 0), /* FCSE */
247 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, 20, 4, 0), /* AuxReg */
248 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 16, 4, 0), /* TCM */
249 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 12, 4, 0), /* ShareLvl */
250 S_ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 8, 4, 0xf), /* OuterShr */
251 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0), /* PMSA */
252 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0), /* VMSA */
256 static const struct arm64_ftr_bits ftr_id_aa64dfr0
[] = {
257 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_EXACT
, 36, 28, 0),
258 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64DFR0_PMSVER_SHIFT
, 4, 0),
259 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64DFR0_CTX_CMPS_SHIFT
, 4, 0),
260 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64DFR0_WRPS_SHIFT
, 4, 0),
261 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64DFR0_BRPS_SHIFT
, 4, 0),
263 * We can instantiate multiple PMU instances with different levels
266 S_ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_EXACT
, ID_AA64DFR0_PMUVER_SHIFT
, 4, 0),
267 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_EXACT
, ID_AA64DFR0_TRACEVER_SHIFT
, 4, 0),
268 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_EXACT
, ID_AA64DFR0_DEBUGVER_SHIFT
, 4, 0x6),
272 static const struct arm64_ftr_bits ftr_mvfr2
[] = {
273 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0), /* FPMisc */
274 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0), /* SIMDMisc */
278 static const struct arm64_ftr_bits ftr_dczid
[] = {
279 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_EXACT
, 4, 1, 1), /* DZP */
280 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0), /* BS */
285 static const struct arm64_ftr_bits ftr_id_isar5
[] = {
286 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_ISAR5_RDM_SHIFT
, 4, 0),
287 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_ISAR5_CRC32_SHIFT
, 4, 0),
288 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_ISAR5_SHA2_SHIFT
, 4, 0),
289 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_ISAR5_SHA1_SHIFT
, 4, 0),
290 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_ISAR5_AES_SHIFT
, 4, 0),
291 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_ISAR5_SEVL_SHIFT
, 4, 0),
295 static const struct arm64_ftr_bits ftr_id_mmfr4
[] = {
296 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0), /* ac2 */
300 static const struct arm64_ftr_bits ftr_id_pfr0
[] = {
301 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 12, 4, 0), /* State3 */
302 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 8, 4, 0), /* State2 */
303 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0), /* State1 */
304 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0), /* State0 */
308 static const struct arm64_ftr_bits ftr_id_dfr0
[] = {
309 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 28, 4, 0),
310 S_ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 24, 4, 0xf), /* PerfMon */
311 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 20, 4, 0),
312 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 16, 4, 0),
313 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 12, 4, 0),
314 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 8, 4, 0),
315 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0),
316 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0),
320 static const struct arm64_ftr_bits ftr_zcr
[] = {
321 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
,
322 ZCR_ELx_LEN_SHIFT
, ZCR_ELx_LEN_SIZE
, 0), /* LEN */
327 * Common ftr bits for a 32bit register with all hidden, strict
328 * attributes, with 4bit feature fields and a default safe value of
329 * 0. Covers the following 32bit registers:
330 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
332 static const struct arm64_ftr_bits ftr_generic_32bits
[] = {
333 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 28, 4, 0),
334 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 24, 4, 0),
335 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 20, 4, 0),
336 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 16, 4, 0),
337 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 12, 4, 0),
338 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 8, 4, 0),
339 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0),
340 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0),
344 /* Table for a single 32bit feature value */
345 static const struct arm64_ftr_bits ftr_single32
[] = {
346 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_EXACT
, 0, 32, 0),
350 static const struct arm64_ftr_bits ftr_raz
[] = {
354 #define ARM64_FTR_REG(id, table) { \
356 .reg = &(struct arm64_ftr_reg){ \
358 .ftr_bits = &((table)[0]), \
361 static const struct __ftr_reg_entry
{
363 struct arm64_ftr_reg
*reg
;
364 } arm64_ftr_regs
[] = {
366 /* Op1 = 0, CRn = 0, CRm = 1 */
367 ARM64_FTR_REG(SYS_ID_PFR0_EL1
, ftr_id_pfr0
),
368 ARM64_FTR_REG(SYS_ID_PFR1_EL1
, ftr_generic_32bits
),
369 ARM64_FTR_REG(SYS_ID_DFR0_EL1
, ftr_id_dfr0
),
370 ARM64_FTR_REG(SYS_ID_MMFR0_EL1
, ftr_id_mmfr0
),
371 ARM64_FTR_REG(SYS_ID_MMFR1_EL1
, ftr_generic_32bits
),
372 ARM64_FTR_REG(SYS_ID_MMFR2_EL1
, ftr_generic_32bits
),
373 ARM64_FTR_REG(SYS_ID_MMFR3_EL1
, ftr_generic_32bits
),
375 /* Op1 = 0, CRn = 0, CRm = 2 */
376 ARM64_FTR_REG(SYS_ID_ISAR0_EL1
, ftr_generic_32bits
),
377 ARM64_FTR_REG(SYS_ID_ISAR1_EL1
, ftr_generic_32bits
),
378 ARM64_FTR_REG(SYS_ID_ISAR2_EL1
, ftr_generic_32bits
),
379 ARM64_FTR_REG(SYS_ID_ISAR3_EL1
, ftr_generic_32bits
),
380 ARM64_FTR_REG(SYS_ID_ISAR4_EL1
, ftr_generic_32bits
),
381 ARM64_FTR_REG(SYS_ID_ISAR5_EL1
, ftr_id_isar5
),
382 ARM64_FTR_REG(SYS_ID_MMFR4_EL1
, ftr_id_mmfr4
),
384 /* Op1 = 0, CRn = 0, CRm = 3 */
385 ARM64_FTR_REG(SYS_MVFR0_EL1
, ftr_generic_32bits
),
386 ARM64_FTR_REG(SYS_MVFR1_EL1
, ftr_generic_32bits
),
387 ARM64_FTR_REG(SYS_MVFR2_EL1
, ftr_mvfr2
),
389 /* Op1 = 0, CRn = 0, CRm = 4 */
390 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1
, ftr_id_aa64pfr0
),
391 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1
, ftr_id_aa64pfr1
),
392 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1
, ftr_raz
),
394 /* Op1 = 0, CRn = 0, CRm = 5 */
395 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1
, ftr_id_aa64dfr0
),
396 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1
, ftr_raz
),
398 /* Op1 = 0, CRn = 0, CRm = 6 */
399 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1
, ftr_id_aa64isar0
),
400 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1
, ftr_id_aa64isar1
),
402 /* Op1 = 0, CRn = 0, CRm = 7 */
403 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1
, ftr_id_aa64mmfr0
),
404 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1
, ftr_id_aa64mmfr1
),
405 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1
, ftr_id_aa64mmfr2
),
407 /* Op1 = 0, CRn = 1, CRm = 2 */
408 ARM64_FTR_REG(SYS_ZCR_EL1
, ftr_zcr
),
410 /* Op1 = 3, CRn = 0, CRm = 0 */
411 { SYS_CTR_EL0
, &arm64_ftr_reg_ctrel0
},
412 ARM64_FTR_REG(SYS_DCZID_EL0
, ftr_dczid
),
414 /* Op1 = 3, CRn = 14, CRm = 0 */
415 ARM64_FTR_REG(SYS_CNTFRQ_EL0
, ftr_single32
),
418 static int search_cmp_ftr_reg(const void *id
, const void *regp
)
420 return (int)(unsigned long)id
- (int)((const struct __ftr_reg_entry
*)regp
)->sys_id
;
424 * get_arm64_ftr_reg - Lookup a feature register entry using its
425 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
426 * ascending order of sys_id , we use binary search to find a matching
429 * returns - Upon success, matching ftr_reg entry for id.
430 * - NULL on failure. It is upto the caller to decide
431 * the impact of a failure.
433 static struct arm64_ftr_reg
*get_arm64_ftr_reg(u32 sys_id
)
435 const struct __ftr_reg_entry
*ret
;
437 ret
= bsearch((const void *)(unsigned long)sys_id
,
439 ARRAY_SIZE(arm64_ftr_regs
),
440 sizeof(arm64_ftr_regs
[0]),
447 static u64
arm64_ftr_set_value(const struct arm64_ftr_bits
*ftrp
, s64 reg
,
450 u64 mask
= arm64_ftr_mask(ftrp
);
453 reg
|= (ftr_val
<< ftrp
->shift
) & mask
;
457 static s64
arm64_ftr_safe_value(const struct arm64_ftr_bits
*ftrp
, s64
new,
462 switch (ftrp
->type
) {
464 ret
= ftrp
->safe_val
;
467 ret
= new < cur
? new : cur
;
469 case FTR_HIGHER_SAFE
:
470 ret
= new > cur
? new : cur
;
479 static void __init
sort_ftr_regs(void)
483 /* Check that the array is sorted so that we can do the binary search */
484 for (i
= 1; i
< ARRAY_SIZE(arm64_ftr_regs
); i
++)
485 BUG_ON(arm64_ftr_regs
[i
].sys_id
< arm64_ftr_regs
[i
- 1].sys_id
);
489 * Initialise the CPU feature register from Boot CPU values.
490 * Also initiliases the strict_mask for the register.
491 * Any bits that are not covered by an arm64_ftr_bits entry are considered
492 * RES0 for the system-wide value, and must strictly match.
494 static void __init
init_cpu_ftr_reg(u32 sys_reg
, u64
new)
497 u64 strict_mask
= ~0x0ULL
;
501 const struct arm64_ftr_bits
*ftrp
;
502 struct arm64_ftr_reg
*reg
= get_arm64_ftr_reg(sys_reg
);
506 for (ftrp
= reg
->ftr_bits
; ftrp
->width
; ftrp
++) {
507 u64 ftr_mask
= arm64_ftr_mask(ftrp
);
508 s64 ftr_new
= arm64_ftr_value(ftrp
, new);
510 val
= arm64_ftr_set_value(ftrp
, val
, ftr_new
);
512 valid_mask
|= ftr_mask
;
514 strict_mask
&= ~ftr_mask
;
516 user_mask
|= ftr_mask
;
518 reg
->user_val
= arm64_ftr_set_value(ftrp
,
526 reg
->strict_mask
= strict_mask
;
527 reg
->user_mask
= user_mask
;
530 extern const struct arm64_cpu_capabilities arm64_errata
[];
531 static const struct arm64_cpu_capabilities arm64_features
[];
534 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities
*caps
)
536 for (; caps
->matches
; caps
++) {
537 if (WARN(caps
->capability
>= ARM64_NCAPS
,
538 "Invalid capability %d\n", caps
->capability
))
540 if (WARN(cpu_hwcaps_ptrs
[caps
->capability
],
541 "Duplicate entry for capability %d\n",
544 cpu_hwcaps_ptrs
[caps
->capability
] = caps
;
548 static void __init
init_cpu_hwcaps_indirect_list(void)
550 init_cpu_hwcaps_indirect_list_from_array(arm64_features
);
551 init_cpu_hwcaps_indirect_list_from_array(arm64_errata
);
554 static void __init
setup_boot_cpu_capabilities(void);
556 void __init
init_cpu_features(struct cpuinfo_arm64
*info
)
558 /* Before we start using the tables, make sure it is sorted */
561 init_cpu_ftr_reg(SYS_CTR_EL0
, info
->reg_ctr
);
562 init_cpu_ftr_reg(SYS_DCZID_EL0
, info
->reg_dczid
);
563 init_cpu_ftr_reg(SYS_CNTFRQ_EL0
, info
->reg_cntfrq
);
564 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1
, info
->reg_id_aa64dfr0
);
565 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1
, info
->reg_id_aa64dfr1
);
566 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1
, info
->reg_id_aa64isar0
);
567 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1
, info
->reg_id_aa64isar1
);
568 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1
, info
->reg_id_aa64mmfr0
);
569 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1
, info
->reg_id_aa64mmfr1
);
570 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1
, info
->reg_id_aa64mmfr2
);
571 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1
, info
->reg_id_aa64pfr0
);
572 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1
, info
->reg_id_aa64pfr1
);
573 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1
, info
->reg_id_aa64zfr0
);
575 if (id_aa64pfr0_32bit_el0(info
->reg_id_aa64pfr0
)) {
576 init_cpu_ftr_reg(SYS_ID_DFR0_EL1
, info
->reg_id_dfr0
);
577 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1
, info
->reg_id_isar0
);
578 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1
, info
->reg_id_isar1
);
579 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1
, info
->reg_id_isar2
);
580 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1
, info
->reg_id_isar3
);
581 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1
, info
->reg_id_isar4
);
582 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1
, info
->reg_id_isar5
);
583 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1
, info
->reg_id_mmfr0
);
584 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1
, info
->reg_id_mmfr1
);
585 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1
, info
->reg_id_mmfr2
);
586 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1
, info
->reg_id_mmfr3
);
587 init_cpu_ftr_reg(SYS_ID_PFR0_EL1
, info
->reg_id_pfr0
);
588 init_cpu_ftr_reg(SYS_ID_PFR1_EL1
, info
->reg_id_pfr1
);
589 init_cpu_ftr_reg(SYS_MVFR0_EL1
, info
->reg_mvfr0
);
590 init_cpu_ftr_reg(SYS_MVFR1_EL1
, info
->reg_mvfr1
);
591 init_cpu_ftr_reg(SYS_MVFR2_EL1
, info
->reg_mvfr2
);
594 if (id_aa64pfr0_sve(info
->reg_id_aa64pfr0
)) {
595 init_cpu_ftr_reg(SYS_ZCR_EL1
, info
->reg_zcr
);
600 * Initialize the indirect array of CPU hwcaps capabilities pointers
601 * before we handle the boot CPU below.
603 init_cpu_hwcaps_indirect_list();
606 * Detect and enable early CPU capabilities based on the boot CPU,
607 * after we have initialised the CPU feature infrastructure.
609 setup_boot_cpu_capabilities();
612 static void update_cpu_ftr_reg(struct arm64_ftr_reg
*reg
, u64
new)
614 const struct arm64_ftr_bits
*ftrp
;
616 for (ftrp
= reg
->ftr_bits
; ftrp
->width
; ftrp
++) {
617 s64 ftr_cur
= arm64_ftr_value(ftrp
, reg
->sys_val
);
618 s64 ftr_new
= arm64_ftr_value(ftrp
, new);
620 if (ftr_cur
== ftr_new
)
622 /* Find a safe value */
623 ftr_new
= arm64_ftr_safe_value(ftrp
, ftr_new
, ftr_cur
);
624 reg
->sys_val
= arm64_ftr_set_value(ftrp
, reg
->sys_val
, ftr_new
);
629 static int check_update_ftr_reg(u32 sys_id
, int cpu
, u64 val
, u64 boot
)
631 struct arm64_ftr_reg
*regp
= get_arm64_ftr_reg(sys_id
);
634 update_cpu_ftr_reg(regp
, val
);
635 if ((boot
& regp
->strict_mask
) == (val
& regp
->strict_mask
))
637 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
638 regp
->name
, boot
, cpu
, val
);
643 * Update system wide CPU feature registers with the values from a
644 * non-boot CPU. Also performs SANITY checks to make sure that there
645 * aren't any insane variations from that of the boot CPU.
647 void update_cpu_features(int cpu
,
648 struct cpuinfo_arm64
*info
,
649 struct cpuinfo_arm64
*boot
)
654 * The kernel can handle differing I-cache policies, but otherwise
655 * caches should look identical. Userspace JITs will make use of
658 taint
|= check_update_ftr_reg(SYS_CTR_EL0
, cpu
,
659 info
->reg_ctr
, boot
->reg_ctr
);
662 * Userspace may perform DC ZVA instructions. Mismatched block sizes
663 * could result in too much or too little memory being zeroed if a
664 * process is preempted and migrated between CPUs.
666 taint
|= check_update_ftr_reg(SYS_DCZID_EL0
, cpu
,
667 info
->reg_dczid
, boot
->reg_dczid
);
669 /* If different, timekeeping will be broken (especially with KVM) */
670 taint
|= check_update_ftr_reg(SYS_CNTFRQ_EL0
, cpu
,
671 info
->reg_cntfrq
, boot
->reg_cntfrq
);
674 * The kernel uses self-hosted debug features and expects CPUs to
675 * support identical debug features. We presently need CTX_CMPs, WRPs,
676 * and BRPs to be identical.
677 * ID_AA64DFR1 is currently RES0.
679 taint
|= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1
, cpu
,
680 info
->reg_id_aa64dfr0
, boot
->reg_id_aa64dfr0
);
681 taint
|= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1
, cpu
,
682 info
->reg_id_aa64dfr1
, boot
->reg_id_aa64dfr1
);
684 * Even in big.LITTLE, processors should be identical instruction-set
687 taint
|= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1
, cpu
,
688 info
->reg_id_aa64isar0
, boot
->reg_id_aa64isar0
);
689 taint
|= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1
, cpu
,
690 info
->reg_id_aa64isar1
, boot
->reg_id_aa64isar1
);
693 * Differing PARange support is fine as long as all peripherals and
694 * memory are mapped within the minimum PARange of all CPUs.
695 * Linux should not care about secure memory.
697 taint
|= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1
, cpu
,
698 info
->reg_id_aa64mmfr0
, boot
->reg_id_aa64mmfr0
);
699 taint
|= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1
, cpu
,
700 info
->reg_id_aa64mmfr1
, boot
->reg_id_aa64mmfr1
);
701 taint
|= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1
, cpu
,
702 info
->reg_id_aa64mmfr2
, boot
->reg_id_aa64mmfr2
);
705 * EL3 is not our concern.
707 taint
|= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1
, cpu
,
708 info
->reg_id_aa64pfr0
, boot
->reg_id_aa64pfr0
);
709 taint
|= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1
, cpu
,
710 info
->reg_id_aa64pfr1
, boot
->reg_id_aa64pfr1
);
712 taint
|= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1
, cpu
,
713 info
->reg_id_aa64zfr0
, boot
->reg_id_aa64zfr0
);
716 * If we have AArch32, we care about 32-bit features for compat.
717 * If the system doesn't support AArch32, don't update them.
719 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1
)) &&
720 id_aa64pfr0_32bit_el0(info
->reg_id_aa64pfr0
)) {
722 taint
|= check_update_ftr_reg(SYS_ID_DFR0_EL1
, cpu
,
723 info
->reg_id_dfr0
, boot
->reg_id_dfr0
);
724 taint
|= check_update_ftr_reg(SYS_ID_ISAR0_EL1
, cpu
,
725 info
->reg_id_isar0
, boot
->reg_id_isar0
);
726 taint
|= check_update_ftr_reg(SYS_ID_ISAR1_EL1
, cpu
,
727 info
->reg_id_isar1
, boot
->reg_id_isar1
);
728 taint
|= check_update_ftr_reg(SYS_ID_ISAR2_EL1
, cpu
,
729 info
->reg_id_isar2
, boot
->reg_id_isar2
);
730 taint
|= check_update_ftr_reg(SYS_ID_ISAR3_EL1
, cpu
,
731 info
->reg_id_isar3
, boot
->reg_id_isar3
);
732 taint
|= check_update_ftr_reg(SYS_ID_ISAR4_EL1
, cpu
,
733 info
->reg_id_isar4
, boot
->reg_id_isar4
);
734 taint
|= check_update_ftr_reg(SYS_ID_ISAR5_EL1
, cpu
,
735 info
->reg_id_isar5
, boot
->reg_id_isar5
);
738 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
739 * ACTLR formats could differ across CPUs and therefore would have to
740 * be trapped for virtualization anyway.
742 taint
|= check_update_ftr_reg(SYS_ID_MMFR0_EL1
, cpu
,
743 info
->reg_id_mmfr0
, boot
->reg_id_mmfr0
);
744 taint
|= check_update_ftr_reg(SYS_ID_MMFR1_EL1
, cpu
,
745 info
->reg_id_mmfr1
, boot
->reg_id_mmfr1
);
746 taint
|= check_update_ftr_reg(SYS_ID_MMFR2_EL1
, cpu
,
747 info
->reg_id_mmfr2
, boot
->reg_id_mmfr2
);
748 taint
|= check_update_ftr_reg(SYS_ID_MMFR3_EL1
, cpu
,
749 info
->reg_id_mmfr3
, boot
->reg_id_mmfr3
);
750 taint
|= check_update_ftr_reg(SYS_ID_PFR0_EL1
, cpu
,
751 info
->reg_id_pfr0
, boot
->reg_id_pfr0
);
752 taint
|= check_update_ftr_reg(SYS_ID_PFR1_EL1
, cpu
,
753 info
->reg_id_pfr1
, boot
->reg_id_pfr1
);
754 taint
|= check_update_ftr_reg(SYS_MVFR0_EL1
, cpu
,
755 info
->reg_mvfr0
, boot
->reg_mvfr0
);
756 taint
|= check_update_ftr_reg(SYS_MVFR1_EL1
, cpu
,
757 info
->reg_mvfr1
, boot
->reg_mvfr1
);
758 taint
|= check_update_ftr_reg(SYS_MVFR2_EL1
, cpu
,
759 info
->reg_mvfr2
, boot
->reg_mvfr2
);
762 if (id_aa64pfr0_sve(info
->reg_id_aa64pfr0
)) {
763 taint
|= check_update_ftr_reg(SYS_ZCR_EL1
, cpu
,
764 info
->reg_zcr
, boot
->reg_zcr
);
766 /* Probe vector lengths, unless we already gave up on SVE */
767 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1
)) &&
768 !sys_caps_initialised
)
773 * Mismatched CPU features are a recipe for disaster. Don't even
774 * pretend to support them.
777 pr_warn_once("Unsupported CPU feature variation detected.\n");
778 add_taint(TAINT_CPU_OUT_OF_SPEC
, LOCKDEP_STILL_OK
);
782 u64
read_sanitised_ftr_reg(u32 id
)
784 struct arm64_ftr_reg
*regp
= get_arm64_ftr_reg(id
);
786 /* We shouldn't get a request for an unsupported register */
788 return regp
->sys_val
;
791 #define read_sysreg_case(r) \
792 case r: return read_sysreg_s(r)
795 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
796 * Read the system register on the current CPU
798 static u64
__read_sysreg_by_encoding(u32 sys_id
)
801 read_sysreg_case(SYS_ID_PFR0_EL1
);
802 read_sysreg_case(SYS_ID_PFR1_EL1
);
803 read_sysreg_case(SYS_ID_DFR0_EL1
);
804 read_sysreg_case(SYS_ID_MMFR0_EL1
);
805 read_sysreg_case(SYS_ID_MMFR1_EL1
);
806 read_sysreg_case(SYS_ID_MMFR2_EL1
);
807 read_sysreg_case(SYS_ID_MMFR3_EL1
);
808 read_sysreg_case(SYS_ID_ISAR0_EL1
);
809 read_sysreg_case(SYS_ID_ISAR1_EL1
);
810 read_sysreg_case(SYS_ID_ISAR2_EL1
);
811 read_sysreg_case(SYS_ID_ISAR3_EL1
);
812 read_sysreg_case(SYS_ID_ISAR4_EL1
);
813 read_sysreg_case(SYS_ID_ISAR5_EL1
);
814 read_sysreg_case(SYS_MVFR0_EL1
);
815 read_sysreg_case(SYS_MVFR1_EL1
);
816 read_sysreg_case(SYS_MVFR2_EL1
);
818 read_sysreg_case(SYS_ID_AA64PFR0_EL1
);
819 read_sysreg_case(SYS_ID_AA64PFR1_EL1
);
820 read_sysreg_case(SYS_ID_AA64DFR0_EL1
);
821 read_sysreg_case(SYS_ID_AA64DFR1_EL1
);
822 read_sysreg_case(SYS_ID_AA64MMFR0_EL1
);
823 read_sysreg_case(SYS_ID_AA64MMFR1_EL1
);
824 read_sysreg_case(SYS_ID_AA64MMFR2_EL1
);
825 read_sysreg_case(SYS_ID_AA64ISAR0_EL1
);
826 read_sysreg_case(SYS_ID_AA64ISAR1_EL1
);
828 read_sysreg_case(SYS_CNTFRQ_EL0
);
829 read_sysreg_case(SYS_CTR_EL0
);
830 read_sysreg_case(SYS_DCZID_EL0
);
838 #include <linux/irqchip/arm-gic-v3.h>
841 feature_matches(u64 reg
, const struct arm64_cpu_capabilities
*entry
)
843 int val
= cpuid_feature_extract_field(reg
, entry
->field_pos
, entry
->sign
);
845 return val
>= entry
->min_field_value
;
849 has_cpuid_feature(const struct arm64_cpu_capabilities
*entry
, int scope
)
853 WARN_ON(scope
== SCOPE_LOCAL_CPU
&& preemptible());
854 if (scope
== SCOPE_SYSTEM
)
855 val
= read_sanitised_ftr_reg(entry
->sys_reg
);
857 val
= __read_sysreg_by_encoding(entry
->sys_reg
);
859 return feature_matches(val
, entry
);
862 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities
*entry
, int scope
)
866 if (!has_cpuid_feature(entry
, scope
))
869 has_sre
= gic_enable_sre();
871 pr_warn_once("%s present but disabled by higher exception level\n",
877 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities
*entry
, int __unused
)
879 u32 midr
= read_cpuid_id();
881 /* Cavium ThunderX pass 1.x and 2.x */
882 return MIDR_IS_CPU_MODEL_RANGE(midr
, MIDR_THUNDERX
,
883 MIDR_CPU_VAR_REV(0, 0),
884 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK
));
887 static bool has_no_fpsimd(const struct arm64_cpu_capabilities
*entry
, int __unused
)
889 u64 pfr0
= read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1
);
891 return cpuid_feature_extract_signed_field(pfr0
,
892 ID_AA64PFR0_FP_SHIFT
) < 0;
895 static bool has_cache_idc(const struct arm64_cpu_capabilities
*entry
,
900 if (scope
== SCOPE_SYSTEM
)
901 ctr
= arm64_ftr_reg_ctrel0
.sys_val
;
903 ctr
= read_cpuid_effective_cachetype();
905 return ctr
& BIT(CTR_IDC_SHIFT
);
908 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities
*__unused
)
911 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
912 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
913 * to the CTR_EL0 on this CPU and emulate it with the real/safe
916 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT
)))
917 sysreg_clear_set(sctlr_el1
, SCTLR_EL1_UCT
, 0);
920 static bool has_cache_dic(const struct arm64_cpu_capabilities
*entry
,
925 if (scope
== SCOPE_SYSTEM
)
926 ctr
= arm64_ftr_reg_ctrel0
.sys_val
;
928 ctr
= read_cpuid_cachetype();
930 return ctr
& BIT(CTR_DIC_SHIFT
);
933 static bool __maybe_unused
934 has_useable_cnp(const struct arm64_cpu_capabilities
*entry
, int scope
)
937 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
938 * may share TLB entries with a CPU stuck in the crashed
941 if (is_kdump_kernel())
944 return has_cpuid_feature(entry
, scope
);
947 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
948 static int __kpti_forced
; /* 0: not forced, >0: forced on, <0: forced off */
950 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities
*entry
,
953 /* List of CPUs that are not vulnerable and don't need KPTI */
954 static const struct midr_range kpti_safe_list
[] = {
955 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2
),
956 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN
),
957 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35
),
958 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53
),
959 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55
),
960 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57
),
961 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72
),
962 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73
),
965 char const *str
= "command line option";
968 * For reasons that aren't entirely clear, enabling KPTI on Cavium
969 * ThunderX leads to apparent I-cache corruption of kernel text, which
970 * ends as well as you might imagine. Don't even try.
972 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456
)) {
973 str
= "ARM64_WORKAROUND_CAVIUM_27456";
979 pr_info_once("kernel page table isolation forced %s by %s\n",
980 __kpti_forced
> 0 ? "ON" : "OFF", str
);
981 return __kpti_forced
> 0;
984 /* Useful for KASLR robustness */
985 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE
))
988 /* Don't force KPTI for CPUs that are not vulnerable */
989 if (is_midr_in_range_list(read_cpuid_id(), kpti_safe_list
))
992 /* Defer to CPU feature registers */
993 return !has_cpuid_feature(entry
, scope
);
997 kpti_install_ng_mappings(const struct arm64_cpu_capabilities
*__unused
)
999 typedef void (kpti_remap_fn
)(int, int, phys_addr_t
);
1000 extern kpti_remap_fn idmap_kpti_install_ng_mappings
;
1001 kpti_remap_fn
*remap_fn
;
1003 static bool kpti_applied
= false;
1004 int cpu
= smp_processor_id();
1009 remap_fn
= (void *)__pa_symbol(idmap_kpti_install_ng_mappings
);
1011 cpu_install_idmap();
1012 remap_fn(cpu
, num_online_cpus(), __pa_symbol(swapper_pg_dir
));
1013 cpu_uninstall_idmap();
1016 kpti_applied
= true;
1021 static int __init
parse_kpti(char *str
)
1024 int ret
= strtobool(str
, &enabled
);
1029 __kpti_forced
= enabled
? 1 : -1;
1032 early_param("kpti", parse_kpti
);
1033 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1035 #ifdef CONFIG_ARM64_HW_AFDBM
1036 static inline void __cpu_enable_hw_dbm(void)
1038 u64 tcr
= read_sysreg(tcr_el1
) | TCR_HD
;
1040 write_sysreg(tcr
, tcr_el1
);
1044 static bool cpu_has_broken_dbm(void)
1046 /* List of CPUs which have broken DBM support. */
1047 static const struct midr_range cpus
[] = {
1048 #ifdef CONFIG_ARM64_ERRATUM_1024718
1049 MIDR_RANGE(MIDR_CORTEX_A55
, 0, 0, 1, 0), // A55 r0p0 -r1p0
1054 return is_midr_in_range_list(read_cpuid_id(), cpus
);
1057 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities
*cap
)
1059 return has_cpuid_feature(cap
, SCOPE_LOCAL_CPU
) &&
1060 !cpu_has_broken_dbm();
1063 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities
const *cap
)
1065 if (cpu_can_use_dbm(cap
))
1066 __cpu_enable_hw_dbm();
1069 static bool has_hw_dbm(const struct arm64_cpu_capabilities
*cap
,
1072 static bool detected
= false;
1074 * DBM is a non-conflicting feature. i.e, the kernel can safely
1075 * run a mix of CPUs with and without the feature. So, we
1076 * unconditionally enable the capability to allow any late CPU
1077 * to use the feature. We only enable the control bits on the
1078 * CPU, if it actually supports.
1080 * We have to make sure we print the "feature" detection only
1081 * when at least one CPU actually uses it. So check if this CPU
1082 * can actually use it and print the message exactly once.
1084 * This is safe as all CPUs (including secondary CPUs - due to the
1085 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1086 * goes through the "matches" check exactly once. Also if a CPU
1087 * matches the criteria, it is guaranteed that the CPU will turn
1088 * the DBM on, as the capability is unconditionally enabled.
1090 if (!detected
&& cpu_can_use_dbm(cap
)) {
1092 pr_info("detected: Hardware dirty bit management\n");
1100 #ifdef CONFIG_ARM64_VHE
1101 static bool runs_at_el2(const struct arm64_cpu_capabilities
*entry
, int __unused
)
1103 return is_kernel_in_hyp_mode();
1106 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities
*__unused
)
1109 * Copy register values that aren't redirected by hardware.
1111 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1112 * this value to tpidr_el2 before we patch the code. Once we've done
1113 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1116 if (!alternatives_applied
)
1117 write_sysreg(read_sysreg(tpidr_el1
), tpidr_el2
);
1121 static void cpu_has_fwb(const struct arm64_cpu_capabilities
*__unused
)
1123 u64 val
= read_sysreg_s(SYS_CLIDR_EL1
);
1125 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1126 WARN_ON(val
& (7 << 27 | 7 << 21));
1129 #ifdef CONFIG_ARM64_SSBD
1130 static int ssbs_emulation_handler(struct pt_regs
*regs
, u32 instr
)
1132 if (user_mode(regs
))
1135 if (instr
& BIT(PSTATE_Imm_shift
))
1136 regs
->pstate
|= PSR_SSBS_BIT
;
1138 regs
->pstate
&= ~PSR_SSBS_BIT
;
1140 arm64_skip_faulting_instruction(regs
, 4);
1144 static struct undef_hook ssbs_emulation_hook
= {
1145 .instr_mask
= ~(1U << PSTATE_Imm_shift
),
1146 .instr_val
= 0xd500401f | PSTATE_SSBS
,
1147 .fn
= ssbs_emulation_handler
,
1150 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities
*__unused
)
1152 static bool undef_hook_registered
= false;
1153 static DEFINE_SPINLOCK(hook_lock
);
1155 spin_lock(&hook_lock
);
1156 if (!undef_hook_registered
) {
1157 register_undef_hook(&ssbs_emulation_hook
);
1158 undef_hook_registered
= true;
1160 spin_unlock(&hook_lock
);
1162 if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE
) {
1163 sysreg_clear_set(sctlr_el1
, 0, SCTLR_ELx_DSSBS
);
1164 arm64_set_ssbd_mitigation(false);
1166 arm64_set_ssbd_mitigation(true);
1169 #endif /* CONFIG_ARM64_SSBD */
1171 #ifdef CONFIG_ARM64_PAN
1172 static void cpu_enable_pan(const struct arm64_cpu_capabilities
*__unused
)
1175 * We modify PSTATE. This won't work from irq context as the PSTATE
1176 * is discarded once we return from the exception.
1178 WARN_ON_ONCE(in_interrupt());
1180 sysreg_clear_set(sctlr_el1
, SCTLR_EL1_SPAN
, 0);
1181 asm(SET_PSTATE_PAN(1));
1183 #endif /* CONFIG_ARM64_PAN */
1185 #ifdef CONFIG_ARM64_RAS_EXTN
1186 static void cpu_clear_disr(const struct arm64_cpu_capabilities
*__unused
)
1188 /* Firmware may have left a deferred SError in this register. */
1189 write_sysreg_s(0, SYS_DISR_EL1
);
1191 #endif /* CONFIG_ARM64_RAS_EXTN */
1193 #ifdef CONFIG_ARM64_PTR_AUTH
1194 static void cpu_enable_address_auth(struct arm64_cpu_capabilities
const *cap
)
1196 sysreg_clear_set(sctlr_el1
, 0, SCTLR_ELx_ENIA
| SCTLR_ELx_ENIB
|
1197 SCTLR_ELx_ENDA
| SCTLR_ELx_ENDB
);
1199 #endif /* CONFIG_ARM64_PTR_AUTH */
1201 static const struct arm64_cpu_capabilities arm64_features
[] = {
1203 .desc
= "GIC system register CPU interface",
1204 .capability
= ARM64_HAS_SYSREG_GIC_CPUIF
,
1205 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1206 .matches
= has_useable_gicv3_cpuif
,
1207 .sys_reg
= SYS_ID_AA64PFR0_EL1
,
1208 .field_pos
= ID_AA64PFR0_GIC_SHIFT
,
1209 .sign
= FTR_UNSIGNED
,
1210 .min_field_value
= 1,
1212 #ifdef CONFIG_ARM64_PAN
1214 .desc
= "Privileged Access Never",
1215 .capability
= ARM64_HAS_PAN
,
1216 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1217 .matches
= has_cpuid_feature
,
1218 .sys_reg
= SYS_ID_AA64MMFR1_EL1
,
1219 .field_pos
= ID_AA64MMFR1_PAN_SHIFT
,
1220 .sign
= FTR_UNSIGNED
,
1221 .min_field_value
= 1,
1222 .cpu_enable
= cpu_enable_pan
,
1224 #endif /* CONFIG_ARM64_PAN */
1225 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1227 .desc
= "LSE atomic instructions",
1228 .capability
= ARM64_HAS_LSE_ATOMICS
,
1229 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1230 .matches
= has_cpuid_feature
,
1231 .sys_reg
= SYS_ID_AA64ISAR0_EL1
,
1232 .field_pos
= ID_AA64ISAR0_ATOMICS_SHIFT
,
1233 .sign
= FTR_UNSIGNED
,
1234 .min_field_value
= 2,
1236 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1238 .desc
= "Software prefetching using PRFM",
1239 .capability
= ARM64_HAS_NO_HW_PREFETCH
,
1240 .type
= ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE
,
1241 .matches
= has_no_hw_prefetch
,
1243 #ifdef CONFIG_ARM64_UAO
1245 .desc
= "User Access Override",
1246 .capability
= ARM64_HAS_UAO
,
1247 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1248 .matches
= has_cpuid_feature
,
1249 .sys_reg
= SYS_ID_AA64MMFR2_EL1
,
1250 .field_pos
= ID_AA64MMFR2_UAO_SHIFT
,
1251 .min_field_value
= 1,
1253 * We rely on stop_machine() calling uao_thread_switch() to set
1254 * UAO immediately after patching.
1257 #endif /* CONFIG_ARM64_UAO */
1258 #ifdef CONFIG_ARM64_PAN
1260 .capability
= ARM64_ALT_PAN_NOT_UAO
,
1261 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1262 .matches
= cpufeature_pan_not_uao
,
1264 #endif /* CONFIG_ARM64_PAN */
1265 #ifdef CONFIG_ARM64_VHE
1267 .desc
= "Virtualization Host Extensions",
1268 .capability
= ARM64_HAS_VIRT_HOST_EXTN
,
1269 .type
= ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE
,
1270 .matches
= runs_at_el2
,
1271 .cpu_enable
= cpu_copy_el2regs
,
1273 #endif /* CONFIG_ARM64_VHE */
1275 .desc
= "32-bit EL0 Support",
1276 .capability
= ARM64_HAS_32BIT_EL0
,
1277 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1278 .matches
= has_cpuid_feature
,
1279 .sys_reg
= SYS_ID_AA64PFR0_EL1
,
1280 .sign
= FTR_UNSIGNED
,
1281 .field_pos
= ID_AA64PFR0_EL0_SHIFT
,
1282 .min_field_value
= ID_AA64PFR0_EL0_32BIT_64BIT
,
1284 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1286 .desc
= "Kernel page table isolation (KPTI)",
1287 .capability
= ARM64_UNMAP_KERNEL_AT_EL0
,
1288 .type
= ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE
,
1290 * The ID feature fields below are used to indicate that
1291 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1294 .sys_reg
= SYS_ID_AA64PFR0_EL1
,
1295 .field_pos
= ID_AA64PFR0_CSV3_SHIFT
,
1296 .min_field_value
= 1,
1297 .matches
= unmap_kernel_at_el0
,
1298 .cpu_enable
= kpti_install_ng_mappings
,
1302 /* FP/SIMD is not implemented */
1303 .capability
= ARM64_HAS_NO_FPSIMD
,
1304 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1305 .min_field_value
= 0,
1306 .matches
= has_no_fpsimd
,
1308 #ifdef CONFIG_ARM64_PMEM
1310 .desc
= "Data cache clean to Point of Persistence",
1311 .capability
= ARM64_HAS_DCPOP
,
1312 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1313 .matches
= has_cpuid_feature
,
1314 .sys_reg
= SYS_ID_AA64ISAR1_EL1
,
1315 .field_pos
= ID_AA64ISAR1_DPB_SHIFT
,
1316 .min_field_value
= 1,
1319 #ifdef CONFIG_ARM64_SVE
1321 .desc
= "Scalable Vector Extension",
1322 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1323 .capability
= ARM64_SVE
,
1324 .sys_reg
= SYS_ID_AA64PFR0_EL1
,
1325 .sign
= FTR_UNSIGNED
,
1326 .field_pos
= ID_AA64PFR0_SVE_SHIFT
,
1327 .min_field_value
= ID_AA64PFR0_SVE
,
1328 .matches
= has_cpuid_feature
,
1329 .cpu_enable
= sve_kernel_enable
,
1331 #endif /* CONFIG_ARM64_SVE */
1332 #ifdef CONFIG_ARM64_RAS_EXTN
1334 .desc
= "RAS Extension Support",
1335 .capability
= ARM64_HAS_RAS_EXTN
,
1336 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1337 .matches
= has_cpuid_feature
,
1338 .sys_reg
= SYS_ID_AA64PFR0_EL1
,
1339 .sign
= FTR_UNSIGNED
,
1340 .field_pos
= ID_AA64PFR0_RAS_SHIFT
,
1341 .min_field_value
= ID_AA64PFR0_RAS_V1
,
1342 .cpu_enable
= cpu_clear_disr
,
1344 #endif /* CONFIG_ARM64_RAS_EXTN */
1346 .desc
= "Data cache clean to the PoU not required for I/D coherence",
1347 .capability
= ARM64_HAS_CACHE_IDC
,
1348 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1349 .matches
= has_cache_idc
,
1350 .cpu_enable
= cpu_emulate_effective_ctr
,
1353 .desc
= "Instruction cache invalidation not required for I/D coherence",
1354 .capability
= ARM64_HAS_CACHE_DIC
,
1355 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1356 .matches
= has_cache_dic
,
1359 .desc
= "Stage-2 Force Write-Back",
1360 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1361 .capability
= ARM64_HAS_STAGE2_FWB
,
1362 .sys_reg
= SYS_ID_AA64MMFR2_EL1
,
1363 .sign
= FTR_UNSIGNED
,
1364 .field_pos
= ID_AA64MMFR2_FWB_SHIFT
,
1365 .min_field_value
= 1,
1366 .matches
= has_cpuid_feature
,
1367 .cpu_enable
= cpu_has_fwb
,
1369 #ifdef CONFIG_ARM64_HW_AFDBM
1372 * Since we turn this on always, we don't want the user to
1373 * think that the feature is available when it may not be.
1374 * So hide the description.
1376 * .desc = "Hardware pagetable Dirty Bit Management",
1379 .type
= ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE
,
1380 .capability
= ARM64_HW_DBM
,
1381 .sys_reg
= SYS_ID_AA64MMFR1_EL1
,
1382 .sign
= FTR_UNSIGNED
,
1383 .field_pos
= ID_AA64MMFR1_HADBS_SHIFT
,
1384 .min_field_value
= 2,
1385 .matches
= has_hw_dbm
,
1386 .cpu_enable
= cpu_enable_hw_dbm
,
1390 .desc
= "CRC32 instructions",
1391 .capability
= ARM64_HAS_CRC32
,
1392 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1393 .matches
= has_cpuid_feature
,
1394 .sys_reg
= SYS_ID_AA64ISAR0_EL1
,
1395 .field_pos
= ID_AA64ISAR0_CRC32_SHIFT
,
1396 .min_field_value
= 1,
1398 #ifdef CONFIG_ARM64_SSBD
1400 .desc
= "Speculative Store Bypassing Safe (SSBS)",
1401 .capability
= ARM64_SSBS
,
1402 .type
= ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE
,
1403 .matches
= has_cpuid_feature
,
1404 .sys_reg
= SYS_ID_AA64PFR1_EL1
,
1405 .field_pos
= ID_AA64PFR1_SSBS_SHIFT
,
1406 .sign
= FTR_UNSIGNED
,
1407 .min_field_value
= ID_AA64PFR1_SSBS_PSTATE_ONLY
,
1408 .cpu_enable
= cpu_enable_ssbs
,
1411 #ifdef CONFIG_ARM64_CNP
1413 .desc
= "Common not Private translations",
1414 .capability
= ARM64_HAS_CNP
,
1415 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1416 .matches
= has_useable_cnp
,
1417 .sys_reg
= SYS_ID_AA64MMFR2_EL1
,
1418 .sign
= FTR_UNSIGNED
,
1419 .field_pos
= ID_AA64MMFR2_CNP_SHIFT
,
1420 .min_field_value
= 1,
1421 .cpu_enable
= cpu_enable_cnp
,
1425 .desc
= "Speculation barrier (SB)",
1426 .capability
= ARM64_HAS_SB
,
1427 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1428 .matches
= has_cpuid_feature
,
1429 .sys_reg
= SYS_ID_AA64ISAR1_EL1
,
1430 .field_pos
= ID_AA64ISAR1_SB_SHIFT
,
1431 .sign
= FTR_UNSIGNED
,
1432 .min_field_value
= 1,
1434 #ifdef CONFIG_ARM64_PTR_AUTH
1436 .desc
= "Address authentication (architected algorithm)",
1437 .capability
= ARM64_HAS_ADDRESS_AUTH_ARCH
,
1438 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1439 .sys_reg
= SYS_ID_AA64ISAR1_EL1
,
1440 .sign
= FTR_UNSIGNED
,
1441 .field_pos
= ID_AA64ISAR1_APA_SHIFT
,
1442 .min_field_value
= ID_AA64ISAR1_APA_ARCHITECTED
,
1443 .matches
= has_cpuid_feature
,
1444 .cpu_enable
= cpu_enable_address_auth
,
1447 .desc
= "Address authentication (IMP DEF algorithm)",
1448 .capability
= ARM64_HAS_ADDRESS_AUTH_IMP_DEF
,
1449 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1450 .sys_reg
= SYS_ID_AA64ISAR1_EL1
,
1451 .sign
= FTR_UNSIGNED
,
1452 .field_pos
= ID_AA64ISAR1_API_SHIFT
,
1453 .min_field_value
= ID_AA64ISAR1_API_IMP_DEF
,
1454 .matches
= has_cpuid_feature
,
1455 .cpu_enable
= cpu_enable_address_auth
,
1458 .desc
= "Generic authentication (architected algorithm)",
1459 .capability
= ARM64_HAS_GENERIC_AUTH_ARCH
,
1460 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1461 .sys_reg
= SYS_ID_AA64ISAR1_EL1
,
1462 .sign
= FTR_UNSIGNED
,
1463 .field_pos
= ID_AA64ISAR1_GPA_SHIFT
,
1464 .min_field_value
= ID_AA64ISAR1_GPA_ARCHITECTED
,
1465 .matches
= has_cpuid_feature
,
1468 .desc
= "Generic authentication (IMP DEF algorithm)",
1469 .capability
= ARM64_HAS_GENERIC_AUTH_IMP_DEF
,
1470 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1471 .sys_reg
= SYS_ID_AA64ISAR1_EL1
,
1472 .sign
= FTR_UNSIGNED
,
1473 .field_pos
= ID_AA64ISAR1_GPI_SHIFT
,
1474 .min_field_value
= ID_AA64ISAR1_GPI_IMP_DEF
,
1475 .matches
= has_cpuid_feature
,
1477 #endif /* CONFIG_ARM64_PTR_AUTH */
1481 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
1482 .matches = has_cpuid_feature, \
1484 .field_pos = field, \
1486 .min_field_value = min_value,
1488 #define __HWCAP_CAP(name, cap_type, cap) \
1490 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
1491 .hwcap_type = cap_type, \
1494 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
1496 __HWCAP_CAP(#cap, cap_type, cap) \
1497 HWCAP_CPUID_MATCH(reg, field, s, min_value) \
1500 #define HWCAP_MULTI_CAP(list, cap_type, cap) \
1502 __HWCAP_CAP(#cap, cap_type, cap) \
1503 .matches = cpucap_multi_entry_cap_matches, \
1504 .match_list = list, \
1507 #ifdef CONFIG_ARM64_PTR_AUTH
1508 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches
[] = {
1510 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1
, ID_AA64ISAR1_APA_SHIFT
,
1511 FTR_UNSIGNED
, ID_AA64ISAR1_APA_ARCHITECTED
)
1514 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1
, ID_AA64ISAR1_API_SHIFT
,
1515 FTR_UNSIGNED
, ID_AA64ISAR1_API_IMP_DEF
)
1520 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches
[] = {
1522 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1
, ID_AA64ISAR1_GPA_SHIFT
,
1523 FTR_UNSIGNED
, ID_AA64ISAR1_GPA_ARCHITECTED
)
1526 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1
, ID_AA64ISAR1_GPI_SHIFT
,
1527 FTR_UNSIGNED
, ID_AA64ISAR1_GPI_IMP_DEF
)
1533 static const struct arm64_cpu_capabilities arm64_elf_hwcaps
[] = {
1534 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_AES_SHIFT
, FTR_UNSIGNED
, 2, CAP_HWCAP
, HWCAP_PMULL
),
1535 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_AES_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_AES
),
1536 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SHA1_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_SHA1
),
1537 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SHA2_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_SHA2
),
1538 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SHA2_SHIFT
, FTR_UNSIGNED
, 2, CAP_HWCAP
, HWCAP_SHA512
),
1539 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_CRC32_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_CRC32
),
1540 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_ATOMICS_SHIFT
, FTR_UNSIGNED
, 2, CAP_HWCAP
, HWCAP_ATOMICS
),
1541 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_RDM_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_ASIMDRDM
),
1542 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SHA3_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_SHA3
),
1543 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SM3_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_SM3
),
1544 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SM4_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_SM4
),
1545 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_DP_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_ASIMDDP
),
1546 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_FHM_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_ASIMDFHM
),
1547 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_TS_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_FLAGM
),
1548 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_FP_SHIFT
, FTR_SIGNED
, 0, CAP_HWCAP
, HWCAP_FP
),
1549 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_FP_SHIFT
, FTR_SIGNED
, 1, CAP_HWCAP
, HWCAP_FPHP
),
1550 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_ASIMD_SHIFT
, FTR_SIGNED
, 0, CAP_HWCAP
, HWCAP_ASIMD
),
1551 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_ASIMD_SHIFT
, FTR_SIGNED
, 1, CAP_HWCAP
, HWCAP_ASIMDHP
),
1552 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_DIT_SHIFT
, FTR_SIGNED
, 1, CAP_HWCAP
, HWCAP_DIT
),
1553 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1
, ID_AA64ISAR1_DPB_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_DCPOP
),
1554 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1
, ID_AA64ISAR1_JSCVT_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_JSCVT
),
1555 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1
, ID_AA64ISAR1_FCMA_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_FCMA
),
1556 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1
, ID_AA64ISAR1_LRCPC_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_LRCPC
),
1557 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1
, ID_AA64ISAR1_LRCPC_SHIFT
, FTR_UNSIGNED
, 2, CAP_HWCAP
, HWCAP_ILRCPC
),
1558 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1
, ID_AA64ISAR1_SB_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_SB
),
1559 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1
, ID_AA64MMFR2_AT_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_USCAT
),
1560 #ifdef CONFIG_ARM64_SVE
1561 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_SVE_SHIFT
, FTR_UNSIGNED
, ID_AA64PFR0_SVE
, CAP_HWCAP
, HWCAP_SVE
),
1563 HWCAP_CAP(SYS_ID_AA64PFR1_EL1
, ID_AA64PFR1_SSBS_SHIFT
, FTR_UNSIGNED
, ID_AA64PFR1_SSBS_PSTATE_INSNS
, CAP_HWCAP
, HWCAP_SSBS
),
1564 #ifdef CONFIG_ARM64_PTR_AUTH
1565 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches
, CAP_HWCAP
, HWCAP_PACA
),
1566 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches
, CAP_HWCAP
, HWCAP_PACG
),
1571 static const struct arm64_cpu_capabilities compat_elf_hwcaps
[] = {
1572 #ifdef CONFIG_COMPAT
1573 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_AES_SHIFT
, FTR_UNSIGNED
, 2, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_PMULL
),
1574 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_AES_SHIFT
, FTR_UNSIGNED
, 1, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_AES
),
1575 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_SHA1_SHIFT
, FTR_UNSIGNED
, 1, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_SHA1
),
1576 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_SHA2_SHIFT
, FTR_UNSIGNED
, 1, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_SHA2
),
1577 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_CRC32_SHIFT
, FTR_UNSIGNED
, 1, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_CRC32
),
1582 static void __init
cap_set_elf_hwcap(const struct arm64_cpu_capabilities
*cap
)
1584 switch (cap
->hwcap_type
) {
1586 elf_hwcap
|= cap
->hwcap
;
1588 #ifdef CONFIG_COMPAT
1589 case CAP_COMPAT_HWCAP
:
1590 compat_elf_hwcap
|= (u32
)cap
->hwcap
;
1592 case CAP_COMPAT_HWCAP2
:
1593 compat_elf_hwcap2
|= (u32
)cap
->hwcap
;
1602 /* Check if we have a particular HWCAP enabled */
1603 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities
*cap
)
1607 switch (cap
->hwcap_type
) {
1609 rc
= (elf_hwcap
& cap
->hwcap
) != 0;
1611 #ifdef CONFIG_COMPAT
1612 case CAP_COMPAT_HWCAP
:
1613 rc
= (compat_elf_hwcap
& (u32
)cap
->hwcap
) != 0;
1615 case CAP_COMPAT_HWCAP2
:
1616 rc
= (compat_elf_hwcap2
& (u32
)cap
->hwcap
) != 0;
1627 static void __init
setup_elf_hwcaps(const struct arm64_cpu_capabilities
*hwcaps
)
1629 /* We support emulation of accesses to CPU ID feature registers */
1630 elf_hwcap
|= HWCAP_CPUID
;
1631 for (; hwcaps
->matches
; hwcaps
++)
1632 if (hwcaps
->matches(hwcaps
, cpucap_default_scope(hwcaps
)))
1633 cap_set_elf_hwcap(hwcaps
);
1636 static void update_cpu_capabilities(u16 scope_mask
)
1639 const struct arm64_cpu_capabilities
*caps
;
1641 scope_mask
&= ARM64_CPUCAP_SCOPE_MASK
;
1642 for (i
= 0; i
< ARM64_NCAPS
; i
++) {
1643 caps
= cpu_hwcaps_ptrs
[i
];
1644 if (!caps
|| !(caps
->type
& scope_mask
) ||
1645 cpus_have_cap(caps
->capability
) ||
1646 !caps
->matches(caps
, cpucap_default_scope(caps
)))
1650 pr_info("detected: %s\n", caps
->desc
);
1651 cpus_set_cap(caps
->capability
);
1656 * Enable all the available capabilities on this CPU. The capabilities
1657 * with BOOT_CPU scope are handled separately and hence skipped here.
1659 static int cpu_enable_non_boot_scope_capabilities(void *__unused
)
1662 u16 non_boot_scope
= SCOPE_ALL
& ~SCOPE_BOOT_CPU
;
1664 for_each_available_cap(i
) {
1665 const struct arm64_cpu_capabilities
*cap
= cpu_hwcaps_ptrs
[i
];
1670 if (!(cap
->type
& non_boot_scope
))
1673 if (cap
->cpu_enable
)
1674 cap
->cpu_enable(cap
);
1680 * Run through the enabled capabilities and enable() it on all active
1683 static void __init
enable_cpu_capabilities(u16 scope_mask
)
1686 const struct arm64_cpu_capabilities
*caps
;
1689 scope_mask
&= ARM64_CPUCAP_SCOPE_MASK
;
1690 boot_scope
= !!(scope_mask
& SCOPE_BOOT_CPU
);
1692 for (i
= 0; i
< ARM64_NCAPS
; i
++) {
1695 caps
= cpu_hwcaps_ptrs
[i
];
1696 if (!caps
|| !(caps
->type
& scope_mask
))
1698 num
= caps
->capability
;
1699 if (!cpus_have_cap(num
))
1702 /* Ensure cpus_have_const_cap(num) works */
1703 static_branch_enable(&cpu_hwcap_keys
[num
]);
1705 if (boot_scope
&& caps
->cpu_enable
)
1707 * Capabilities with SCOPE_BOOT_CPU scope are finalised
1708 * before any secondary CPU boots. Thus, each secondary
1709 * will enable the capability as appropriate via
1710 * check_local_cpu_capabilities(). The only exception is
1711 * the boot CPU, for which the capability must be
1712 * enabled here. This approach avoids costly
1713 * stop_machine() calls for this case.
1715 caps
->cpu_enable(caps
);
1719 * For all non-boot scope capabilities, use stop_machine()
1720 * as it schedules the work allowing us to modify PSTATE,
1721 * instead of on_each_cpu() which uses an IPI, giving us a
1722 * PSTATE that disappears when we return.
1725 stop_machine(cpu_enable_non_boot_scope_capabilities
,
1726 NULL
, cpu_online_mask
);
1730 * Run through the list of capabilities to check for conflicts.
1731 * If the system has already detected a capability, take necessary
1732 * action on this CPU.
1734 * Returns "false" on conflicts.
1736 static bool verify_local_cpu_caps(u16 scope_mask
)
1739 bool cpu_has_cap
, system_has_cap
;
1740 const struct arm64_cpu_capabilities
*caps
;
1742 scope_mask
&= ARM64_CPUCAP_SCOPE_MASK
;
1744 for (i
= 0; i
< ARM64_NCAPS
; i
++) {
1745 caps
= cpu_hwcaps_ptrs
[i
];
1746 if (!caps
|| !(caps
->type
& scope_mask
))
1749 cpu_has_cap
= caps
->matches(caps
, SCOPE_LOCAL_CPU
);
1750 system_has_cap
= cpus_have_cap(caps
->capability
);
1752 if (system_has_cap
) {
1754 * Check if the new CPU misses an advertised feature,
1755 * which is not safe to miss.
1757 if (!cpu_has_cap
&& !cpucap_late_cpu_optional(caps
))
1760 * We have to issue cpu_enable() irrespective of
1761 * whether the CPU has it or not, as it is enabeld
1762 * system wide. It is upto the call back to take
1763 * appropriate action on this CPU.
1765 if (caps
->cpu_enable
)
1766 caps
->cpu_enable(caps
);
1769 * Check if the CPU has this capability if it isn't
1770 * safe to have when the system doesn't.
1772 if (cpu_has_cap
&& !cpucap_late_cpu_permitted(caps
))
1777 if (i
< ARM64_NCAPS
) {
1778 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1779 smp_processor_id(), caps
->capability
,
1780 caps
->desc
, system_has_cap
, cpu_has_cap
);
1788 * Check for CPU features that are used in early boot
1789 * based on the Boot CPU value.
1791 static void check_early_cpu_features(void)
1793 verify_cpu_asid_bits();
1795 * Early features are used by the kernel already. If there
1796 * is a conflict, we cannot proceed further.
1798 if (!verify_local_cpu_caps(SCOPE_BOOT_CPU
))
1803 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities
*caps
)
1806 for (; caps
->matches
; caps
++)
1807 if (cpus_have_elf_hwcap(caps
) && !caps
->matches(caps
, SCOPE_LOCAL_CPU
)) {
1808 pr_crit("CPU%d: missing HWCAP: %s\n",
1809 smp_processor_id(), caps
->desc
);
1814 static void verify_sve_features(void)
1816 u64 safe_zcr
= read_sanitised_ftr_reg(SYS_ZCR_EL1
);
1817 u64 zcr
= read_zcr_features();
1819 unsigned int safe_len
= safe_zcr
& ZCR_ELx_LEN_MASK
;
1820 unsigned int len
= zcr
& ZCR_ELx_LEN_MASK
;
1822 if (len
< safe_len
|| sve_verify_vq_map()) {
1823 pr_crit("CPU%d: SVE: required vector length(s) missing\n",
1824 smp_processor_id());
1828 /* Add checks on other ZCR bits here if necessary */
1833 * Run through the enabled system capabilities and enable() it on this CPU.
1834 * The capabilities were decided based on the available CPUs at the boot time.
1835 * Any new CPU should match the system wide status of the capability. If the
1836 * new CPU doesn't have a capability which the system now has enabled, we
1837 * cannot do anything to fix it up and could cause unexpected failures. So
1840 static void verify_local_cpu_capabilities(void)
1843 * The capabilities with SCOPE_BOOT_CPU are checked from
1844 * check_early_cpu_features(), as they need to be verified
1845 * on all secondary CPUs.
1847 if (!verify_local_cpu_caps(SCOPE_ALL
& ~SCOPE_BOOT_CPU
))
1850 verify_local_elf_hwcaps(arm64_elf_hwcaps
);
1852 if (system_supports_32bit_el0())
1853 verify_local_elf_hwcaps(compat_elf_hwcaps
);
1855 if (system_supports_sve())
1856 verify_sve_features();
1859 void check_local_cpu_capabilities(void)
1862 * All secondary CPUs should conform to the early CPU features
1863 * in use by the kernel based on boot CPU.
1865 check_early_cpu_features();
1868 * If we haven't finalised the system capabilities, this CPU gets
1869 * a chance to update the errata work arounds and local features.
1870 * Otherwise, this CPU should verify that it has all the system
1871 * advertised capabilities.
1873 if (!sys_caps_initialised
)
1874 update_cpu_capabilities(SCOPE_LOCAL_CPU
);
1876 verify_local_cpu_capabilities();
1879 static void __init
setup_boot_cpu_capabilities(void)
1881 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
1882 update_cpu_capabilities(SCOPE_BOOT_CPU
| SCOPE_LOCAL_CPU
);
1883 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
1884 enable_cpu_capabilities(SCOPE_BOOT_CPU
);
1887 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready
);
1888 EXPORT_SYMBOL(arm64_const_caps_ready
);
1890 static void __init
mark_const_caps_ready(void)
1892 static_branch_enable(&arm64_const_caps_ready
);
1895 bool this_cpu_has_cap(unsigned int n
)
1897 if (!WARN_ON(preemptible()) && n
< ARM64_NCAPS
) {
1898 const struct arm64_cpu_capabilities
*cap
= cpu_hwcaps_ptrs
[n
];
1901 return cap
->matches(cap
, SCOPE_LOCAL_CPU
);
1907 static void __init
setup_system_capabilities(void)
1910 * We have finalised the system-wide safe feature
1911 * registers, finalise the capabilities that depend
1912 * on it. Also enable all the available capabilities,
1913 * that are not enabled already.
1915 update_cpu_capabilities(SCOPE_SYSTEM
);
1916 enable_cpu_capabilities(SCOPE_ALL
& ~SCOPE_BOOT_CPU
);
1919 void __init
setup_cpu_features(void)
1923 setup_system_capabilities();
1924 mark_const_caps_ready();
1925 setup_elf_hwcaps(arm64_elf_hwcaps
);
1927 if (system_supports_32bit_el0())
1928 setup_elf_hwcaps(compat_elf_hwcaps
);
1930 if (system_uses_ttbr0_pan())
1931 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
1934 minsigstksz_setup();
1936 /* Advertise that we have computed the system capabilities */
1937 set_sys_caps_initialised();
1940 * Check for sane CTR_EL0.CWG value.
1942 cwg
= cache_type_cwg();
1944 pr_warn("No Cache Writeback Granule information, assuming %d\n",
1948 static bool __maybe_unused
1949 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities
*entry
, int __unused
)
1951 return (cpus_have_const_cap(ARM64_HAS_PAN
) && !cpus_have_const_cap(ARM64_HAS_UAO
));
1954 static void __maybe_unused
cpu_enable_cnp(struct arm64_cpu_capabilities
const *cap
)
1956 cpu_replace_ttbr1(lm_alias(swapper_pg_dir
));
1960 * We emulate only the following system register space.
1961 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1962 * See Table C5-6 System instruction encodings for System register accesses,
1963 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1965 static inline bool __attribute_const__
is_emulated(u32 id
)
1967 return (sys_reg_Op0(id
) == 0x3 &&
1968 sys_reg_CRn(id
) == 0x0 &&
1969 sys_reg_Op1(id
) == 0x0 &&
1970 (sys_reg_CRm(id
) == 0 ||
1971 ((sys_reg_CRm(id
) >= 4) && (sys_reg_CRm(id
) <= 7))));
1975 * With CRm == 0, reg should be one of :
1976 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1978 static inline int emulate_id_reg(u32 id
, u64
*valp
)
1982 *valp
= read_cpuid_id();
1985 *valp
= SYS_MPIDR_SAFE_VAL
;
1987 case SYS_REVIDR_EL1
:
1988 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1998 static int emulate_sys_reg(u32 id
, u64
*valp
)
2000 struct arm64_ftr_reg
*regp
;
2002 if (!is_emulated(id
))
2005 if (sys_reg_CRm(id
) == 0)
2006 return emulate_id_reg(id
, valp
);
2008 regp
= get_arm64_ftr_reg(id
);
2010 *valp
= arm64_ftr_reg_user_value(regp
);
2013 * The untracked registers are either IMPLEMENTATION DEFINED
2014 * (e.g, ID_AFR0_EL1) or reserved RAZ.
2020 int do_emulate_mrs(struct pt_regs
*regs
, u32 sys_reg
, u32 rt
)
2025 rc
= emulate_sys_reg(sys_reg
, &val
);
2027 pt_regs_write_reg(regs
, rt
, val
);
2028 arm64_skip_faulting_instruction(regs
, AARCH64_INSN_SIZE
);
2033 static int emulate_mrs(struct pt_regs
*regs
, u32 insn
)
2038 * sys_reg values are defined as used in mrs/msr instruction.
2039 * shift the imm value to get the encoding.
2041 sys_reg
= (u32
)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16
, insn
) << 5;
2042 rt
= aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT
, insn
);
2043 return do_emulate_mrs(regs
, sys_reg
, rt
);
2046 static struct undef_hook mrs_hook
= {
2047 .instr_mask
= 0xfff00000,
2048 .instr_val
= 0xd5300000,
2049 .pstate_mask
= PSR_AA32_MODE_MASK
,
2050 .pstate_val
= PSR_MODE_EL0t
,
2054 static int __init
enable_mrs_emulation(void)
2056 register_undef_hook(&mrs_hook
);
2060 core_initcall(enable_mrs_emulation
);