arch/arm64/kernel/cpufeature.c

   1 /*
   2  * Contains CPU feature definitions
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt) "CPU features: " fmt
  20
  21 #include <linux/bsearch.h>
  22 #include <linux/sort.h>
  23 #include <linux/types.h>
  24 #include <asm/cpu.h>
  25 #include <asm/cpufeature.h>
  26 #include <asm/processor.h>
  27 #include <asm/sysreg.h>
  28
  29 static bool mixed_endian_el0 = true;
  30 unsigned long elf_hwcap __read_mostly;
  31 EXPORT_SYMBOL_GPL(elf_hwcap);
  32
  33 #ifdef CONFIG_COMPAT
  34 #define COMPAT_ELF_HWCAP_DEFAULT        \
  35                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  36                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  37                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  38                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  39                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  40                                  COMPAT_HWCAP_LPAE)
  41 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  42 unsigned int compat_elf_hwcap2 __read_mostly;
  43 #endif
  44
  45 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  46
  47
  48 bool cpu_supports_mixed_endian_el0(void)
  49 {
  50         return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
  51 }
  52
  53 bool system_supports_mixed_endian_el0(void)
  54 {
  55         return mixed_endian_el0;
  56 }
  57
  58 static void update_mixed_endian_el0_support(struct cpuinfo_arm64 *info)
  59 {
  60         mixed_endian_el0 &= id_aa64mmfr0_mixed_endian_el0(info->reg_id_aa64mmfr0);
  61 }
  62
  63 #define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  64         {                                               \
  65                 .strict = STRICT,                       \
  66                 .type = TYPE,                           \
  67                 .shift = SHIFT,                         \
  68                 .width = WIDTH,                         \
  69                 .safe_val = SAFE_VAL,                   \
  70         }
  71
  72 #define ARM64_FTR_END                                   \
  73         {                                               \
  74                 .width = 0,                             \
  75         }
  76
  77 static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
  78         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  79         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
  80         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
  81         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
  82         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
  83         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
  84         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
  85         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
  86         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
  87         ARM64_FTR_END,
  88 };
  89
  90 static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
  91         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
  92         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
  93         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
  94         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
  95         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
  96         /* Linux doesn't care about the EL3 */
  97         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
  98         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
  99         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 100         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 101         ARM64_FTR_END,
 102 };
 103
 104 static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 105         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 106         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 107         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 108         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 109         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 110         /* Linux shouldn't care about secure memory */
 111         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 112         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 113         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 114         /*
 115          * Differing PARange is fine as long as all peripherals and memory are mapped
 116          * within the minimum PARange of all CPUs
 117          */
 118         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 119         ARM64_FTR_END,
 120 };
 121
 122 static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 123         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 124         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 125         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 126         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 127         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 128         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 129         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 130         ARM64_FTR_END,
 131 };
 132
 133 static struct arm64_ftr_bits ftr_ctr[] = {
 134         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1),        /* RAO */
 135         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
 136         ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0),  /* CWG */
 137         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),   /* ERG */
 138         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1),   /* DminLine */
 139         /*
 140          * Linux can handle differing I-cache policies. Userspace JITs will
 141          * make use of *minLine
 142          */
 143         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0),     /* L1Ip */
 144         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0),        /* RAZ */
 145         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),    /* IminLine */
 146         ARM64_FTR_END,
 147 };
 148
 149 static struct arm64_ftr_bits ftr_id_mmfr0[] = {
 150         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),        /* InnerShr */
 151         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),        /* FCSE */
 152         ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),        /* AuxReg */
 153         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0),        /* TCM */
 154         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),        /* ShareLvl */
 155         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* OuterShr */
 156         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
 157         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
 158         ARM64_FTR_END,
 159 };
 160
 161 static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 162         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
 163         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 164         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 165         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 166         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 167         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 168         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 169         ARM64_FTR_END,
 170 };
 171
 172 static struct arm64_ftr_bits ftr_mvfr2[] = {
 173         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0),        /* RAZ */
 174         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* FPMisc */
 175         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* SIMDMisc */
 176         ARM64_FTR_END,
 177 };
 178
 179 static struct arm64_ftr_bits ftr_dczid[] = {
 180         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0),        /* RAZ */
 181         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1),         /* DZP */
 182         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),    /* BS */
 183         ARM64_FTR_END,
 184 };
 185
 186
 187 static struct arm64_ftr_bits ftr_id_isar5[] = {
 188         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
 189         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0),        /* RAZ */
 190         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
 191         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
 192         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
 193         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
 194         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
 195         ARM64_FTR_END,
 196 };
 197
 198 static struct arm64_ftr_bits ftr_id_mmfr4[] = {
 199         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0),        /* RAZ */
 200         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* ac2 */
 201         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* RAZ */
 202         ARM64_FTR_END,
 203 };
 204
 205 static struct arm64_ftr_bits ftr_id_pfr0[] = {
 206         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0),       /* RAZ */
 207         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0),        /* State3 */
 208         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0),         /* State2 */
 209         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0),         /* State1 */
 210         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0),         /* State0 */
 211         ARM64_FTR_END,
 212 };
 213
 214 /*
 215  * Common ftr bits for a 32bit register with all hidden, strict
 216  * attributes, with 4bit feature fields and a default safe value of
 217  * 0. Covers the following 32bit registers:
 218  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 219  */
 220 static struct arm64_ftr_bits ftr_generic_32bits[] = {
 221         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 222         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 223         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 224         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 225         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 226         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 227         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 228         ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 229         ARM64_FTR_END,
 230 };
 231
 232 static struct arm64_ftr_bits ftr_generic[] = {
 233         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
 234         ARM64_FTR_END,
 235 };
 236
 237 static struct arm64_ftr_bits ftr_generic32[] = {
 238         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
 239         ARM64_FTR_END,
 240 };
 241
 242 static struct arm64_ftr_bits ftr_aa64raz[] = {
 243         ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
 244         ARM64_FTR_END,
 245 };
 246
 247 #define ARM64_FTR_REG(id, table)                \
 248         {                                       \
 249                 .sys_id = id,                   \
 250                 .name = #id,                    \
 251                 .ftr_bits = &((table)[0]),      \
 252         }
 253
 254 static struct arm64_ftr_reg arm64_ftr_regs[] = {
 255
 256         /* Op1 = 0, CRn = 0, CRm = 1 */
 257         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 258         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 259         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_generic_32bits),
 260         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 261         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 262         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 263         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 264
 265         /* Op1 = 0, CRn = 0, CRm = 2 */
 266         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 267         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 268         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 269         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 270         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 271         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 272         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 273
 274         /* Op1 = 0, CRn = 0, CRm = 3 */
 275         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 276         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 277         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 278
 279         /* Op1 = 0, CRn = 0, CRm = 4 */
 280         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 281         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
 282
 283         /* Op1 = 0, CRn = 0, CRm = 5 */
 284         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 285         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
 286
 287         /* Op1 = 0, CRn = 0, CRm = 6 */
 288         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 289         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
 290
 291         /* Op1 = 0, CRn = 0, CRm = 7 */
 292         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 293         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 294
 295         /* Op1 = 3, CRn = 0, CRm = 0 */
 296         ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
 297         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 298
 299         /* Op1 = 3, CRn = 14, CRm = 0 */
 300         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
 301 };
 302
 303 static int search_cmp_ftr_reg(const void *id, const void *regp)
 304 {
 305         return (int)(unsigned long)id - (int)((const struct arm64_ftr_reg *)regp)->sys_id;
 306 }
 307
 308 /*
 309  * get_arm64_ftr_reg - Lookup a feature register entry using its
 310  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 311  * ascending order of sys_id , we use binary search to find a matching
 312  * entry.
 313  *
 314  * returns - Upon success,  matching ftr_reg entry for id.
 315  *         - NULL on failure. It is upto the caller to decide
 316  *           the impact of a failure.
 317  */
 318 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 319 {
 320         return bsearch((const void *)(unsigned long)sys_id,
 321                         arm64_ftr_regs,
 322                         ARRAY_SIZE(arm64_ftr_regs),
 323                         sizeof(arm64_ftr_regs[0]),
 324                         search_cmp_ftr_reg);
 325 }
 326
 327 static u64 arm64_ftr_set_value(struct arm64_ftr_bits *ftrp, s64 reg, s64 ftr_val)
 328 {
 329         u64 mask = arm64_ftr_mask(ftrp);
 330
 331         reg &= ~mask;
 332         reg |= (ftr_val << ftrp->shift) & mask;
 333         return reg;
 334 }
 335
 336 static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur)
 337 {
 338         s64 ret = 0;
 339
 340         switch (ftrp->type) {
 341         case FTR_EXACT:
 342                 ret = ftrp->safe_val;
 343                 break;
 344         case FTR_LOWER_SAFE:
 345                 ret = new < cur ? new : cur;
 346                 break;
 347         case FTR_HIGHER_SAFE:
 348                 ret = new > cur ? new : cur;
 349                 break;
 350         default:
 351                 BUG();
 352         }
 353
 354         return ret;
 355 }
 356
 357 static int __init sort_cmp_ftr_regs(const void *a, const void *b)
 358 {
 359         return ((const struct arm64_ftr_reg *)a)->sys_id -
 360                  ((const struct arm64_ftr_reg *)b)->sys_id;
 361 }
 362
 363 static void __init swap_ftr_regs(void *a, void *b, int size)
 364 {
 365         struct arm64_ftr_reg tmp = *(struct arm64_ftr_reg *)a;
 366         *(struct arm64_ftr_reg *)a = *(struct arm64_ftr_reg *)b;
 367         *(struct arm64_ftr_reg *)b = tmp;
 368 }
 369
 370 static void __init sort_ftr_regs(void)
 371 {
 372         /* Keep the array sorted so that we can do the binary search */
 373         sort(arm64_ftr_regs,
 374                 ARRAY_SIZE(arm64_ftr_regs),
 375                 sizeof(arm64_ftr_regs[0]),
 376                 sort_cmp_ftr_regs,
 377                 swap_ftr_regs);
 378 }
 379
 380 /*
 381  * Initialise the CPU feature register from Boot CPU values.
 382  * Also initiliases the strict_mask for the register.
 383  */
 384 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 385 {
 386         u64 val = 0;
 387         u64 strict_mask = ~0x0ULL;
 388         struct arm64_ftr_bits *ftrp;
 389         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 390
 391         BUG_ON(!reg);
 392
 393         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 394                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 395
 396                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 397                 if (!ftrp->strict)
 398                         strict_mask &= ~arm64_ftr_mask(ftrp);
 399         }
 400         reg->sys_val = val;
 401         reg->strict_mask = strict_mask;
 402 }
 403
 404 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 405 {
 406         /* Before we start using the tables, make sure it is sorted */
 407         sort_ftr_regs();
 408
 409         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 410         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 411         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 412         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 413         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 414         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 415         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 416         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 417         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 418         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 419         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 420         init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 421         init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 422         init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 423         init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 424         init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 425         init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 426         init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 427         init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 428         init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 429         init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 430         init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 431         init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 432         init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 433         init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 434         init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 435         init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 436
 437         /* This will be removed later, once we start using the infrastructure */
 438         update_mixed_endian_el0_support(info);
 439 }
 440
 441 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 442 {
 443         struct arm64_ftr_bits *ftrp;
 444
 445         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 446                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 447                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 448
 449                 if (ftr_cur == ftr_new)
 450                         continue;
 451                 /* Find a safe value */
 452                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 453                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 454         }
 455
 456 }
 457
 458 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 459 {
 460         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 461
 462         BUG_ON(!regp);
 463         update_cpu_ftr_reg(regp, val);
 464         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 465                 return 0;
 466         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 467                         regp->name, boot, cpu, val);
 468         return 1;
 469 }
 470
 471 /*
 472  * Update system wide CPU feature registers with the values from a
 473  * non-boot CPU. Also performs SANITY checks to make sure that there
 474  * aren't any insane variations from that of the boot CPU.
 475  */
 476 void update_cpu_features(int cpu,
 477                          struct cpuinfo_arm64 *info,
 478                          struct cpuinfo_arm64 *boot)
 479 {
 480         int taint = 0;
 481
 482         /*
 483          * The kernel can handle differing I-cache policies, but otherwise
 484          * caches should look identical. Userspace JITs will make use of
 485          * *minLine.
 486          */
 487         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 488                                       info->reg_ctr, boot->reg_ctr);
 489
 490         /*
 491          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 492          * could result in too much or too little memory being zeroed if a
 493          * process is preempted and migrated between CPUs.
 494          */
 495         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 496                                       info->reg_dczid, boot->reg_dczid);
 497
 498         /* If different, timekeeping will be broken (especially with KVM) */
 499         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 500                                       info->reg_cntfrq, boot->reg_cntfrq);
 501
 502         /*
 503          * The kernel uses self-hosted debug features and expects CPUs to
 504          * support identical debug features. We presently need CTX_CMPs, WRPs,
 505          * and BRPs to be identical.
 506          * ID_AA64DFR1 is currently RES0.
 507          */
 508         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 509                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 510         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 511                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 512         /*
 513          * Even in big.LITTLE, processors should be identical instruction-set
 514          * wise.
 515          */
 516         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 517                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 518         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 519                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 520
 521         /*
 522          * Differing PARange support is fine as long as all peripherals and
 523          * memory are mapped within the minimum PARange of all CPUs.
 524          * Linux should not care about secure memory.
 525          */
 526         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 527                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 528         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 529                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 530
 531         /*
 532          * EL3 is not our concern.
 533          * ID_AA64PFR1 is currently RES0.
 534          */
 535         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 536                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 537         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 538                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 539
 540         /*
 541          * If we have AArch32, we care about 32-bit features for compat. These
 542          * registers should be RES0 otherwise.
 543          */
 544         taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 545                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 546         taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 547                                         info->reg_id_isar0, boot->reg_id_isar0);
 548         taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 549                                         info->reg_id_isar1, boot->reg_id_isar1);
 550         taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 551                                         info->reg_id_isar2, boot->reg_id_isar2);
 552         taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 553                                         info->reg_id_isar3, boot->reg_id_isar3);
 554         taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 555                                         info->reg_id_isar4, boot->reg_id_isar4);
 556         taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 557                                         info->reg_id_isar5, boot->reg_id_isar5);
 558
 559         /*
 560          * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 561          * ACTLR formats could differ across CPUs and therefore would have to
 562          * be trapped for virtualization anyway.
 563          */
 564         taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 565                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 566         taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 567                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 568         taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 569                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 570         taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 571                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 572         taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 573                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 574         taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 575                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 576         taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 577                                         info->reg_mvfr0, boot->reg_mvfr0);
 578         taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 579                                         info->reg_mvfr1, boot->reg_mvfr1);
 580         taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 581                                         info->reg_mvfr2, boot->reg_mvfr2);
 582
 583         /*
 584          * Mismatched CPU features are a recipe for disaster. Don't even
 585          * pretend to support them.
 586          */
 587         WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
 588                         "Unsupported CPU feature variation.\n");
 589
 590         update_mixed_endian_el0_support(info);
 591 }
 592
 593 u64 read_system_reg(u32 id)
 594 {
 595         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 596
 597         /* We shouldn't get a request for an unsupported register */
 598         BUG_ON(!regp);
 599         return regp->sys_val;
 600 }
 601
 602 static bool
 603 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 604 {
 605         int val = cpuid_feature_extract_field(reg, entry->field_pos);
 606
 607         return val >= entry->min_field_value;
 608 }
 609
 610 #define __ID_FEAT_CHK(reg)                                              \
 611 static bool __maybe_unused                                              \
 612 has_##reg##_feature(const struct arm64_cpu_capabilities *entry)         \
 613 {                                                                       \
 614         u64 val;                                                        \
 615                                                                         \
 616         val = read_cpuid(reg##_el1);                                    \
 617         return feature_matches(val, entry);                             \
 618 }
 619
 620 __ID_FEAT_CHK(id_aa64pfr0);
 621 __ID_FEAT_CHK(id_aa64mmfr1);
 622 __ID_FEAT_CHK(id_aa64isar0);
 623
 624 static const struct arm64_cpu_capabilities arm64_features[] = {
 625         {
 626                 .desc = "GIC system register CPU interface",
 627                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
 628                 .matches = has_id_aa64pfr0_feature,
 629                 .field_pos = 24,
 630                 .min_field_value = 1,
 631         },
 632 #ifdef CONFIG_ARM64_PAN
 633         {
 634                 .desc = "Privileged Access Never",
 635                 .capability = ARM64_HAS_PAN,
 636                 .matches = has_id_aa64mmfr1_feature,
 637                 .field_pos = 20,
 638                 .min_field_value = 1,
 639                 .enable = cpu_enable_pan,
 640         },
 641 #endif /* CONFIG_ARM64_PAN */
 642 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
 643         {
 644                 .desc = "LSE atomic instructions",
 645                 .capability = ARM64_HAS_LSE_ATOMICS,
 646                 .matches = has_id_aa64isar0_feature,
 647                 .field_pos = 20,
 648                 .min_field_value = 2,
 649         },
 650 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
 651         {},
 652 };
 653
 654 void check_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
 655                             const char *info)
 656 {
 657         int i;
 658
 659         for (i = 0; caps[i].desc; i++) {
 660                 if (!caps[i].matches(&caps[i]))
 661                         continue;
 662
 663                 if (!cpus_have_cap(caps[i].capability))
 664                         pr_info("%s %s\n", info, caps[i].desc);
 665                 cpus_set_cap(caps[i].capability);
 666         }
 667
 668         /* second pass allows enable() to consider interacting capabilities */
 669         for (i = 0; caps[i].desc; i++) {
 670                 if (cpus_have_cap(caps[i].capability) && caps[i].enable)
 671                         caps[i].enable();
 672         }
 673 }
 674
 675 void check_local_cpu_features(void)
 676 {
 677         check_cpu_capabilities(arm64_features, "detected feature:");
 678 }
 679
 680 void __init setup_cpu_features(void)
 681 {
 682         u64 features;
 683         s64 block;
 684         u32 cwg;
 685         int cls;
 686
 687         /*
 688          * Check for sane CTR_EL0.CWG value.
 689          */
 690         cwg = cache_type_cwg();
 691         cls = cache_line_size();
 692         if (!cwg)
 693                 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
 694                         cls);
 695         if (L1_CACHE_BYTES < cls)
 696                 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
 697                         L1_CACHE_BYTES, cls);
 698
 699         /*
 700          * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
 701          * The blocks we test below represent incremental functionality
 702          * for non-negative values. Negative values are reserved.
 703          */
 704         features = read_cpuid(ID_AA64ISAR0_EL1);
 705         block = cpuid_feature_extract_field(features, 4);
 706         if (block > 0) {
 707                 switch (block) {
 708                 default:
 709                 case 2:
 710                         elf_hwcap |= HWCAP_PMULL;
 711                 case 1:
 712                         elf_hwcap |= HWCAP_AES;
 713                 case 0:
 714                         break;
 715                 }
 716         }
 717
 718         if (cpuid_feature_extract_field(features, 8) > 0)
 719                 elf_hwcap |= HWCAP_SHA1;
 720
 721         if (cpuid_feature_extract_field(features, 12) > 0)
 722                 elf_hwcap |= HWCAP_SHA2;
 723
 724         if (cpuid_feature_extract_field(features, 16) > 0)
 725                 elf_hwcap |= HWCAP_CRC32;
 726
 727         block = cpuid_feature_extract_field(features, 20);
 728         if (block > 0) {
 729                 switch (block) {
 730                 default:
 731                 case 2:
 732                         elf_hwcap |= HWCAP_ATOMICS;
 733                 case 1:
 734                         /* RESERVED */
 735                 case 0:
 736                         break;
 737                 }
 738         }
 739
 740 #ifdef CONFIG_COMPAT
 741         /*
 742          * ID_ISAR5_EL1 carries similar information as above, but pertaining to
 743          * the AArch32 32-bit execution state.
 744          */
 745         features = read_cpuid(ID_ISAR5_EL1);
 746         block = cpuid_feature_extract_field(features, 4);
 747         if (block > 0) {
 748                 switch (block) {
 749                 default:
 750                 case 2:
 751                         compat_elf_hwcap2 |= COMPAT_HWCAP2_PMULL;
 752                 case 1:
 753                         compat_elf_hwcap2 |= COMPAT_HWCAP2_AES;
 754                 case 0:
 755                         break;
 756                 }
 757         }
 758
 759         if (cpuid_feature_extract_field(features, 8) > 0)
 760                 compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA1;
 761
 762         if (cpuid_feature_extract_field(features, 12) > 0)
 763                 compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA2;
 764
 765         if (cpuid_feature_extract_field(features, 16) > 0)
 766                 compat_elf_hwcap2 |= COMPAT_HWCAP2_CRC32;
 767 #endif
 768 }