2 * Contains CPU feature definitions
4 * Copyright (C) 2015 ARM Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) "CPU features: " fmt
21 #include <linux/bsearch.h>
22 #include <linux/cpumask.h>
23 #include <linux/sort.h>
24 #include <linux/stop_machine.h>
25 #include <linux/types.h>
28 #include <asm/cpufeature.h>
29 #include <asm/cpu_ops.h>
30 #include <asm/fpsimd.h>
31 #include <asm/mmu_context.h>
32 #include <asm/processor.h>
33 #include <asm/sysreg.h>
34 #include <asm/traps.h>
37 unsigned long elf_hwcap __read_mostly
;
38 EXPORT_SYMBOL_GPL(elf_hwcap
);
41 #define COMPAT_ELF_HWCAP_DEFAULT \
42 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
43 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
44 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
45 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
46 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
48 unsigned int compat_elf_hwcap __read_mostly
= COMPAT_ELF_HWCAP_DEFAULT
;
49 unsigned int compat_elf_hwcap2 __read_mostly
;
52 DECLARE_BITMAP(cpu_hwcaps
, ARM64_NCAPS
);
53 EXPORT_SYMBOL(cpu_hwcaps
);
56 * Flag to indicate if we have computed the system wide
57 * capabilities based on the boot time active CPUs. This
58 * will be used to determine if a new booting CPU should
59 * go through the verification process to make sure that it
60 * supports the system capabilities, without using a hotplug
63 static bool sys_caps_initialised
;
65 static inline void set_sys_caps_initialised(void)
67 sys_caps_initialised
= true;
70 static int dump_cpu_hwcaps(struct notifier_block
*self
, unsigned long v
, void *p
)
72 /* file-wide pr_fmt adds "CPU features: " prefix */
73 pr_emerg("0x%*pb\n", ARM64_NCAPS
, &cpu_hwcaps
);
77 static struct notifier_block cpu_hwcaps_notifier
= {
78 .notifier_call
= dump_cpu_hwcaps
81 static int __init
register_cpu_hwcaps_dumper(void)
83 atomic_notifier_chain_register(&panic_notifier_list
,
84 &cpu_hwcaps_notifier
);
87 __initcall(register_cpu_hwcaps_dumper
);
89 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys
, ARM64_NCAPS
);
90 EXPORT_SYMBOL(cpu_hwcap_keys
);
92 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
100 .safe_val = SAFE_VAL, \
103 /* Define a feature with unsigned values */
104 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
105 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
107 /* Define a feature with a signed value */
108 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
109 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
111 #define ARM64_FTR_END \
116 /* meta feature for alternatives */
117 static bool __maybe_unused
118 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities
*entry
, int __unused
);
122 * NOTE: Any changes to the visibility of features should be kept in
123 * sync with the documentation of the CPU feature register ABI.
125 static const struct arm64_ftr_bits ftr_id_aa64isar0
[] = {
126 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_DP_SHIFT
, 4, 0),
127 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_SM4_SHIFT
, 4, 0),
128 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_SM3_SHIFT
, 4, 0),
129 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_SHA3_SHIFT
, 4, 0),
130 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_RDM_SHIFT
, 4, 0),
131 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_ATOMICS_SHIFT
, 4, 0),
132 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_CRC32_SHIFT
, 4, 0),
133 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_SHA2_SHIFT
, 4, 0),
134 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_SHA1_SHIFT
, 4, 0),
135 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_AES_SHIFT
, 4, 0),
139 static const struct arm64_ftr_bits ftr_id_aa64isar1
[] = {
140 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR1_LRCPC_SHIFT
, 4, 0),
141 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR1_FCMA_SHIFT
, 4, 0),
142 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR1_JSCVT_SHIFT
, 4, 0),
143 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR1_DPB_SHIFT
, 4, 0),
147 static const struct arm64_ftr_bits ftr_id_aa64pfr0
[] = {
148 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_SVE_SHIFT
, 4, 0),
149 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_GIC_SHIFT
, 4, 0),
150 S_ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_ASIMD_SHIFT
, 4, ID_AA64PFR0_ASIMD_NI
),
151 S_ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_FP_SHIFT
, 4, ID_AA64PFR0_FP_NI
),
152 /* Linux doesn't care about the EL3 */
153 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_EL3_SHIFT
, 4, 0),
154 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_EL2_SHIFT
, 4, 0),
155 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_EL1_SHIFT
, 4, ID_AA64PFR0_EL1_64BIT_ONLY
),
156 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_EL0_SHIFT
, 4, ID_AA64PFR0_EL0_64BIT_ONLY
),
160 static const struct arm64_ftr_bits ftr_id_aa64mmfr0
[] = {
161 S_ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_TGRAN4_SHIFT
, 4, ID_AA64MMFR0_TGRAN4_NI
),
162 S_ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_TGRAN64_SHIFT
, 4, ID_AA64MMFR0_TGRAN64_NI
),
163 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_TGRAN16_SHIFT
, 4, ID_AA64MMFR0_TGRAN16_NI
),
164 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_BIGENDEL0_SHIFT
, 4, 0),
165 /* Linux shouldn't care about secure memory */
166 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_SNSMEM_SHIFT
, 4, 0),
167 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_BIGENDEL_SHIFT
, 4, 0),
168 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_ASID_SHIFT
, 4, 0),
170 * Differing PARange is fine as long as all peripherals and memory are mapped
171 * within the minimum PARange of all CPUs
173 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_PARANGE_SHIFT
, 4, 0),
177 static const struct arm64_ftr_bits ftr_id_aa64mmfr1
[] = {
178 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR1_PAN_SHIFT
, 4, 0),
179 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR1_LOR_SHIFT
, 4, 0),
180 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR1_HPD_SHIFT
, 4, 0),
181 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR1_VHE_SHIFT
, 4, 0),
182 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR1_VMIDBITS_SHIFT
, 4, 0),
183 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR1_HADBS_SHIFT
, 4, 0),
187 static const struct arm64_ftr_bits ftr_id_aa64mmfr2
[] = {
188 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR2_LVA_SHIFT
, 4, 0),
189 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR2_IESB_SHIFT
, 4, 0),
190 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR2_LSM_SHIFT
, 4, 0),
191 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR2_UAO_SHIFT
, 4, 0),
192 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR2_CNP_SHIFT
, 4, 0),
196 static const struct arm64_ftr_bits ftr_ctr
[] = {
197 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_EXACT
, 31, 1, 1), /* RAO */
198 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_HIGHER_SAFE
, 24, 4, 0), /* CWG */
199 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, 20, 4, 0), /* ERG */
200 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, 16, 4, 1), /* DminLine */
202 * Linux can handle differing I-cache policies. Userspace JITs will
203 * make use of *minLine.
204 * If we have differing I-cache policies, report it as the weakest - VIPT.
206 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_NONSTRICT
, FTR_EXACT
, 14, 2, ICACHE_POLICY_VIPT
), /* L1Ip */
207 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0), /* IminLine */
211 struct arm64_ftr_reg arm64_ftr_reg_ctrel0
= {
212 .name
= "SYS_CTR_EL0",
216 static const struct arm64_ftr_bits ftr_id_mmfr0
[] = {
217 S_ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 28, 4, 0xf), /* InnerShr */
218 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 24, 4, 0), /* FCSE */
219 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, 20, 4, 0), /* AuxReg */
220 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 16, 4, 0), /* TCM */
221 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 12, 4, 0), /* ShareLvl */
222 S_ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 8, 4, 0xf), /* OuterShr */
223 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0), /* PMSA */
224 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0), /* VMSA */
228 static const struct arm64_ftr_bits ftr_id_aa64dfr0
[] = {
229 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_EXACT
, 36, 28, 0),
230 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64DFR0_PMSVER_SHIFT
, 4, 0),
231 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64DFR0_CTX_CMPS_SHIFT
, 4, 0),
232 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64DFR0_WRPS_SHIFT
, 4, 0),
233 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64DFR0_BRPS_SHIFT
, 4, 0),
235 * We can instantiate multiple PMU instances with different levels
238 S_ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_EXACT
, ID_AA64DFR0_PMUVER_SHIFT
, 4, 0),
239 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_EXACT
, ID_AA64DFR0_TRACEVER_SHIFT
, 4, 0),
240 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_EXACT
, ID_AA64DFR0_DEBUGVER_SHIFT
, 4, 0x6),
244 static const struct arm64_ftr_bits ftr_mvfr2
[] = {
245 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0), /* FPMisc */
246 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0), /* SIMDMisc */
250 static const struct arm64_ftr_bits ftr_dczid
[] = {
251 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_EXACT
, 4, 1, 1), /* DZP */
252 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0), /* BS */
257 static const struct arm64_ftr_bits ftr_id_isar5
[] = {
258 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_ISAR5_RDM_SHIFT
, 4, 0),
259 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_ISAR5_CRC32_SHIFT
, 4, 0),
260 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_ISAR5_SHA2_SHIFT
, 4, 0),
261 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_ISAR5_SHA1_SHIFT
, 4, 0),
262 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_ISAR5_AES_SHIFT
, 4, 0),
263 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_ISAR5_SEVL_SHIFT
, 4, 0),
267 static const struct arm64_ftr_bits ftr_id_mmfr4
[] = {
268 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0), /* ac2 */
272 static const struct arm64_ftr_bits ftr_id_pfr0
[] = {
273 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 12, 4, 0), /* State3 */
274 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 8, 4, 0), /* State2 */
275 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0), /* State1 */
276 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0), /* State0 */
280 static const struct arm64_ftr_bits ftr_id_dfr0
[] = {
281 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 28, 4, 0),
282 S_ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 24, 4, 0xf), /* PerfMon */
283 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 20, 4, 0),
284 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 16, 4, 0),
285 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 12, 4, 0),
286 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 8, 4, 0),
287 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0),
288 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0),
292 static const struct arm64_ftr_bits ftr_zcr
[] = {
293 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
,
294 ZCR_ELx_LEN_SHIFT
, ZCR_ELx_LEN_SIZE
, 0), /* LEN */
299 * Common ftr bits for a 32bit register with all hidden, strict
300 * attributes, with 4bit feature fields and a default safe value of
301 * 0. Covers the following 32bit registers:
302 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
304 static const struct arm64_ftr_bits ftr_generic_32bits
[] = {
305 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 28, 4, 0),
306 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 24, 4, 0),
307 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 20, 4, 0),
308 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 16, 4, 0),
309 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 12, 4, 0),
310 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 8, 4, 0),
311 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0),
312 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0),
316 /* Table for a single 32bit feature value */
317 static const struct arm64_ftr_bits ftr_single32
[] = {
318 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_EXACT
, 0, 32, 0),
322 static const struct arm64_ftr_bits ftr_raz
[] = {
326 #define ARM64_FTR_REG(id, table) { \
328 .reg = &(struct arm64_ftr_reg){ \
330 .ftr_bits = &((table)[0]), \
333 static const struct __ftr_reg_entry
{
335 struct arm64_ftr_reg
*reg
;
336 } arm64_ftr_regs
[] = {
338 /* Op1 = 0, CRn = 0, CRm = 1 */
339 ARM64_FTR_REG(SYS_ID_PFR0_EL1
, ftr_id_pfr0
),
340 ARM64_FTR_REG(SYS_ID_PFR1_EL1
, ftr_generic_32bits
),
341 ARM64_FTR_REG(SYS_ID_DFR0_EL1
, ftr_id_dfr0
),
342 ARM64_FTR_REG(SYS_ID_MMFR0_EL1
, ftr_id_mmfr0
),
343 ARM64_FTR_REG(SYS_ID_MMFR1_EL1
, ftr_generic_32bits
),
344 ARM64_FTR_REG(SYS_ID_MMFR2_EL1
, ftr_generic_32bits
),
345 ARM64_FTR_REG(SYS_ID_MMFR3_EL1
, ftr_generic_32bits
),
347 /* Op1 = 0, CRn = 0, CRm = 2 */
348 ARM64_FTR_REG(SYS_ID_ISAR0_EL1
, ftr_generic_32bits
),
349 ARM64_FTR_REG(SYS_ID_ISAR1_EL1
, ftr_generic_32bits
),
350 ARM64_FTR_REG(SYS_ID_ISAR2_EL1
, ftr_generic_32bits
),
351 ARM64_FTR_REG(SYS_ID_ISAR3_EL1
, ftr_generic_32bits
),
352 ARM64_FTR_REG(SYS_ID_ISAR4_EL1
, ftr_generic_32bits
),
353 ARM64_FTR_REG(SYS_ID_ISAR5_EL1
, ftr_id_isar5
),
354 ARM64_FTR_REG(SYS_ID_MMFR4_EL1
, ftr_id_mmfr4
),
356 /* Op1 = 0, CRn = 0, CRm = 3 */
357 ARM64_FTR_REG(SYS_MVFR0_EL1
, ftr_generic_32bits
),
358 ARM64_FTR_REG(SYS_MVFR1_EL1
, ftr_generic_32bits
),
359 ARM64_FTR_REG(SYS_MVFR2_EL1
, ftr_mvfr2
),
361 /* Op1 = 0, CRn = 0, CRm = 4 */
362 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1
, ftr_id_aa64pfr0
),
363 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1
, ftr_raz
),
364 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1
, ftr_raz
),
366 /* Op1 = 0, CRn = 0, CRm = 5 */
367 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1
, ftr_id_aa64dfr0
),
368 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1
, ftr_raz
),
370 /* Op1 = 0, CRn = 0, CRm = 6 */
371 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1
, ftr_id_aa64isar0
),
372 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1
, ftr_id_aa64isar1
),
374 /* Op1 = 0, CRn = 0, CRm = 7 */
375 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1
, ftr_id_aa64mmfr0
),
376 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1
, ftr_id_aa64mmfr1
),
377 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1
, ftr_id_aa64mmfr2
),
379 /* Op1 = 0, CRn = 1, CRm = 2 */
380 ARM64_FTR_REG(SYS_ZCR_EL1
, ftr_zcr
),
382 /* Op1 = 3, CRn = 0, CRm = 0 */
383 { SYS_CTR_EL0
, &arm64_ftr_reg_ctrel0
},
384 ARM64_FTR_REG(SYS_DCZID_EL0
, ftr_dczid
),
386 /* Op1 = 3, CRn = 14, CRm = 0 */
387 ARM64_FTR_REG(SYS_CNTFRQ_EL0
, ftr_single32
),
390 static int search_cmp_ftr_reg(const void *id
, const void *regp
)
392 return (int)(unsigned long)id
- (int)((const struct __ftr_reg_entry
*)regp
)->sys_id
;
396 * get_arm64_ftr_reg - Lookup a feature register entry using its
397 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
398 * ascending order of sys_id , we use binary search to find a matching
401 * returns - Upon success, matching ftr_reg entry for id.
402 * - NULL on failure. It is upto the caller to decide
403 * the impact of a failure.
405 static struct arm64_ftr_reg
*get_arm64_ftr_reg(u32 sys_id
)
407 const struct __ftr_reg_entry
*ret
;
409 ret
= bsearch((const void *)(unsigned long)sys_id
,
411 ARRAY_SIZE(arm64_ftr_regs
),
412 sizeof(arm64_ftr_regs
[0]),
419 static u64
arm64_ftr_set_value(const struct arm64_ftr_bits
*ftrp
, s64 reg
,
422 u64 mask
= arm64_ftr_mask(ftrp
);
425 reg
|= (ftr_val
<< ftrp
->shift
) & mask
;
429 static s64
arm64_ftr_safe_value(const struct arm64_ftr_bits
*ftrp
, s64
new,
434 switch (ftrp
->type
) {
436 ret
= ftrp
->safe_val
;
439 ret
= new < cur
? new : cur
;
441 case FTR_HIGHER_SAFE
:
442 ret
= new > cur
? new : cur
;
451 static void __init
sort_ftr_regs(void)
455 /* Check that the array is sorted so that we can do the binary search */
456 for (i
= 1; i
< ARRAY_SIZE(arm64_ftr_regs
); i
++)
457 BUG_ON(arm64_ftr_regs
[i
].sys_id
< arm64_ftr_regs
[i
- 1].sys_id
);
461 * Initialise the CPU feature register from Boot CPU values.
462 * Also initiliases the strict_mask for the register.
463 * Any bits that are not covered by an arm64_ftr_bits entry are considered
464 * RES0 for the system-wide value, and must strictly match.
466 static void __init
init_cpu_ftr_reg(u32 sys_reg
, u64
new)
469 u64 strict_mask
= ~0x0ULL
;
473 const struct arm64_ftr_bits
*ftrp
;
474 struct arm64_ftr_reg
*reg
= get_arm64_ftr_reg(sys_reg
);
478 for (ftrp
= reg
->ftr_bits
; ftrp
->width
; ftrp
++) {
479 u64 ftr_mask
= arm64_ftr_mask(ftrp
);
480 s64 ftr_new
= arm64_ftr_value(ftrp
, new);
482 val
= arm64_ftr_set_value(ftrp
, val
, ftr_new
);
484 valid_mask
|= ftr_mask
;
486 strict_mask
&= ~ftr_mask
;
488 user_mask
|= ftr_mask
;
490 reg
->user_val
= arm64_ftr_set_value(ftrp
,
498 reg
->strict_mask
= strict_mask
;
499 reg
->user_mask
= user_mask
;
502 void __init
init_cpu_features(struct cpuinfo_arm64
*info
)
504 /* Before we start using the tables, make sure it is sorted */
507 init_cpu_ftr_reg(SYS_CTR_EL0
, info
->reg_ctr
);
508 init_cpu_ftr_reg(SYS_DCZID_EL0
, info
->reg_dczid
);
509 init_cpu_ftr_reg(SYS_CNTFRQ_EL0
, info
->reg_cntfrq
);
510 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1
, info
->reg_id_aa64dfr0
);
511 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1
, info
->reg_id_aa64dfr1
);
512 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1
, info
->reg_id_aa64isar0
);
513 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1
, info
->reg_id_aa64isar1
);
514 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1
, info
->reg_id_aa64mmfr0
);
515 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1
, info
->reg_id_aa64mmfr1
);
516 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1
, info
->reg_id_aa64mmfr2
);
517 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1
, info
->reg_id_aa64pfr0
);
518 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1
, info
->reg_id_aa64pfr1
);
519 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1
, info
->reg_id_aa64zfr0
);
521 if (id_aa64pfr0_32bit_el0(info
->reg_id_aa64pfr0
)) {
522 init_cpu_ftr_reg(SYS_ID_DFR0_EL1
, info
->reg_id_dfr0
);
523 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1
, info
->reg_id_isar0
);
524 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1
, info
->reg_id_isar1
);
525 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1
, info
->reg_id_isar2
);
526 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1
, info
->reg_id_isar3
);
527 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1
, info
->reg_id_isar4
);
528 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1
, info
->reg_id_isar5
);
529 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1
, info
->reg_id_mmfr0
);
530 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1
, info
->reg_id_mmfr1
);
531 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1
, info
->reg_id_mmfr2
);
532 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1
, info
->reg_id_mmfr3
);
533 init_cpu_ftr_reg(SYS_ID_PFR0_EL1
, info
->reg_id_pfr0
);
534 init_cpu_ftr_reg(SYS_ID_PFR1_EL1
, info
->reg_id_pfr1
);
535 init_cpu_ftr_reg(SYS_MVFR0_EL1
, info
->reg_mvfr0
);
536 init_cpu_ftr_reg(SYS_MVFR1_EL1
, info
->reg_mvfr1
);
537 init_cpu_ftr_reg(SYS_MVFR2_EL1
, info
->reg_mvfr2
);
540 if (id_aa64pfr0_sve(info
->reg_id_aa64pfr0
)) {
541 init_cpu_ftr_reg(SYS_ZCR_EL1
, info
->reg_zcr
);
546 static void update_cpu_ftr_reg(struct arm64_ftr_reg
*reg
, u64
new)
548 const struct arm64_ftr_bits
*ftrp
;
550 for (ftrp
= reg
->ftr_bits
; ftrp
->width
; ftrp
++) {
551 s64 ftr_cur
= arm64_ftr_value(ftrp
, reg
->sys_val
);
552 s64 ftr_new
= arm64_ftr_value(ftrp
, new);
554 if (ftr_cur
== ftr_new
)
556 /* Find a safe value */
557 ftr_new
= arm64_ftr_safe_value(ftrp
, ftr_new
, ftr_cur
);
558 reg
->sys_val
= arm64_ftr_set_value(ftrp
, reg
->sys_val
, ftr_new
);
563 static int check_update_ftr_reg(u32 sys_id
, int cpu
, u64 val
, u64 boot
)
565 struct arm64_ftr_reg
*regp
= get_arm64_ftr_reg(sys_id
);
568 update_cpu_ftr_reg(regp
, val
);
569 if ((boot
& regp
->strict_mask
) == (val
& regp
->strict_mask
))
571 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
572 regp
->name
, boot
, cpu
, val
);
577 * Update system wide CPU feature registers with the values from a
578 * non-boot CPU. Also performs SANITY checks to make sure that there
579 * aren't any insane variations from that of the boot CPU.
581 void update_cpu_features(int cpu
,
582 struct cpuinfo_arm64
*info
,
583 struct cpuinfo_arm64
*boot
)
588 * The kernel can handle differing I-cache policies, but otherwise
589 * caches should look identical. Userspace JITs will make use of
592 taint
|= check_update_ftr_reg(SYS_CTR_EL0
, cpu
,
593 info
->reg_ctr
, boot
->reg_ctr
);
596 * Userspace may perform DC ZVA instructions. Mismatched block sizes
597 * could result in too much or too little memory being zeroed if a
598 * process is preempted and migrated between CPUs.
600 taint
|= check_update_ftr_reg(SYS_DCZID_EL0
, cpu
,
601 info
->reg_dczid
, boot
->reg_dczid
);
603 /* If different, timekeeping will be broken (especially with KVM) */
604 taint
|= check_update_ftr_reg(SYS_CNTFRQ_EL0
, cpu
,
605 info
->reg_cntfrq
, boot
->reg_cntfrq
);
608 * The kernel uses self-hosted debug features and expects CPUs to
609 * support identical debug features. We presently need CTX_CMPs, WRPs,
610 * and BRPs to be identical.
611 * ID_AA64DFR1 is currently RES0.
613 taint
|= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1
, cpu
,
614 info
->reg_id_aa64dfr0
, boot
->reg_id_aa64dfr0
);
615 taint
|= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1
, cpu
,
616 info
->reg_id_aa64dfr1
, boot
->reg_id_aa64dfr1
);
618 * Even in big.LITTLE, processors should be identical instruction-set
621 taint
|= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1
, cpu
,
622 info
->reg_id_aa64isar0
, boot
->reg_id_aa64isar0
);
623 taint
|= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1
, cpu
,
624 info
->reg_id_aa64isar1
, boot
->reg_id_aa64isar1
);
627 * Differing PARange support is fine as long as all peripherals and
628 * memory are mapped within the minimum PARange of all CPUs.
629 * Linux should not care about secure memory.
631 taint
|= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1
, cpu
,
632 info
->reg_id_aa64mmfr0
, boot
->reg_id_aa64mmfr0
);
633 taint
|= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1
, cpu
,
634 info
->reg_id_aa64mmfr1
, boot
->reg_id_aa64mmfr1
);
635 taint
|= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1
, cpu
,
636 info
->reg_id_aa64mmfr2
, boot
->reg_id_aa64mmfr2
);
639 * EL3 is not our concern.
640 * ID_AA64PFR1 is currently RES0.
642 taint
|= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1
, cpu
,
643 info
->reg_id_aa64pfr0
, boot
->reg_id_aa64pfr0
);
644 taint
|= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1
, cpu
,
645 info
->reg_id_aa64pfr1
, boot
->reg_id_aa64pfr1
);
647 taint
|= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1
, cpu
,
648 info
->reg_id_aa64zfr0
, boot
->reg_id_aa64zfr0
);
651 * If we have AArch32, we care about 32-bit features for compat.
652 * If the system doesn't support AArch32, don't update them.
654 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1
)) &&
655 id_aa64pfr0_32bit_el0(info
->reg_id_aa64pfr0
)) {
657 taint
|= check_update_ftr_reg(SYS_ID_DFR0_EL1
, cpu
,
658 info
->reg_id_dfr0
, boot
->reg_id_dfr0
);
659 taint
|= check_update_ftr_reg(SYS_ID_ISAR0_EL1
, cpu
,
660 info
->reg_id_isar0
, boot
->reg_id_isar0
);
661 taint
|= check_update_ftr_reg(SYS_ID_ISAR1_EL1
, cpu
,
662 info
->reg_id_isar1
, boot
->reg_id_isar1
);
663 taint
|= check_update_ftr_reg(SYS_ID_ISAR2_EL1
, cpu
,
664 info
->reg_id_isar2
, boot
->reg_id_isar2
);
665 taint
|= check_update_ftr_reg(SYS_ID_ISAR3_EL1
, cpu
,
666 info
->reg_id_isar3
, boot
->reg_id_isar3
);
667 taint
|= check_update_ftr_reg(SYS_ID_ISAR4_EL1
, cpu
,
668 info
->reg_id_isar4
, boot
->reg_id_isar4
);
669 taint
|= check_update_ftr_reg(SYS_ID_ISAR5_EL1
, cpu
,
670 info
->reg_id_isar5
, boot
->reg_id_isar5
);
673 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
674 * ACTLR formats could differ across CPUs and therefore would have to
675 * be trapped for virtualization anyway.
677 taint
|= check_update_ftr_reg(SYS_ID_MMFR0_EL1
, cpu
,
678 info
->reg_id_mmfr0
, boot
->reg_id_mmfr0
);
679 taint
|= check_update_ftr_reg(SYS_ID_MMFR1_EL1
, cpu
,
680 info
->reg_id_mmfr1
, boot
->reg_id_mmfr1
);
681 taint
|= check_update_ftr_reg(SYS_ID_MMFR2_EL1
, cpu
,
682 info
->reg_id_mmfr2
, boot
->reg_id_mmfr2
);
683 taint
|= check_update_ftr_reg(SYS_ID_MMFR3_EL1
, cpu
,
684 info
->reg_id_mmfr3
, boot
->reg_id_mmfr3
);
685 taint
|= check_update_ftr_reg(SYS_ID_PFR0_EL1
, cpu
,
686 info
->reg_id_pfr0
, boot
->reg_id_pfr0
);
687 taint
|= check_update_ftr_reg(SYS_ID_PFR1_EL1
, cpu
,
688 info
->reg_id_pfr1
, boot
->reg_id_pfr1
);
689 taint
|= check_update_ftr_reg(SYS_MVFR0_EL1
, cpu
,
690 info
->reg_mvfr0
, boot
->reg_mvfr0
);
691 taint
|= check_update_ftr_reg(SYS_MVFR1_EL1
, cpu
,
692 info
->reg_mvfr1
, boot
->reg_mvfr1
);
693 taint
|= check_update_ftr_reg(SYS_MVFR2_EL1
, cpu
,
694 info
->reg_mvfr2
, boot
->reg_mvfr2
);
697 if (id_aa64pfr0_sve(info
->reg_id_aa64pfr0
)) {
698 taint
|= check_update_ftr_reg(SYS_ZCR_EL1
, cpu
,
699 info
->reg_zcr
, boot
->reg_zcr
);
701 /* Probe vector lengths, unless we already gave up on SVE */
702 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1
)) &&
703 !sys_caps_initialised
)
708 * Mismatched CPU features are a recipe for disaster. Don't even
709 * pretend to support them.
712 pr_warn_once("Unsupported CPU feature variation detected.\n");
713 add_taint(TAINT_CPU_OUT_OF_SPEC
, LOCKDEP_STILL_OK
);
717 u64
read_sanitised_ftr_reg(u32 id
)
719 struct arm64_ftr_reg
*regp
= get_arm64_ftr_reg(id
);
721 /* We shouldn't get a request for an unsupported register */
723 return regp
->sys_val
;
726 #define read_sysreg_case(r) \
727 case r: return read_sysreg_s(r)
730 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
731 * Read the system register on the current CPU
733 static u64
__read_sysreg_by_encoding(u32 sys_id
)
736 read_sysreg_case(SYS_ID_PFR0_EL1
);
737 read_sysreg_case(SYS_ID_PFR1_EL1
);
738 read_sysreg_case(SYS_ID_DFR0_EL1
);
739 read_sysreg_case(SYS_ID_MMFR0_EL1
);
740 read_sysreg_case(SYS_ID_MMFR1_EL1
);
741 read_sysreg_case(SYS_ID_MMFR2_EL1
);
742 read_sysreg_case(SYS_ID_MMFR3_EL1
);
743 read_sysreg_case(SYS_ID_ISAR0_EL1
);
744 read_sysreg_case(SYS_ID_ISAR1_EL1
);
745 read_sysreg_case(SYS_ID_ISAR2_EL1
);
746 read_sysreg_case(SYS_ID_ISAR3_EL1
);
747 read_sysreg_case(SYS_ID_ISAR4_EL1
);
748 read_sysreg_case(SYS_ID_ISAR5_EL1
);
749 read_sysreg_case(SYS_MVFR0_EL1
);
750 read_sysreg_case(SYS_MVFR1_EL1
);
751 read_sysreg_case(SYS_MVFR2_EL1
);
753 read_sysreg_case(SYS_ID_AA64PFR0_EL1
);
754 read_sysreg_case(SYS_ID_AA64PFR1_EL1
);
755 read_sysreg_case(SYS_ID_AA64DFR0_EL1
);
756 read_sysreg_case(SYS_ID_AA64DFR1_EL1
);
757 read_sysreg_case(SYS_ID_AA64MMFR0_EL1
);
758 read_sysreg_case(SYS_ID_AA64MMFR1_EL1
);
759 read_sysreg_case(SYS_ID_AA64MMFR2_EL1
);
760 read_sysreg_case(SYS_ID_AA64ISAR0_EL1
);
761 read_sysreg_case(SYS_ID_AA64ISAR1_EL1
);
763 read_sysreg_case(SYS_CNTFRQ_EL0
);
764 read_sysreg_case(SYS_CTR_EL0
);
765 read_sysreg_case(SYS_DCZID_EL0
);
773 #include <linux/irqchip/arm-gic-v3.h>
776 feature_matches(u64 reg
, const struct arm64_cpu_capabilities
*entry
)
778 int val
= cpuid_feature_extract_field(reg
, entry
->field_pos
, entry
->sign
);
780 return val
>= entry
->min_field_value
;
784 has_cpuid_feature(const struct arm64_cpu_capabilities
*entry
, int scope
)
788 WARN_ON(scope
== SCOPE_LOCAL_CPU
&& preemptible());
789 if (scope
== SCOPE_SYSTEM
)
790 val
= read_sanitised_ftr_reg(entry
->sys_reg
);
792 val
= __read_sysreg_by_encoding(entry
->sys_reg
);
794 return feature_matches(val
, entry
);
797 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities
*entry
, int scope
)
801 if (!has_cpuid_feature(entry
, scope
))
804 has_sre
= gic_enable_sre();
806 pr_warn_once("%s present but disabled by higher exception level\n",
812 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities
*entry
, int __unused
)
814 u32 midr
= read_cpuid_id();
816 /* Cavium ThunderX pass 1.x and 2.x */
817 return MIDR_IS_CPU_MODEL_RANGE(midr
, MIDR_THUNDERX
,
818 MIDR_CPU_VAR_REV(0, 0),
819 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK
));
822 static bool runs_at_el2(const struct arm64_cpu_capabilities
*entry
, int __unused
)
824 return is_kernel_in_hyp_mode();
827 static bool hyp_offset_low(const struct arm64_cpu_capabilities
*entry
,
830 phys_addr_t idmap_addr
= __pa_symbol(__hyp_idmap_text_start
);
833 * Activate the lower HYP offset only if:
834 * - the idmap doesn't clash with it,
835 * - the kernel is not running at EL2.
837 return idmap_addr
> GENMASK(VA_BITS
- 2, 0) && !is_kernel_in_hyp_mode();
840 static bool has_no_fpsimd(const struct arm64_cpu_capabilities
*entry
, int __unused
)
842 u64 pfr0
= read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1
);
844 return cpuid_feature_extract_signed_field(pfr0
,
845 ID_AA64PFR0_FP_SHIFT
) < 0;
848 static const struct arm64_cpu_capabilities arm64_features
[] = {
850 .desc
= "GIC system register CPU interface",
851 .capability
= ARM64_HAS_SYSREG_GIC_CPUIF
,
852 .def_scope
= SCOPE_SYSTEM
,
853 .matches
= has_useable_gicv3_cpuif
,
854 .sys_reg
= SYS_ID_AA64PFR0_EL1
,
855 .field_pos
= ID_AA64PFR0_GIC_SHIFT
,
856 .sign
= FTR_UNSIGNED
,
857 .min_field_value
= 1,
859 #ifdef CONFIG_ARM64_PAN
861 .desc
= "Privileged Access Never",
862 .capability
= ARM64_HAS_PAN
,
863 .def_scope
= SCOPE_SYSTEM
,
864 .matches
= has_cpuid_feature
,
865 .sys_reg
= SYS_ID_AA64MMFR1_EL1
,
866 .field_pos
= ID_AA64MMFR1_PAN_SHIFT
,
867 .sign
= FTR_UNSIGNED
,
868 .min_field_value
= 1,
869 .enable
= cpu_enable_pan
,
871 #endif /* CONFIG_ARM64_PAN */
872 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
874 .desc
= "LSE atomic instructions",
875 .capability
= ARM64_HAS_LSE_ATOMICS
,
876 .def_scope
= SCOPE_SYSTEM
,
877 .matches
= has_cpuid_feature
,
878 .sys_reg
= SYS_ID_AA64ISAR0_EL1
,
879 .field_pos
= ID_AA64ISAR0_ATOMICS_SHIFT
,
880 .sign
= FTR_UNSIGNED
,
881 .min_field_value
= 2,
883 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
885 .desc
= "Software prefetching using PRFM",
886 .capability
= ARM64_HAS_NO_HW_PREFETCH
,
887 .def_scope
= SCOPE_SYSTEM
,
888 .matches
= has_no_hw_prefetch
,
890 #ifdef CONFIG_ARM64_UAO
892 .desc
= "User Access Override",
893 .capability
= ARM64_HAS_UAO
,
894 .def_scope
= SCOPE_SYSTEM
,
895 .matches
= has_cpuid_feature
,
896 .sys_reg
= SYS_ID_AA64MMFR2_EL1
,
897 .field_pos
= ID_AA64MMFR2_UAO_SHIFT
,
898 .min_field_value
= 1,
900 * We rely on stop_machine() calling uao_thread_switch() to set
901 * UAO immediately after patching.
904 #endif /* CONFIG_ARM64_UAO */
905 #ifdef CONFIG_ARM64_PAN
907 .capability
= ARM64_ALT_PAN_NOT_UAO
,
908 .def_scope
= SCOPE_SYSTEM
,
909 .matches
= cpufeature_pan_not_uao
,
911 #endif /* CONFIG_ARM64_PAN */
913 .desc
= "Virtualization Host Extensions",
914 .capability
= ARM64_HAS_VIRT_HOST_EXTN
,
915 .def_scope
= SCOPE_SYSTEM
,
916 .matches
= runs_at_el2
,
919 .desc
= "32-bit EL0 Support",
920 .capability
= ARM64_HAS_32BIT_EL0
,
921 .def_scope
= SCOPE_SYSTEM
,
922 .matches
= has_cpuid_feature
,
923 .sys_reg
= SYS_ID_AA64PFR0_EL1
,
924 .sign
= FTR_UNSIGNED
,
925 .field_pos
= ID_AA64PFR0_EL0_SHIFT
,
926 .min_field_value
= ID_AA64PFR0_EL0_32BIT_64BIT
,
929 .desc
= "Reduced HYP mapping offset",
930 .capability
= ARM64_HYP_OFFSET_LOW
,
931 .def_scope
= SCOPE_SYSTEM
,
932 .matches
= hyp_offset_low
,
935 /* FP/SIMD is not implemented */
936 .capability
= ARM64_HAS_NO_FPSIMD
,
937 .def_scope
= SCOPE_SYSTEM
,
938 .min_field_value
= 0,
939 .matches
= has_no_fpsimd
,
941 #ifdef CONFIG_ARM64_PMEM
943 .desc
= "Data cache clean to Point of Persistence",
944 .capability
= ARM64_HAS_DCPOP
,
945 .def_scope
= SCOPE_SYSTEM
,
946 .matches
= has_cpuid_feature
,
947 .sys_reg
= SYS_ID_AA64ISAR1_EL1
,
948 .field_pos
= ID_AA64ISAR1_DPB_SHIFT
,
949 .min_field_value
= 1,
952 #ifdef CONFIG_ARM64_SVE
954 .desc
= "Scalable Vector Extension",
955 .capability
= ARM64_SVE
,
956 .def_scope
= SCOPE_SYSTEM
,
957 .sys_reg
= SYS_ID_AA64PFR0_EL1
,
958 .sign
= FTR_UNSIGNED
,
959 .field_pos
= ID_AA64PFR0_SVE_SHIFT
,
960 .min_field_value
= ID_AA64PFR0_SVE
,
961 .matches
= has_cpuid_feature
,
962 .enable
= sve_kernel_enable
,
964 #endif /* CONFIG_ARM64_SVE */
968 #define HWCAP_CAP(reg, field, s, min_value, type, cap) \
971 .def_scope = SCOPE_SYSTEM, \
972 .matches = has_cpuid_feature, \
974 .field_pos = field, \
976 .min_field_value = min_value, \
977 .hwcap_type = type, \
981 static const struct arm64_cpu_capabilities arm64_elf_hwcaps
[] = {
982 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_AES_SHIFT
, FTR_UNSIGNED
, 2, CAP_HWCAP
, HWCAP_PMULL
),
983 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_AES_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_AES
),
984 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SHA1_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_SHA1
),
985 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SHA2_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_SHA2
),
986 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SHA2_SHIFT
, FTR_UNSIGNED
, 2, CAP_HWCAP
, HWCAP_SHA512
),
987 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_CRC32_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_CRC32
),
988 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_ATOMICS_SHIFT
, FTR_UNSIGNED
, 2, CAP_HWCAP
, HWCAP_ATOMICS
),
989 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_RDM_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_ASIMDRDM
),
990 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SHA3_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_SHA3
),
991 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SM3_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_SM3
),
992 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SM4_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_SM4
),
993 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_DP_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_ASIMDDP
),
994 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_FP_SHIFT
, FTR_SIGNED
, 0, CAP_HWCAP
, HWCAP_FP
),
995 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_FP_SHIFT
, FTR_SIGNED
, 1, CAP_HWCAP
, HWCAP_FPHP
),
996 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_ASIMD_SHIFT
, FTR_SIGNED
, 0, CAP_HWCAP
, HWCAP_ASIMD
),
997 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_ASIMD_SHIFT
, FTR_SIGNED
, 1, CAP_HWCAP
, HWCAP_ASIMDHP
),
998 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1
, ID_AA64ISAR1_DPB_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_DCPOP
),
999 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1
, ID_AA64ISAR1_JSCVT_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_JSCVT
),
1000 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1
, ID_AA64ISAR1_FCMA_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_FCMA
),
1001 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1
, ID_AA64ISAR1_LRCPC_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_LRCPC
),
1002 #ifdef CONFIG_ARM64_SVE
1003 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_SVE_SHIFT
, FTR_UNSIGNED
, ID_AA64PFR0_SVE
, CAP_HWCAP
, HWCAP_SVE
),
1008 static const struct arm64_cpu_capabilities compat_elf_hwcaps
[] = {
1009 #ifdef CONFIG_COMPAT
1010 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_AES_SHIFT
, FTR_UNSIGNED
, 2, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_PMULL
),
1011 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_AES_SHIFT
, FTR_UNSIGNED
, 1, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_AES
),
1012 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_SHA1_SHIFT
, FTR_UNSIGNED
, 1, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_SHA1
),
1013 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_SHA2_SHIFT
, FTR_UNSIGNED
, 1, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_SHA2
),
1014 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_CRC32_SHIFT
, FTR_UNSIGNED
, 1, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_CRC32
),
1019 static void __init
cap_set_elf_hwcap(const struct arm64_cpu_capabilities
*cap
)
1021 switch (cap
->hwcap_type
) {
1023 elf_hwcap
|= cap
->hwcap
;
1025 #ifdef CONFIG_COMPAT
1026 case CAP_COMPAT_HWCAP
:
1027 compat_elf_hwcap
|= (u32
)cap
->hwcap
;
1029 case CAP_COMPAT_HWCAP2
:
1030 compat_elf_hwcap2
|= (u32
)cap
->hwcap
;
1039 /* Check if we have a particular HWCAP enabled */
1040 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities
*cap
)
1044 switch (cap
->hwcap_type
) {
1046 rc
= (elf_hwcap
& cap
->hwcap
) != 0;
1048 #ifdef CONFIG_COMPAT
1049 case CAP_COMPAT_HWCAP
:
1050 rc
= (compat_elf_hwcap
& (u32
)cap
->hwcap
) != 0;
1052 case CAP_COMPAT_HWCAP2
:
1053 rc
= (compat_elf_hwcap2
& (u32
)cap
->hwcap
) != 0;
1064 static void __init
setup_elf_hwcaps(const struct arm64_cpu_capabilities
*hwcaps
)
1066 /* We support emulation of accesses to CPU ID feature registers */
1067 elf_hwcap
|= HWCAP_CPUID
;
1068 for (; hwcaps
->matches
; hwcaps
++)
1069 if (hwcaps
->matches(hwcaps
, hwcaps
->def_scope
))
1070 cap_set_elf_hwcap(hwcaps
);
1073 void update_cpu_capabilities(const struct arm64_cpu_capabilities
*caps
,
1076 for (; caps
->matches
; caps
++) {
1077 if (!caps
->matches(caps
, caps
->def_scope
))
1080 if (!cpus_have_cap(caps
->capability
) && caps
->desc
)
1081 pr_info("%s %s\n", info
, caps
->desc
);
1082 cpus_set_cap(caps
->capability
);
1087 * Run through the enabled capabilities and enable() it on all active
1090 void __init
enable_cpu_capabilities(const struct arm64_cpu_capabilities
*caps
)
1092 for (; caps
->matches
; caps
++) {
1093 unsigned int num
= caps
->capability
;
1095 if (!cpus_have_cap(num
))
1098 /* Ensure cpus_have_const_cap(num) works */
1099 static_branch_enable(&cpu_hwcap_keys
[num
]);
1103 * Use stop_machine() as it schedules the work allowing
1104 * us to modify PSTATE, instead of on_each_cpu() which
1105 * uses an IPI, giving us a PSTATE that disappears when
1108 stop_machine(caps
->enable
, NULL
, cpu_online_mask
);
1114 * Check for CPU features that are used in early boot
1115 * based on the Boot CPU value.
1117 static void check_early_cpu_features(void)
1119 verify_cpu_run_el();
1120 verify_cpu_asid_bits();
1124 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities
*caps
)
1127 for (; caps
->matches
; caps
++)
1128 if (cpus_have_elf_hwcap(caps
) && !caps
->matches(caps
, SCOPE_LOCAL_CPU
)) {
1129 pr_crit("CPU%d: missing HWCAP: %s\n",
1130 smp_processor_id(), caps
->desc
);
1136 verify_local_cpu_features(const struct arm64_cpu_capabilities
*caps
)
1138 for (; caps
->matches
; caps
++) {
1139 if (!cpus_have_cap(caps
->capability
))
1142 * If the new CPU misses an advertised feature, we cannot proceed
1143 * further, park the cpu.
1145 if (!caps
->matches(caps
, SCOPE_LOCAL_CPU
)) {
1146 pr_crit("CPU%d: missing feature: %s\n",
1147 smp_processor_id(), caps
->desc
);
1155 static void verify_sve_features(void)
1157 u64 safe_zcr
= read_sanitised_ftr_reg(SYS_ZCR_EL1
);
1158 u64 zcr
= read_zcr_features();
1160 unsigned int safe_len
= safe_zcr
& ZCR_ELx_LEN_MASK
;
1161 unsigned int len
= zcr
& ZCR_ELx_LEN_MASK
;
1163 if (len
< safe_len
|| sve_verify_vq_map()) {
1164 pr_crit("CPU%d: SVE: required vector length(s) missing\n",
1165 smp_processor_id());
1169 /* Add checks on other ZCR bits here if necessary */
1173 * Run through the enabled system capabilities and enable() it on this CPU.
1174 * The capabilities were decided based on the available CPUs at the boot time.
1175 * Any new CPU should match the system wide status of the capability. If the
1176 * new CPU doesn't have a capability which the system now has enabled, we
1177 * cannot do anything to fix it up and could cause unexpected failures. So
1180 static void verify_local_cpu_capabilities(void)
1182 verify_local_cpu_errata_workarounds();
1183 verify_local_cpu_features(arm64_features
);
1184 verify_local_elf_hwcaps(arm64_elf_hwcaps
);
1186 if (system_supports_32bit_el0())
1187 verify_local_elf_hwcaps(compat_elf_hwcaps
);
1189 if (system_supports_sve())
1190 verify_sve_features();
1193 void check_local_cpu_capabilities(void)
1196 * All secondary CPUs should conform to the early CPU features
1197 * in use by the kernel based on boot CPU.
1199 check_early_cpu_features();
1202 * If we haven't finalised the system capabilities, this CPU gets
1203 * a chance to update the errata work arounds.
1204 * Otherwise, this CPU should verify that it has all the system
1205 * advertised capabilities.
1207 if (!sys_caps_initialised
)
1208 update_cpu_errata_workarounds();
1210 verify_local_cpu_capabilities();
1213 static void __init
setup_feature_capabilities(void)
1215 update_cpu_capabilities(arm64_features
, "detected feature:");
1216 enable_cpu_capabilities(arm64_features
);
1219 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready
);
1220 EXPORT_SYMBOL(arm64_const_caps_ready
);
1222 static void __init
mark_const_caps_ready(void)
1224 static_branch_enable(&arm64_const_caps_ready
);
1228 * Check if the current CPU has a given feature capability.
1229 * Should be called from non-preemptible context.
1231 static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities
*cap_array
,
1234 const struct arm64_cpu_capabilities
*caps
;
1236 if (WARN_ON(preemptible()))
1239 for (caps
= cap_array
; caps
->desc
; caps
++)
1240 if (caps
->capability
== cap
&& caps
->matches
)
1241 return caps
->matches(caps
, SCOPE_LOCAL_CPU
);
1246 extern const struct arm64_cpu_capabilities arm64_errata
[];
1248 bool this_cpu_has_cap(unsigned int cap
)
1250 return (__this_cpu_has_cap(arm64_features
, cap
) ||
1251 __this_cpu_has_cap(arm64_errata
, cap
));
1254 void __init
setup_cpu_features(void)
1259 /* Set the CPU feature capabilies */
1260 setup_feature_capabilities();
1261 enable_errata_workarounds();
1262 mark_const_caps_ready();
1263 setup_elf_hwcaps(arm64_elf_hwcaps
);
1265 if (system_supports_32bit_el0())
1266 setup_elf_hwcaps(compat_elf_hwcaps
);
1270 /* Advertise that we have computed the system capabilities */
1271 set_sys_caps_initialised();
1274 * Check for sane CTR_EL0.CWG value.
1276 cwg
= cache_type_cwg();
1277 cls
= cache_line_size();
1279 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1281 if (L1_CACHE_BYTES
< cls
)
1282 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1283 L1_CACHE_BYTES
, cls
);
1286 static bool __maybe_unused
1287 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities
*entry
, int __unused
)
1289 return (cpus_have_const_cap(ARM64_HAS_PAN
) && !cpus_have_const_cap(ARM64_HAS_UAO
));
1293 * We emulate only the following system register space.
1294 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1295 * See Table C5-6 System instruction encodings for System register accesses,
1296 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1298 static inline bool __attribute_const__
is_emulated(u32 id
)
1300 return (sys_reg_Op0(id
) == 0x3 &&
1301 sys_reg_CRn(id
) == 0x0 &&
1302 sys_reg_Op1(id
) == 0x0 &&
1303 (sys_reg_CRm(id
) == 0 ||
1304 ((sys_reg_CRm(id
) >= 4) && (sys_reg_CRm(id
) <= 7))));
1308 * With CRm == 0, reg should be one of :
1309 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1311 static inline int emulate_id_reg(u32 id
, u64
*valp
)
1315 *valp
= read_cpuid_id();
1318 *valp
= SYS_MPIDR_SAFE_VAL
;
1320 case SYS_REVIDR_EL1
:
1321 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1331 static int emulate_sys_reg(u32 id
, u64
*valp
)
1333 struct arm64_ftr_reg
*regp
;
1335 if (!is_emulated(id
))
1338 if (sys_reg_CRm(id
) == 0)
1339 return emulate_id_reg(id
, valp
);
1341 regp
= get_arm64_ftr_reg(id
);
1343 *valp
= arm64_ftr_reg_user_value(regp
);
1346 * The untracked registers are either IMPLEMENTATION DEFINED
1347 * (e.g, ID_AFR0_EL1) or reserved RAZ.
1353 static int emulate_mrs(struct pt_regs
*regs
, u32 insn
)
1360 * sys_reg values are defined as used in mrs/msr instruction.
1361 * shift the imm value to get the encoding.
1363 sys_reg
= (u32
)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16
, insn
) << 5;
1364 rc
= emulate_sys_reg(sys_reg
, &val
);
1366 dst
= aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT
, insn
);
1367 pt_regs_write_reg(regs
, dst
, val
);
1368 arm64_skip_faulting_instruction(regs
, AARCH64_INSN_SIZE
);
1374 static struct undef_hook mrs_hook
= {
1375 .instr_mask
= 0xfff00000,
1376 .instr_val
= 0xd5300000,
1377 .pstate_mask
= COMPAT_PSR_MODE_MASK
,
1378 .pstate_val
= PSR_MODE_EL0t
,
1382 static int __init
enable_mrs_emulation(void)
1384 register_undef_hook(&mrs_hook
);
1388 core_initcall(enable_mrs_emulation
);