2 * Contains CPU feature definitions
4 * Copyright (C) 2015 ARM Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) "CPU features: " fmt
21 #include <linux/bsearch.h>
22 #include <linux/cpumask.h>
23 #include <linux/sort.h>
24 #include <linux/stop_machine.h>
25 #include <linux/types.h>
27 #include <linux/cpu.h>
29 #include <asm/cpufeature.h>
30 #include <asm/cpu_ops.h>
31 #include <asm/fpsimd.h>
32 #include <asm/mmu_context.h>
33 #include <asm/processor.h>
34 #include <asm/sysreg.h>
35 #include <asm/traps.h>
38 unsigned long elf_hwcap __read_mostly
;
39 EXPORT_SYMBOL_GPL(elf_hwcap
);
42 #define COMPAT_ELF_HWCAP_DEFAULT \
43 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
44 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
45 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
46 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
47 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
49 unsigned int compat_elf_hwcap __read_mostly
= COMPAT_ELF_HWCAP_DEFAULT
;
50 unsigned int compat_elf_hwcap2 __read_mostly
;
53 DECLARE_BITMAP(cpu_hwcaps
, ARM64_NCAPS
);
54 EXPORT_SYMBOL(cpu_hwcaps
);
57 * Flag to indicate if we have computed the system wide
58 * capabilities based on the boot time active CPUs. This
59 * will be used to determine if a new booting CPU should
60 * go through the verification process to make sure that it
61 * supports the system capabilities, without using a hotplug
64 static bool sys_caps_initialised
;
66 static inline void set_sys_caps_initialised(void)
68 sys_caps_initialised
= true;
71 static int dump_cpu_hwcaps(struct notifier_block
*self
, unsigned long v
, void *p
)
73 /* file-wide pr_fmt adds "CPU features: " prefix */
74 pr_emerg("0x%*pb\n", ARM64_NCAPS
, &cpu_hwcaps
);
78 static struct notifier_block cpu_hwcaps_notifier
= {
79 .notifier_call
= dump_cpu_hwcaps
82 static int __init
register_cpu_hwcaps_dumper(void)
84 atomic_notifier_chain_register(&panic_notifier_list
,
85 &cpu_hwcaps_notifier
);
88 __initcall(register_cpu_hwcaps_dumper
);
90 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys
, ARM64_NCAPS
);
91 EXPORT_SYMBOL(cpu_hwcap_keys
);
93 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
101 .safe_val = SAFE_VAL, \
104 /* Define a feature with unsigned values */
105 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
106 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
108 /* Define a feature with a signed value */
109 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
110 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
112 #define ARM64_FTR_END \
117 /* meta feature for alternatives */
118 static bool __maybe_unused
119 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities
*entry
, int __unused
);
123 * NOTE: Any changes to the visibility of features should be kept in
124 * sync with the documentation of the CPU feature register ABI.
126 static const struct arm64_ftr_bits ftr_id_aa64isar0
[] = {
127 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_TS_SHIFT
, 4, 0),
128 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_FHM_SHIFT
, 4, 0),
129 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_DP_SHIFT
, 4, 0),
130 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_SM4_SHIFT
, 4, 0),
131 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_SM3_SHIFT
, 4, 0),
132 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_SHA3_SHIFT
, 4, 0),
133 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_RDM_SHIFT
, 4, 0),
134 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_ATOMICS_SHIFT
, 4, 0),
135 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_CRC32_SHIFT
, 4, 0),
136 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_SHA2_SHIFT
, 4, 0),
137 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_SHA1_SHIFT
, 4, 0),
138 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_AES_SHIFT
, 4, 0),
142 static const struct arm64_ftr_bits ftr_id_aa64isar1
[] = {
143 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR1_LRCPC_SHIFT
, 4, 0),
144 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR1_FCMA_SHIFT
, 4, 0),
145 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR1_JSCVT_SHIFT
, 4, 0),
146 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR1_DPB_SHIFT
, 4, 0),
150 static const struct arm64_ftr_bits ftr_id_aa64pfr0
[] = {
151 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_CSV3_SHIFT
, 4, 0),
152 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_CSV2_SHIFT
, 4, 0),
153 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_DIT_SHIFT
, 4, 0),
154 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE
),
155 FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_SVE_SHIFT
, 4, 0),
156 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_RAS_SHIFT
, 4, 0),
157 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_GIC_SHIFT
, 4, 0),
158 S_ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_ASIMD_SHIFT
, 4, ID_AA64PFR0_ASIMD_NI
),
159 S_ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_FP_SHIFT
, 4, ID_AA64PFR0_FP_NI
),
160 /* Linux doesn't care about the EL3 */
161 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_EL3_SHIFT
, 4, 0),
162 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_EL2_SHIFT
, 4, 0),
163 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_EL1_SHIFT
, 4, ID_AA64PFR0_EL1_64BIT_ONLY
),
164 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_EL0_SHIFT
, 4, ID_AA64PFR0_EL0_64BIT_ONLY
),
168 static const struct arm64_ftr_bits ftr_id_aa64pfr1
[] = {
169 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR1_SSBS_SHIFT
, 4, ID_AA64PFR1_SSBS_PSTATE_NI
),
173 static const struct arm64_ftr_bits ftr_id_aa64mmfr0
[] = {
175 * We already refuse to boot CPUs that don't support our configured
176 * page size, so we can only detect mismatches for a page size other
177 * than the one we're currently using. Unfortunately, SoCs like this
178 * exist in the wild so, even though we don't like it, we'll have to go
179 * along with it and treat them as non-strict.
181 S_ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_TGRAN4_SHIFT
, 4, ID_AA64MMFR0_TGRAN4_NI
),
182 S_ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_TGRAN64_SHIFT
, 4, ID_AA64MMFR0_TGRAN64_NI
),
183 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_TGRAN16_SHIFT
, 4, ID_AA64MMFR0_TGRAN16_NI
),
185 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_BIGENDEL0_SHIFT
, 4, 0),
186 /* Linux shouldn't care about secure memory */
187 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_SNSMEM_SHIFT
, 4, 0),
188 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_BIGENDEL_SHIFT
, 4, 0),
189 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_ASID_SHIFT
, 4, 0),
191 * Differing PARange is fine as long as all peripherals and memory are mapped
192 * within the minimum PARange of all CPUs
194 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_PARANGE_SHIFT
, 4, 0),
198 static const struct arm64_ftr_bits ftr_id_aa64mmfr1
[] = {
199 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR1_PAN_SHIFT
, 4, 0),
200 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR1_LOR_SHIFT
, 4, 0),
201 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR1_HPD_SHIFT
, 4, 0),
202 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR1_VHE_SHIFT
, 4, 0),
203 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR1_VMIDBITS_SHIFT
, 4, 0),
204 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR1_HADBS_SHIFT
, 4, 0),
208 static const struct arm64_ftr_bits ftr_id_aa64mmfr2
[] = {
209 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR2_AT_SHIFT
, 4, 0),
210 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR2_LVA_SHIFT
, 4, 0),
211 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR2_IESB_SHIFT
, 4, 0),
212 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR2_LSM_SHIFT
, 4, 0),
213 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR2_UAO_SHIFT
, 4, 0),
214 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR2_CNP_SHIFT
, 4, 0),
218 static const struct arm64_ftr_bits ftr_ctr
[] = {
219 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_EXACT
, 31, 1, 1), /* RES1 */
220 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, 29, 1, 1), /* DIC */
221 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, 28, 1, 1), /* IDC */
222 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_HIGHER_OR_ZERO_SAFE
, 24, 4, 0), /* CWG */
223 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_HIGHER_OR_ZERO_SAFE
, 20, 4, 0), /* ERG */
224 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, CTR_DMINLINE_SHIFT
, 4, 1),
226 * Linux can handle differing I-cache policies. Userspace JITs will
227 * make use of *minLine.
228 * If we have differing I-cache policies, report it as the weakest - VIPT.
230 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_NONSTRICT
, FTR_EXACT
, 14, 2, ICACHE_POLICY_VIPT
), /* L1Ip */
231 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, CTR_IMINLINE_SHIFT
, 4, 0),
235 struct arm64_ftr_reg arm64_ftr_reg_ctrel0
= {
236 .name
= "SYS_CTR_EL0",
240 static const struct arm64_ftr_bits ftr_id_mmfr0
[] = {
241 S_ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 28, 4, 0xf), /* InnerShr */
242 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 24, 4, 0), /* FCSE */
243 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, 20, 4, 0), /* AuxReg */
244 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 16, 4, 0), /* TCM */
245 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 12, 4, 0), /* ShareLvl */
246 S_ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 8, 4, 0xf), /* OuterShr */
247 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0), /* PMSA */
248 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0), /* VMSA */
252 static const struct arm64_ftr_bits ftr_id_aa64dfr0
[] = {
253 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_EXACT
, 36, 28, 0),
254 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64DFR0_PMSVER_SHIFT
, 4, 0),
255 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64DFR0_CTX_CMPS_SHIFT
, 4, 0),
256 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64DFR0_WRPS_SHIFT
, 4, 0),
257 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64DFR0_BRPS_SHIFT
, 4, 0),
259 * We can instantiate multiple PMU instances with different levels
262 S_ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_EXACT
, ID_AA64DFR0_PMUVER_SHIFT
, 4, 0),
263 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_EXACT
, ID_AA64DFR0_TRACEVER_SHIFT
, 4, 0),
264 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_EXACT
, ID_AA64DFR0_DEBUGVER_SHIFT
, 4, 0x6),
268 static const struct arm64_ftr_bits ftr_mvfr2
[] = {
269 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0), /* FPMisc */
270 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0), /* SIMDMisc */
274 static const struct arm64_ftr_bits ftr_dczid
[] = {
275 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_EXACT
, 4, 1, 1), /* DZP */
276 ARM64_FTR_BITS(FTR_VISIBLE
, FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0), /* BS */
281 static const struct arm64_ftr_bits ftr_id_isar5
[] = {
282 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_ISAR5_RDM_SHIFT
, 4, 0),
283 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_ISAR5_CRC32_SHIFT
, 4, 0),
284 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_ISAR5_SHA2_SHIFT
, 4, 0),
285 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_ISAR5_SHA1_SHIFT
, 4, 0),
286 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_ISAR5_AES_SHIFT
, 4, 0),
287 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, ID_ISAR5_SEVL_SHIFT
, 4, 0),
291 static const struct arm64_ftr_bits ftr_id_mmfr4
[] = {
292 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0), /* ac2 */
296 static const struct arm64_ftr_bits ftr_id_pfr0
[] = {
297 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 12, 4, 0), /* State3 */
298 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 8, 4, 0), /* State2 */
299 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0), /* State1 */
300 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0), /* State0 */
304 static const struct arm64_ftr_bits ftr_id_dfr0
[] = {
305 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 28, 4, 0),
306 S_ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 24, 4, 0xf), /* PerfMon */
307 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 20, 4, 0),
308 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 16, 4, 0),
309 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 12, 4, 0),
310 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 8, 4, 0),
311 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0),
312 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0),
316 static const struct arm64_ftr_bits ftr_zcr
[] = {
317 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_NONSTRICT
, FTR_LOWER_SAFE
,
318 ZCR_ELx_LEN_SHIFT
, ZCR_ELx_LEN_SIZE
, 0), /* LEN */
323 * Common ftr bits for a 32bit register with all hidden, strict
324 * attributes, with 4bit feature fields and a default safe value of
325 * 0. Covers the following 32bit registers:
326 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
328 static const struct arm64_ftr_bits ftr_generic_32bits
[] = {
329 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 28, 4, 0),
330 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 24, 4, 0),
331 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 20, 4, 0),
332 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 16, 4, 0),
333 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 12, 4, 0),
334 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 8, 4, 0),
335 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0),
336 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0),
340 /* Table for a single 32bit feature value */
341 static const struct arm64_ftr_bits ftr_single32
[] = {
342 ARM64_FTR_BITS(FTR_HIDDEN
, FTR_STRICT
, FTR_EXACT
, 0, 32, 0),
346 static const struct arm64_ftr_bits ftr_raz
[] = {
350 #define ARM64_FTR_REG(id, table) { \
352 .reg = &(struct arm64_ftr_reg){ \
354 .ftr_bits = &((table)[0]), \
357 static const struct __ftr_reg_entry
{
359 struct arm64_ftr_reg
*reg
;
360 } arm64_ftr_regs
[] = {
362 /* Op1 = 0, CRn = 0, CRm = 1 */
363 ARM64_FTR_REG(SYS_ID_PFR0_EL1
, ftr_id_pfr0
),
364 ARM64_FTR_REG(SYS_ID_PFR1_EL1
, ftr_generic_32bits
),
365 ARM64_FTR_REG(SYS_ID_DFR0_EL1
, ftr_id_dfr0
),
366 ARM64_FTR_REG(SYS_ID_MMFR0_EL1
, ftr_id_mmfr0
),
367 ARM64_FTR_REG(SYS_ID_MMFR1_EL1
, ftr_generic_32bits
),
368 ARM64_FTR_REG(SYS_ID_MMFR2_EL1
, ftr_generic_32bits
),
369 ARM64_FTR_REG(SYS_ID_MMFR3_EL1
, ftr_generic_32bits
),
371 /* Op1 = 0, CRn = 0, CRm = 2 */
372 ARM64_FTR_REG(SYS_ID_ISAR0_EL1
, ftr_generic_32bits
),
373 ARM64_FTR_REG(SYS_ID_ISAR1_EL1
, ftr_generic_32bits
),
374 ARM64_FTR_REG(SYS_ID_ISAR2_EL1
, ftr_generic_32bits
),
375 ARM64_FTR_REG(SYS_ID_ISAR3_EL1
, ftr_generic_32bits
),
376 ARM64_FTR_REG(SYS_ID_ISAR4_EL1
, ftr_generic_32bits
),
377 ARM64_FTR_REG(SYS_ID_ISAR5_EL1
, ftr_id_isar5
),
378 ARM64_FTR_REG(SYS_ID_MMFR4_EL1
, ftr_id_mmfr4
),
380 /* Op1 = 0, CRn = 0, CRm = 3 */
381 ARM64_FTR_REG(SYS_MVFR0_EL1
, ftr_generic_32bits
),
382 ARM64_FTR_REG(SYS_MVFR1_EL1
, ftr_generic_32bits
),
383 ARM64_FTR_REG(SYS_MVFR2_EL1
, ftr_mvfr2
),
385 /* Op1 = 0, CRn = 0, CRm = 4 */
386 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1
, ftr_id_aa64pfr0
),
387 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1
, ftr_id_aa64pfr1
),
388 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1
, ftr_raz
),
390 /* Op1 = 0, CRn = 0, CRm = 5 */
391 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1
, ftr_id_aa64dfr0
),
392 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1
, ftr_raz
),
394 /* Op1 = 0, CRn = 0, CRm = 6 */
395 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1
, ftr_id_aa64isar0
),
396 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1
, ftr_id_aa64isar1
),
398 /* Op1 = 0, CRn = 0, CRm = 7 */
399 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1
, ftr_id_aa64mmfr0
),
400 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1
, ftr_id_aa64mmfr1
),
401 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1
, ftr_id_aa64mmfr2
),
403 /* Op1 = 0, CRn = 1, CRm = 2 */
404 ARM64_FTR_REG(SYS_ZCR_EL1
, ftr_zcr
),
406 /* Op1 = 3, CRn = 0, CRm = 0 */
407 { SYS_CTR_EL0
, &arm64_ftr_reg_ctrel0
},
408 ARM64_FTR_REG(SYS_DCZID_EL0
, ftr_dczid
),
410 /* Op1 = 3, CRn = 14, CRm = 0 */
411 ARM64_FTR_REG(SYS_CNTFRQ_EL0
, ftr_single32
),
414 static int search_cmp_ftr_reg(const void *id
, const void *regp
)
416 return (int)(unsigned long)id
- (int)((const struct __ftr_reg_entry
*)regp
)->sys_id
;
420 * get_arm64_ftr_reg - Lookup a feature register entry using its
421 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
422 * ascending order of sys_id , we use binary search to find a matching
425 * returns - Upon success, matching ftr_reg entry for id.
426 * - NULL on failure. It is upto the caller to decide
427 * the impact of a failure.
429 static struct arm64_ftr_reg
*get_arm64_ftr_reg(u32 sys_id
)
431 const struct __ftr_reg_entry
*ret
;
433 ret
= bsearch((const void *)(unsigned long)sys_id
,
435 ARRAY_SIZE(arm64_ftr_regs
),
436 sizeof(arm64_ftr_regs
[0]),
443 static u64
arm64_ftr_set_value(const struct arm64_ftr_bits
*ftrp
, s64 reg
,
446 u64 mask
= arm64_ftr_mask(ftrp
);
449 reg
|= (ftr_val
<< ftrp
->shift
) & mask
;
453 static s64
arm64_ftr_safe_value(const struct arm64_ftr_bits
*ftrp
, s64
new,
458 switch (ftrp
->type
) {
460 ret
= ftrp
->safe_val
;
463 ret
= new < cur
? new : cur
;
465 case FTR_HIGHER_OR_ZERO_SAFE
:
469 case FTR_HIGHER_SAFE
:
470 ret
= new > cur
? new : cur
;
479 static void __init
sort_ftr_regs(void)
483 /* Check that the array is sorted so that we can do the binary search */
484 for (i
= 1; i
< ARRAY_SIZE(arm64_ftr_regs
); i
++)
485 BUG_ON(arm64_ftr_regs
[i
].sys_id
< arm64_ftr_regs
[i
- 1].sys_id
);
489 * Initialise the CPU feature register from Boot CPU values.
490 * Also initiliases the strict_mask for the register.
491 * Any bits that are not covered by an arm64_ftr_bits entry are considered
492 * RES0 for the system-wide value, and must strictly match.
494 static void __init
init_cpu_ftr_reg(u32 sys_reg
, u64
new)
497 u64 strict_mask
= ~0x0ULL
;
501 const struct arm64_ftr_bits
*ftrp
;
502 struct arm64_ftr_reg
*reg
= get_arm64_ftr_reg(sys_reg
);
506 for (ftrp
= reg
->ftr_bits
; ftrp
->width
; ftrp
++) {
507 u64 ftr_mask
= arm64_ftr_mask(ftrp
);
508 s64 ftr_new
= arm64_ftr_value(ftrp
, new);
510 val
= arm64_ftr_set_value(ftrp
, val
, ftr_new
);
512 valid_mask
|= ftr_mask
;
514 strict_mask
&= ~ftr_mask
;
516 user_mask
|= ftr_mask
;
518 reg
->user_val
= arm64_ftr_set_value(ftrp
,
526 reg
->strict_mask
= strict_mask
;
527 reg
->user_mask
= user_mask
;
530 extern const struct arm64_cpu_capabilities arm64_errata
[];
531 static void __init
setup_boot_cpu_capabilities(void);
533 void __init
init_cpu_features(struct cpuinfo_arm64
*info
)
535 /* Before we start using the tables, make sure it is sorted */
538 init_cpu_ftr_reg(SYS_CTR_EL0
, info
->reg_ctr
);
539 init_cpu_ftr_reg(SYS_DCZID_EL0
, info
->reg_dczid
);
540 init_cpu_ftr_reg(SYS_CNTFRQ_EL0
, info
->reg_cntfrq
);
541 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1
, info
->reg_id_aa64dfr0
);
542 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1
, info
->reg_id_aa64dfr1
);
543 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1
, info
->reg_id_aa64isar0
);
544 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1
, info
->reg_id_aa64isar1
);
545 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1
, info
->reg_id_aa64mmfr0
);
546 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1
, info
->reg_id_aa64mmfr1
);
547 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1
, info
->reg_id_aa64mmfr2
);
548 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1
, info
->reg_id_aa64pfr0
);
549 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1
, info
->reg_id_aa64pfr1
);
550 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1
, info
->reg_id_aa64zfr0
);
552 if (id_aa64pfr0_32bit_el0(info
->reg_id_aa64pfr0
)) {
553 init_cpu_ftr_reg(SYS_ID_DFR0_EL1
, info
->reg_id_dfr0
);
554 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1
, info
->reg_id_isar0
);
555 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1
, info
->reg_id_isar1
);
556 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1
, info
->reg_id_isar2
);
557 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1
, info
->reg_id_isar3
);
558 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1
, info
->reg_id_isar4
);
559 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1
, info
->reg_id_isar5
);
560 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1
, info
->reg_id_mmfr0
);
561 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1
, info
->reg_id_mmfr1
);
562 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1
, info
->reg_id_mmfr2
);
563 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1
, info
->reg_id_mmfr3
);
564 init_cpu_ftr_reg(SYS_ID_PFR0_EL1
, info
->reg_id_pfr0
);
565 init_cpu_ftr_reg(SYS_ID_PFR1_EL1
, info
->reg_id_pfr1
);
566 init_cpu_ftr_reg(SYS_MVFR0_EL1
, info
->reg_mvfr0
);
567 init_cpu_ftr_reg(SYS_MVFR1_EL1
, info
->reg_mvfr1
);
568 init_cpu_ftr_reg(SYS_MVFR2_EL1
, info
->reg_mvfr2
);
571 if (id_aa64pfr0_sve(info
->reg_id_aa64pfr0
)) {
572 init_cpu_ftr_reg(SYS_ZCR_EL1
, info
->reg_zcr
);
577 * Detect and enable early CPU capabilities based on the boot CPU,
578 * after we have initialised the CPU feature infrastructure.
580 setup_boot_cpu_capabilities();
583 static void update_cpu_ftr_reg(struct arm64_ftr_reg
*reg
, u64
new)
585 const struct arm64_ftr_bits
*ftrp
;
587 for (ftrp
= reg
->ftr_bits
; ftrp
->width
; ftrp
++) {
588 s64 ftr_cur
= arm64_ftr_value(ftrp
, reg
->sys_val
);
589 s64 ftr_new
= arm64_ftr_value(ftrp
, new);
591 if (ftr_cur
== ftr_new
)
593 /* Find a safe value */
594 ftr_new
= arm64_ftr_safe_value(ftrp
, ftr_new
, ftr_cur
);
595 reg
->sys_val
= arm64_ftr_set_value(ftrp
, reg
->sys_val
, ftr_new
);
599 static int check_update_ftr_reg(u32 sys_id
, int cpu
, u64 val
, u64 boot
)
601 struct arm64_ftr_reg
*regp
= get_arm64_ftr_reg(sys_id
);
604 update_cpu_ftr_reg(regp
, val
);
605 if ((boot
& regp
->strict_mask
) == (val
& regp
->strict_mask
))
607 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
608 regp
->name
, boot
, cpu
, val
);
613 * Update system wide CPU feature registers with the values from a
614 * non-boot CPU. Also performs SANITY checks to make sure that there
615 * aren't any insane variations from that of the boot CPU.
617 void update_cpu_features(int cpu
,
618 struct cpuinfo_arm64
*info
,
619 struct cpuinfo_arm64
*boot
)
624 * The kernel can handle differing I-cache policies, but otherwise
625 * caches should look identical. Userspace JITs will make use of
628 taint
|= check_update_ftr_reg(SYS_CTR_EL0
, cpu
,
629 info
->reg_ctr
, boot
->reg_ctr
);
632 * Userspace may perform DC ZVA instructions. Mismatched block sizes
633 * could result in too much or too little memory being zeroed if a
634 * process is preempted and migrated between CPUs.
636 taint
|= check_update_ftr_reg(SYS_DCZID_EL0
, cpu
,
637 info
->reg_dczid
, boot
->reg_dczid
);
639 /* If different, timekeeping will be broken (especially with KVM) */
640 taint
|= check_update_ftr_reg(SYS_CNTFRQ_EL0
, cpu
,
641 info
->reg_cntfrq
, boot
->reg_cntfrq
);
644 * The kernel uses self-hosted debug features and expects CPUs to
645 * support identical debug features. We presently need CTX_CMPs, WRPs,
646 * and BRPs to be identical.
647 * ID_AA64DFR1 is currently RES0.
649 taint
|= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1
, cpu
,
650 info
->reg_id_aa64dfr0
, boot
->reg_id_aa64dfr0
);
651 taint
|= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1
, cpu
,
652 info
->reg_id_aa64dfr1
, boot
->reg_id_aa64dfr1
);
654 * Even in big.LITTLE, processors should be identical instruction-set
657 taint
|= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1
, cpu
,
658 info
->reg_id_aa64isar0
, boot
->reg_id_aa64isar0
);
659 taint
|= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1
, cpu
,
660 info
->reg_id_aa64isar1
, boot
->reg_id_aa64isar1
);
663 * Differing PARange support is fine as long as all peripherals and
664 * memory are mapped within the minimum PARange of all CPUs.
665 * Linux should not care about secure memory.
667 taint
|= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1
, cpu
,
668 info
->reg_id_aa64mmfr0
, boot
->reg_id_aa64mmfr0
);
669 taint
|= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1
, cpu
,
670 info
->reg_id_aa64mmfr1
, boot
->reg_id_aa64mmfr1
);
671 taint
|= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1
, cpu
,
672 info
->reg_id_aa64mmfr2
, boot
->reg_id_aa64mmfr2
);
675 * EL3 is not our concern.
677 taint
|= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1
, cpu
,
678 info
->reg_id_aa64pfr0
, boot
->reg_id_aa64pfr0
);
679 taint
|= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1
, cpu
,
680 info
->reg_id_aa64pfr1
, boot
->reg_id_aa64pfr1
);
682 taint
|= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1
, cpu
,
683 info
->reg_id_aa64zfr0
, boot
->reg_id_aa64zfr0
);
686 * If we have AArch32, we care about 32-bit features for compat.
687 * If the system doesn't support AArch32, don't update them.
689 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1
)) &&
690 id_aa64pfr0_32bit_el0(info
->reg_id_aa64pfr0
)) {
692 taint
|= check_update_ftr_reg(SYS_ID_DFR0_EL1
, cpu
,
693 info
->reg_id_dfr0
, boot
->reg_id_dfr0
);
694 taint
|= check_update_ftr_reg(SYS_ID_ISAR0_EL1
, cpu
,
695 info
->reg_id_isar0
, boot
->reg_id_isar0
);
696 taint
|= check_update_ftr_reg(SYS_ID_ISAR1_EL1
, cpu
,
697 info
->reg_id_isar1
, boot
->reg_id_isar1
);
698 taint
|= check_update_ftr_reg(SYS_ID_ISAR2_EL1
, cpu
,
699 info
->reg_id_isar2
, boot
->reg_id_isar2
);
700 taint
|= check_update_ftr_reg(SYS_ID_ISAR3_EL1
, cpu
,
701 info
->reg_id_isar3
, boot
->reg_id_isar3
);
702 taint
|= check_update_ftr_reg(SYS_ID_ISAR4_EL1
, cpu
,
703 info
->reg_id_isar4
, boot
->reg_id_isar4
);
704 taint
|= check_update_ftr_reg(SYS_ID_ISAR5_EL1
, cpu
,
705 info
->reg_id_isar5
, boot
->reg_id_isar5
);
708 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
709 * ACTLR formats could differ across CPUs and therefore would have to
710 * be trapped for virtualization anyway.
712 taint
|= check_update_ftr_reg(SYS_ID_MMFR0_EL1
, cpu
,
713 info
->reg_id_mmfr0
, boot
->reg_id_mmfr0
);
714 taint
|= check_update_ftr_reg(SYS_ID_MMFR1_EL1
, cpu
,
715 info
->reg_id_mmfr1
, boot
->reg_id_mmfr1
);
716 taint
|= check_update_ftr_reg(SYS_ID_MMFR2_EL1
, cpu
,
717 info
->reg_id_mmfr2
, boot
->reg_id_mmfr2
);
718 taint
|= check_update_ftr_reg(SYS_ID_MMFR3_EL1
, cpu
,
719 info
->reg_id_mmfr3
, boot
->reg_id_mmfr3
);
720 taint
|= check_update_ftr_reg(SYS_ID_PFR0_EL1
, cpu
,
721 info
->reg_id_pfr0
, boot
->reg_id_pfr0
);
722 taint
|= check_update_ftr_reg(SYS_ID_PFR1_EL1
, cpu
,
723 info
->reg_id_pfr1
, boot
->reg_id_pfr1
);
724 taint
|= check_update_ftr_reg(SYS_MVFR0_EL1
, cpu
,
725 info
->reg_mvfr0
, boot
->reg_mvfr0
);
726 taint
|= check_update_ftr_reg(SYS_MVFR1_EL1
, cpu
,
727 info
->reg_mvfr1
, boot
->reg_mvfr1
);
728 taint
|= check_update_ftr_reg(SYS_MVFR2_EL1
, cpu
,
729 info
->reg_mvfr2
, boot
->reg_mvfr2
);
732 if (id_aa64pfr0_sve(info
->reg_id_aa64pfr0
)) {
733 taint
|= check_update_ftr_reg(SYS_ZCR_EL1
, cpu
,
734 info
->reg_zcr
, boot
->reg_zcr
);
736 /* Probe vector lengths, unless we already gave up on SVE */
737 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1
)) &&
738 !sys_caps_initialised
)
743 * Mismatched CPU features are a recipe for disaster. Don't even
744 * pretend to support them.
747 pr_warn_once("Unsupported CPU feature variation detected.\n");
748 add_taint(TAINT_CPU_OUT_OF_SPEC
, LOCKDEP_STILL_OK
);
752 u64
read_sanitised_ftr_reg(u32 id
)
754 struct arm64_ftr_reg
*regp
= get_arm64_ftr_reg(id
);
756 /* We shouldn't get a request for an unsupported register */
758 return regp
->sys_val
;
761 #define read_sysreg_case(r) \
762 case r: return read_sysreg_s(r)
765 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
766 * Read the system register on the current CPU
768 static u64
__read_sysreg_by_encoding(u32 sys_id
)
771 read_sysreg_case(SYS_ID_PFR0_EL1
);
772 read_sysreg_case(SYS_ID_PFR1_EL1
);
773 read_sysreg_case(SYS_ID_DFR0_EL1
);
774 read_sysreg_case(SYS_ID_MMFR0_EL1
);
775 read_sysreg_case(SYS_ID_MMFR1_EL1
);
776 read_sysreg_case(SYS_ID_MMFR2_EL1
);
777 read_sysreg_case(SYS_ID_MMFR3_EL1
);
778 read_sysreg_case(SYS_ID_ISAR0_EL1
);
779 read_sysreg_case(SYS_ID_ISAR1_EL1
);
780 read_sysreg_case(SYS_ID_ISAR2_EL1
);
781 read_sysreg_case(SYS_ID_ISAR3_EL1
);
782 read_sysreg_case(SYS_ID_ISAR4_EL1
);
783 read_sysreg_case(SYS_ID_ISAR5_EL1
);
784 read_sysreg_case(SYS_MVFR0_EL1
);
785 read_sysreg_case(SYS_MVFR1_EL1
);
786 read_sysreg_case(SYS_MVFR2_EL1
);
788 read_sysreg_case(SYS_ID_AA64PFR0_EL1
);
789 read_sysreg_case(SYS_ID_AA64PFR1_EL1
);
790 read_sysreg_case(SYS_ID_AA64DFR0_EL1
);
791 read_sysreg_case(SYS_ID_AA64DFR1_EL1
);
792 read_sysreg_case(SYS_ID_AA64MMFR0_EL1
);
793 read_sysreg_case(SYS_ID_AA64MMFR1_EL1
);
794 read_sysreg_case(SYS_ID_AA64MMFR2_EL1
);
795 read_sysreg_case(SYS_ID_AA64ISAR0_EL1
);
796 read_sysreg_case(SYS_ID_AA64ISAR1_EL1
);
798 read_sysreg_case(SYS_CNTFRQ_EL0
);
799 read_sysreg_case(SYS_CTR_EL0
);
800 read_sysreg_case(SYS_DCZID_EL0
);
808 #include <linux/irqchip/arm-gic-v3.h>
811 feature_matches(u64 reg
, const struct arm64_cpu_capabilities
*entry
)
813 int val
= cpuid_feature_extract_field(reg
, entry
->field_pos
, entry
->sign
);
815 return val
>= entry
->min_field_value
;
819 has_cpuid_feature(const struct arm64_cpu_capabilities
*entry
, int scope
)
823 WARN_ON(scope
== SCOPE_LOCAL_CPU
&& preemptible());
824 if (scope
== SCOPE_SYSTEM
)
825 val
= read_sanitised_ftr_reg(entry
->sys_reg
);
827 val
= __read_sysreg_by_encoding(entry
->sys_reg
);
829 return feature_matches(val
, entry
);
832 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities
*entry
, int scope
)
836 if (!has_cpuid_feature(entry
, scope
))
839 has_sre
= gic_enable_sre();
841 pr_warn_once("%s present but disabled by higher exception level\n",
847 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities
*entry
, int __unused
)
849 u32 midr
= read_cpuid_id();
851 /* Cavium ThunderX pass 1.x and 2.x */
852 return MIDR_IS_CPU_MODEL_RANGE(midr
, MIDR_THUNDERX
,
853 MIDR_CPU_VAR_REV(0, 0),
854 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK
));
857 static bool hyp_offset_low(const struct arm64_cpu_capabilities
*entry
,
860 phys_addr_t idmap_addr
= __pa_symbol(__hyp_idmap_text_start
);
863 * Activate the lower HYP offset only if:
864 * - the idmap doesn't clash with it,
865 * - the kernel is not running at EL2.
867 return idmap_addr
> GENMASK(VA_BITS
- 2, 0) && !is_kernel_in_hyp_mode();
870 static bool has_no_fpsimd(const struct arm64_cpu_capabilities
*entry
, int __unused
)
872 u64 pfr0
= read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1
);
874 return cpuid_feature_extract_signed_field(pfr0
,
875 ID_AA64PFR0_FP_SHIFT
) < 0;
878 static bool __meltdown_safe
= true;
879 static int __kpti_forced
; /* 0: not forced, >0: forced on, <0: forced off */
881 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities
*entry
,
884 /* List of CPUs that are not vulnerable and don't need KPTI */
885 static const struct midr_range kpti_safe_list
[] = {
886 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2
),
887 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN
),
888 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35
),
889 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53
),
890 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55
),
891 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57
),
892 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72
),
893 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73
),
894 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110
),
897 char const *str
= "kpti command line option";
900 meltdown_safe
= is_midr_in_range_list(read_cpuid_id(), kpti_safe_list
);
902 /* Defer to CPU feature registers */
903 if (has_cpuid_feature(entry
, scope
))
904 meltdown_safe
= true;
907 __meltdown_safe
= false;
910 * For reasons that aren't entirely clear, enabling KPTI on Cavium
911 * ThunderX leads to apparent I-cache corruption of kernel text, which
912 * ends as well as you might imagine. Don't even try.
914 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456
)) {
915 str
= "ARM64_WORKAROUND_CAVIUM_27456";
919 /* Useful for KASLR robustness */
920 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE
) && kaslr_offset() > 0) {
921 if (!__kpti_forced
) {
927 if (cpu_mitigations_off() && !__kpti_forced
) {
928 str
= "mitigations=off";
932 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0
)) {
933 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
939 pr_info_once("kernel page table isolation forced %s by %s\n",
940 __kpti_forced
> 0 ? "ON" : "OFF", str
);
941 return __kpti_forced
> 0;
944 return !meltdown_safe
;
947 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
949 kpti_install_ng_mappings(const struct arm64_cpu_capabilities
*__unused
)
951 typedef void (kpti_remap_fn
)(int, int, phys_addr_t
);
952 extern kpti_remap_fn idmap_kpti_install_ng_mappings
;
953 kpti_remap_fn
*remap_fn
;
955 static bool kpti_applied
= false;
956 int cpu
= smp_processor_id();
961 remap_fn
= (void *)__pa_symbol(idmap_kpti_install_ng_mappings
);
964 remap_fn(cpu
, num_online_cpus(), __pa_symbol(swapper_pg_dir
));
965 cpu_uninstall_idmap();
974 kpti_install_ng_mappings(const struct arm64_cpu_capabilities
*__unused
)
977 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
979 static int __init
parse_kpti(char *str
)
982 int ret
= strtobool(str
, &enabled
);
987 __kpti_forced
= enabled
? 1 : -1;
990 early_param("kpti", parse_kpti
);
992 #ifdef CONFIG_ARM64_VHE
993 static bool runs_at_el2(const struct arm64_cpu_capabilities
*entry
, int __unused
)
995 return is_kernel_in_hyp_mode();
998 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities
*__unused
)
1001 * Copy register values that aren't redirected by hardware.
1003 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1004 * this value to tpidr_el2 before we patch the code. Once we've done
1005 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1008 if (!alternatives_applied
)
1009 write_sysreg(read_sysreg(tpidr_el1
), tpidr_el2
);
1013 #ifdef CONFIG_ARM64_SSBD
1014 static int ssbs_emulation_handler(struct pt_regs
*regs
, u32 instr
)
1016 if (user_mode(regs
))
1019 if (instr
& BIT(CRm_shift
))
1020 regs
->pstate
|= PSR_SSBS_BIT
;
1022 regs
->pstate
&= ~PSR_SSBS_BIT
;
1024 arm64_skip_faulting_instruction(regs
, 4);
1028 static struct undef_hook ssbs_emulation_hook
= {
1029 .instr_mask
= ~(1U << CRm_shift
),
1030 .instr_val
= 0xd500001f | REG_PSTATE_SSBS_IMM
,
1031 .fn
= ssbs_emulation_handler
,
1034 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities
*__unused
)
1036 static bool undef_hook_registered
= false;
1037 static DEFINE_SPINLOCK(hook_lock
);
1039 spin_lock(&hook_lock
);
1040 if (!undef_hook_registered
) {
1041 register_undef_hook(&ssbs_emulation_hook
);
1042 undef_hook_registered
= true;
1044 spin_unlock(&hook_lock
);
1046 if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE
) {
1047 sysreg_clear_set(sctlr_el1
, 0, SCTLR_ELx_DSSBS
);
1048 arm64_set_ssbd_mitigation(false);
1050 arm64_set_ssbd_mitigation(true);
1053 #endif /* CONFIG_ARM64_SSBD */
1055 static const struct arm64_cpu_capabilities arm64_features
[] = {
1057 .desc
= "GIC system register CPU interface",
1058 .capability
= ARM64_HAS_SYSREG_GIC_CPUIF
,
1059 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1060 .matches
= has_useable_gicv3_cpuif
,
1061 .sys_reg
= SYS_ID_AA64PFR0_EL1
,
1062 .field_pos
= ID_AA64PFR0_GIC_SHIFT
,
1063 .sign
= FTR_UNSIGNED
,
1064 .min_field_value
= 1,
1066 #ifdef CONFIG_ARM64_PAN
1068 .desc
= "Privileged Access Never",
1069 .capability
= ARM64_HAS_PAN
,
1070 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1071 .matches
= has_cpuid_feature
,
1072 .sys_reg
= SYS_ID_AA64MMFR1_EL1
,
1073 .field_pos
= ID_AA64MMFR1_PAN_SHIFT
,
1074 .sign
= FTR_UNSIGNED
,
1075 .min_field_value
= 1,
1076 .cpu_enable
= cpu_enable_pan
,
1078 #endif /* CONFIG_ARM64_PAN */
1079 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1081 .desc
= "LSE atomic instructions",
1082 .capability
= ARM64_HAS_LSE_ATOMICS
,
1083 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1084 .matches
= has_cpuid_feature
,
1085 .sys_reg
= SYS_ID_AA64ISAR0_EL1
,
1086 .field_pos
= ID_AA64ISAR0_ATOMICS_SHIFT
,
1087 .sign
= FTR_UNSIGNED
,
1088 .min_field_value
= 2,
1090 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1092 .desc
= "Software prefetching using PRFM",
1093 .capability
= ARM64_HAS_NO_HW_PREFETCH
,
1094 .type
= ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE
,
1095 .matches
= has_no_hw_prefetch
,
1097 #ifdef CONFIG_ARM64_UAO
1099 .desc
= "User Access Override",
1100 .capability
= ARM64_HAS_UAO
,
1101 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1102 .matches
= has_cpuid_feature
,
1103 .sys_reg
= SYS_ID_AA64MMFR2_EL1
,
1104 .field_pos
= ID_AA64MMFR2_UAO_SHIFT
,
1105 .min_field_value
= 1,
1107 * We rely on stop_machine() calling uao_thread_switch() to set
1108 * UAO immediately after patching.
1111 #endif /* CONFIG_ARM64_UAO */
1112 #ifdef CONFIG_ARM64_PAN
1114 .capability
= ARM64_ALT_PAN_NOT_UAO
,
1115 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1116 .matches
= cpufeature_pan_not_uao
,
1118 #endif /* CONFIG_ARM64_PAN */
1119 #ifdef CONFIG_ARM64_VHE
1121 .desc
= "Virtualization Host Extensions",
1122 .capability
= ARM64_HAS_VIRT_HOST_EXTN
,
1123 .type
= ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE
,
1124 .matches
= runs_at_el2
,
1125 .cpu_enable
= cpu_copy_el2regs
,
1127 #endif /* CONFIG_ARM64_VHE */
1129 .desc
= "32-bit EL0 Support",
1130 .capability
= ARM64_HAS_32BIT_EL0
,
1131 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1132 .matches
= has_cpuid_feature
,
1133 .sys_reg
= SYS_ID_AA64PFR0_EL1
,
1134 .sign
= FTR_UNSIGNED
,
1135 .field_pos
= ID_AA64PFR0_EL0_SHIFT
,
1136 .min_field_value
= ID_AA64PFR0_EL0_32BIT_64BIT
,
1139 .desc
= "Reduced HYP mapping offset",
1140 .capability
= ARM64_HYP_OFFSET_LOW
,
1141 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1142 .matches
= hyp_offset_low
,
1145 .desc
= "Kernel page table isolation (KPTI)",
1146 .capability
= ARM64_UNMAP_KERNEL_AT_EL0
,
1147 .type
= ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE
,
1149 * The ID feature fields below are used to indicate that
1150 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1153 .sys_reg
= SYS_ID_AA64PFR0_EL1
,
1154 .field_pos
= ID_AA64PFR0_CSV3_SHIFT
,
1155 .min_field_value
= 1,
1156 .matches
= unmap_kernel_at_el0
,
1157 .cpu_enable
= kpti_install_ng_mappings
,
1160 /* FP/SIMD is not implemented */
1161 .capability
= ARM64_HAS_NO_FPSIMD
,
1162 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1163 .min_field_value
= 0,
1164 .matches
= has_no_fpsimd
,
1166 #ifdef CONFIG_ARM64_PMEM
1168 .desc
= "Data cache clean to Point of Persistence",
1169 .capability
= ARM64_HAS_DCPOP
,
1170 .type
= ARM64_CPUCAP_SYSTEM_FEATURE
,
1171 .matches
= has_cpuid_feature
,
1172 .sys_reg
= SYS_ID_AA64ISAR1_EL1
,
1173 .field_pos
= ID_AA64ISAR1_DPB_SHIFT
,
1174 .min_field_value
= 1,
1177 #ifdef CONFIG_ARM64_SVE
1179 .desc
= "Scalable Vector Extension",
1180 .capability
= ARM64_SVE
,
1181 .type
= ARM64_CPUCAP_SCOPE_SYSTEM
,
1182 .sys_reg
= SYS_ID_AA64PFR0_EL1
,
1183 .sign
= FTR_UNSIGNED
,
1184 .field_pos
= ID_AA64PFR0_SVE_SHIFT
,
1185 .min_field_value
= ID_AA64PFR0_SVE
,
1186 .matches
= has_cpuid_feature
,
1187 .cpu_enable
= sve_kernel_enable
,
1189 #endif /* CONFIG_ARM64_SVE */
1190 #ifdef CONFIG_ARM64_RAS_EXTN
1192 .desc
= "RAS Extension Support",
1193 .capability
= ARM64_HAS_RAS_EXTN
,
1194 .type
= ARM64_CPUCAP_SCOPE_SYSTEM
,
1195 .matches
= has_cpuid_feature
,
1196 .sys_reg
= SYS_ID_AA64PFR0_EL1
,
1197 .sign
= FTR_UNSIGNED
,
1198 .field_pos
= ID_AA64PFR0_RAS_SHIFT
,
1199 .min_field_value
= ID_AA64PFR0_RAS_V1
,
1200 .cpu_enable
= cpu_clear_disr
,
1202 #endif /* CONFIG_ARM64_RAS_EXTN */
1206 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
1209 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
1210 .matches = has_cpuid_feature, \
1212 .field_pos = field, \
1214 .min_field_value = min_value, \
1215 .hwcap_type = cap_type, \
1219 static const struct arm64_cpu_capabilities arm64_elf_hwcaps
[] = {
1220 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_AES_SHIFT
, FTR_UNSIGNED
, 2, CAP_HWCAP
, HWCAP_PMULL
),
1221 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_AES_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_AES
),
1222 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SHA1_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_SHA1
),
1223 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SHA2_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_SHA2
),
1224 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SHA2_SHIFT
, FTR_UNSIGNED
, 2, CAP_HWCAP
, HWCAP_SHA512
),
1225 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_CRC32_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_CRC32
),
1226 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_ATOMICS_SHIFT
, FTR_UNSIGNED
, 2, CAP_HWCAP
, HWCAP_ATOMICS
),
1227 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_RDM_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_ASIMDRDM
),
1228 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SHA3_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_SHA3
),
1229 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SM3_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_SM3
),
1230 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SM4_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_SM4
),
1231 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_DP_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_ASIMDDP
),
1232 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_FHM_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_ASIMDFHM
),
1233 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_TS_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_FLAGM
),
1234 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_FP_SHIFT
, FTR_SIGNED
, 0, CAP_HWCAP
, HWCAP_FP
),
1235 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_FP_SHIFT
, FTR_SIGNED
, 1, CAP_HWCAP
, HWCAP_FPHP
),
1236 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_ASIMD_SHIFT
, FTR_SIGNED
, 0, CAP_HWCAP
, HWCAP_ASIMD
),
1237 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_ASIMD_SHIFT
, FTR_SIGNED
, 1, CAP_HWCAP
, HWCAP_ASIMDHP
),
1238 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_DIT_SHIFT
, FTR_SIGNED
, 1, CAP_HWCAP
, HWCAP_DIT
),
1239 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1
, ID_AA64ISAR1_DPB_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_DCPOP
),
1240 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1
, ID_AA64ISAR1_JSCVT_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_JSCVT
),
1241 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1
, ID_AA64ISAR1_FCMA_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_FCMA
),
1242 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1
, ID_AA64ISAR1_LRCPC_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_LRCPC
),
1243 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1
, ID_AA64ISAR1_LRCPC_SHIFT
, FTR_UNSIGNED
, 2, CAP_HWCAP
, HWCAP_ILRCPC
),
1244 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1
, ID_AA64MMFR2_AT_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_USCAT
),
1245 HWCAP_CAP(SYS_ID_AA64PFR1_EL1
, ID_AA64PFR1_SSBS_SHIFT
, FTR_UNSIGNED
, ID_AA64PFR1_SSBS_PSTATE_INSNS
, CAP_HWCAP
, HWCAP_SSBS
),
1246 #ifdef CONFIG_ARM64_SVE
1247 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_SVE_SHIFT
, FTR_UNSIGNED
, ID_AA64PFR0_SVE
, CAP_HWCAP
, HWCAP_SVE
),
1249 #ifdef CONFIG_ARM64_SSBD
1251 .desc
= "Speculative Store Bypassing Safe (SSBS)",
1252 .capability
= ARM64_SSBS
,
1253 .type
= ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE
,
1254 .matches
= has_cpuid_feature
,
1255 .sys_reg
= SYS_ID_AA64PFR1_EL1
,
1256 .field_pos
= ID_AA64PFR1_SSBS_SHIFT
,
1257 .sign
= FTR_UNSIGNED
,
1258 .min_field_value
= ID_AA64PFR1_SSBS_PSTATE_ONLY
,
1259 .cpu_enable
= cpu_enable_ssbs
,
1265 static const struct arm64_cpu_capabilities compat_elf_hwcaps
[] = {
1266 #ifdef CONFIG_COMPAT
1267 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_AES_SHIFT
, FTR_UNSIGNED
, 2, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_PMULL
),
1268 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_AES_SHIFT
, FTR_UNSIGNED
, 1, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_AES
),
1269 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_SHA1_SHIFT
, FTR_UNSIGNED
, 1, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_SHA1
),
1270 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_SHA2_SHIFT
, FTR_UNSIGNED
, 1, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_SHA2
),
1271 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_CRC32_SHIFT
, FTR_UNSIGNED
, 1, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_CRC32
),
1276 static void __init
cap_set_elf_hwcap(const struct arm64_cpu_capabilities
*cap
)
1278 switch (cap
->hwcap_type
) {
1280 elf_hwcap
|= cap
->hwcap
;
1282 #ifdef CONFIG_COMPAT
1283 case CAP_COMPAT_HWCAP
:
1284 compat_elf_hwcap
|= (u32
)cap
->hwcap
;
1286 case CAP_COMPAT_HWCAP2
:
1287 compat_elf_hwcap2
|= (u32
)cap
->hwcap
;
1296 /* Check if we have a particular HWCAP enabled */
1297 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities
*cap
)
1301 switch (cap
->hwcap_type
) {
1303 rc
= (elf_hwcap
& cap
->hwcap
) != 0;
1305 #ifdef CONFIG_COMPAT
1306 case CAP_COMPAT_HWCAP
:
1307 rc
= (compat_elf_hwcap
& (u32
)cap
->hwcap
) != 0;
1309 case CAP_COMPAT_HWCAP2
:
1310 rc
= (compat_elf_hwcap2
& (u32
)cap
->hwcap
) != 0;
1321 static void __init
setup_elf_hwcaps(const struct arm64_cpu_capabilities
*hwcaps
)
1323 /* We support emulation of accesses to CPU ID feature registers */
1324 elf_hwcap
|= HWCAP_CPUID
;
1325 for (; hwcaps
->matches
; hwcaps
++)
1326 if (hwcaps
->matches(hwcaps
, cpucap_default_scope(hwcaps
)))
1327 cap_set_elf_hwcap(hwcaps
);
1331 * Check if the current CPU has a given feature capability.
1332 * Should be called from non-preemptible context.
1334 static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities
*cap_array
,
1337 const struct arm64_cpu_capabilities
*caps
;
1339 if (WARN_ON(preemptible()))
1342 for (caps
= cap_array
; caps
->matches
; caps
++)
1343 if (caps
->capability
== cap
&&
1344 caps
->matches(caps
, SCOPE_LOCAL_CPU
))
1349 static void __update_cpu_capabilities(const struct arm64_cpu_capabilities
*caps
,
1350 u16 scope_mask
, const char *info
)
1352 scope_mask
&= ARM64_CPUCAP_SCOPE_MASK
;
1353 for (; caps
->matches
; caps
++) {
1354 if (!(caps
->type
& scope_mask
) ||
1355 !caps
->matches(caps
, cpucap_default_scope(caps
)))
1358 if (!cpus_have_cap(caps
->capability
) && caps
->desc
)
1359 pr_info("%s %s\n", info
, caps
->desc
);
1360 cpus_set_cap(caps
->capability
);
1364 static void update_cpu_capabilities(u16 scope_mask
)
1366 __update_cpu_capabilities(arm64_errata
, scope_mask
,
1367 "enabling workaround for");
1368 __update_cpu_capabilities(arm64_features
, scope_mask
, "detected:");
1371 static int __enable_cpu_capability(void *arg
)
1373 const struct arm64_cpu_capabilities
*cap
= arg
;
1375 cap
->cpu_enable(cap
);
1380 * Run through the enabled capabilities and enable() it on all active
1384 __enable_cpu_capabilities(const struct arm64_cpu_capabilities
*caps
,
1387 scope_mask
&= ARM64_CPUCAP_SCOPE_MASK
;
1388 for (; caps
->matches
; caps
++) {
1389 unsigned int num
= caps
->capability
;
1391 if (!(caps
->type
& scope_mask
) || !cpus_have_cap(num
))
1394 /* Ensure cpus_have_const_cap(num) works */
1395 static_branch_enable(&cpu_hwcap_keys
[num
]);
1397 if (caps
->cpu_enable
) {
1399 * Capabilities with SCOPE_BOOT_CPU scope are finalised
1400 * before any secondary CPU boots. Thus, each secondary
1401 * will enable the capability as appropriate via
1402 * check_local_cpu_capabilities(). The only exception is
1403 * the boot CPU, for which the capability must be
1404 * enabled here. This approach avoids costly
1405 * stop_machine() calls for this case.
1407 * Otherwise, use stop_machine() as it schedules the
1408 * work allowing us to modify PSTATE, instead of
1409 * on_each_cpu() which uses an IPI, giving us a PSTATE
1410 * that disappears when we return.
1412 if (scope_mask
& SCOPE_BOOT_CPU
)
1413 caps
->cpu_enable(caps
);
1415 stop_machine(__enable_cpu_capability
,
1416 (void *)caps
, cpu_online_mask
);
1421 static void __init
enable_cpu_capabilities(u16 scope_mask
)
1423 __enable_cpu_capabilities(arm64_errata
, scope_mask
);
1424 __enable_cpu_capabilities(arm64_features
, scope_mask
);
1428 * Run through the list of capabilities to check for conflicts.
1429 * If the system has already detected a capability, take necessary
1430 * action on this CPU.
1432 * Returns "false" on conflicts.
1435 __verify_local_cpu_caps(const struct arm64_cpu_capabilities
*caps_list
,
1438 bool cpu_has_cap
, system_has_cap
;
1439 const struct arm64_cpu_capabilities
*caps
;
1441 scope_mask
&= ARM64_CPUCAP_SCOPE_MASK
;
1443 for (caps
= caps_list
; caps
->matches
; caps
++) {
1444 if (!(caps
->type
& scope_mask
))
1447 cpu_has_cap
= __this_cpu_has_cap(caps_list
, caps
->capability
);
1448 system_has_cap
= cpus_have_cap(caps
->capability
);
1450 if (system_has_cap
) {
1452 * Check if the new CPU misses an advertised feature,
1453 * which is not safe to miss.
1455 if (!cpu_has_cap
&& !cpucap_late_cpu_optional(caps
))
1458 * We have to issue cpu_enable() irrespective of
1459 * whether the CPU has it or not, as it is enabeld
1460 * system wide. It is upto the call back to take
1461 * appropriate action on this CPU.
1463 if (caps
->cpu_enable
)
1464 caps
->cpu_enable(caps
);
1467 * Check if the CPU has this capability if it isn't
1468 * safe to have when the system doesn't.
1470 if (cpu_has_cap
&& !cpucap_late_cpu_permitted(caps
))
1475 if (caps
->matches
) {
1476 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1477 smp_processor_id(), caps
->capability
,
1478 caps
->desc
, system_has_cap
, cpu_has_cap
);
1485 static bool verify_local_cpu_caps(u16 scope_mask
)
1487 return __verify_local_cpu_caps(arm64_errata
, scope_mask
) &&
1488 __verify_local_cpu_caps(arm64_features
, scope_mask
);
1492 * Check for CPU features that are used in early boot
1493 * based on the Boot CPU value.
1495 static void check_early_cpu_features(void)
1497 verify_cpu_asid_bits();
1499 * Early features are used by the kernel already. If there
1500 * is a conflict, we cannot proceed further.
1502 if (!verify_local_cpu_caps(SCOPE_BOOT_CPU
))
1507 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities
*caps
)
1510 for (; caps
->matches
; caps
++)
1511 if (cpus_have_elf_hwcap(caps
) && !caps
->matches(caps
, SCOPE_LOCAL_CPU
)) {
1512 pr_crit("CPU%d: missing HWCAP: %s\n",
1513 smp_processor_id(), caps
->desc
);
1518 static void verify_sve_features(void)
1520 u64 safe_zcr
= read_sanitised_ftr_reg(SYS_ZCR_EL1
);
1521 u64 zcr
= read_zcr_features();
1523 unsigned int safe_len
= safe_zcr
& ZCR_ELx_LEN_MASK
;
1524 unsigned int len
= zcr
& ZCR_ELx_LEN_MASK
;
1526 if (len
< safe_len
|| sve_verify_vq_map()) {
1527 pr_crit("CPU%d: SVE: required vector length(s) missing\n",
1528 smp_processor_id());
1532 /* Add checks on other ZCR bits here if necessary */
1537 * Run through the enabled system capabilities and enable() it on this CPU.
1538 * The capabilities were decided based on the available CPUs at the boot time.
1539 * Any new CPU should match the system wide status of the capability. If the
1540 * new CPU doesn't have a capability which the system now has enabled, we
1541 * cannot do anything to fix it up and could cause unexpected failures. So
1544 static void verify_local_cpu_capabilities(void)
1547 * The capabilities with SCOPE_BOOT_CPU are checked from
1548 * check_early_cpu_features(), as they need to be verified
1549 * on all secondary CPUs.
1551 if (!verify_local_cpu_caps(SCOPE_ALL
& ~SCOPE_BOOT_CPU
))
1554 verify_local_elf_hwcaps(arm64_elf_hwcaps
);
1556 if (system_supports_32bit_el0())
1557 verify_local_elf_hwcaps(compat_elf_hwcaps
);
1559 if (system_supports_sve())
1560 verify_sve_features();
1563 void check_local_cpu_capabilities(void)
1566 * All secondary CPUs should conform to the early CPU features
1567 * in use by the kernel based on boot CPU.
1569 check_early_cpu_features();
1572 * If we haven't finalised the system capabilities, this CPU gets
1573 * a chance to update the errata work arounds and local features.
1574 * Otherwise, this CPU should verify that it has all the system
1575 * advertised capabilities.
1577 if (!sys_caps_initialised
)
1578 update_cpu_capabilities(SCOPE_LOCAL_CPU
);
1580 verify_local_cpu_capabilities();
1583 static void __init
setup_boot_cpu_capabilities(void)
1585 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
1586 update_cpu_capabilities(SCOPE_BOOT_CPU
| SCOPE_LOCAL_CPU
);
1587 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
1588 enable_cpu_capabilities(SCOPE_BOOT_CPU
);
1591 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready
);
1592 EXPORT_SYMBOL(arm64_const_caps_ready
);
1594 static void __init
mark_const_caps_ready(void)
1596 static_branch_enable(&arm64_const_caps_ready
);
1599 extern const struct arm64_cpu_capabilities arm64_errata
[];
1601 bool this_cpu_has_cap(unsigned int cap
)
1603 return (__this_cpu_has_cap(arm64_features
, cap
) ||
1604 __this_cpu_has_cap(arm64_errata
, cap
));
1607 static void __init
setup_system_capabilities(void)
1610 * We have finalised the system-wide safe feature
1611 * registers, finalise the capabilities that depend
1612 * on it. Also enable all the available capabilities,
1613 * that are not enabled already.
1615 update_cpu_capabilities(SCOPE_SYSTEM
);
1616 enable_cpu_capabilities(SCOPE_ALL
& ~SCOPE_BOOT_CPU
);
1619 void __init
setup_cpu_features(void)
1624 setup_system_capabilities();
1625 mark_const_caps_ready();
1626 setup_elf_hwcaps(arm64_elf_hwcaps
);
1628 if (system_supports_32bit_el0())
1629 setup_elf_hwcaps(compat_elf_hwcaps
);
1633 /* Advertise that we have computed the system capabilities */
1634 set_sys_caps_initialised();
1637 * Check for sane CTR_EL0.CWG value.
1639 cwg
= cache_type_cwg();
1640 cls
= cache_line_size();
1642 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1644 if (L1_CACHE_BYTES
< cls
)
1645 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1646 L1_CACHE_BYTES
, cls
);
1649 static bool __maybe_unused
1650 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities
*entry
, int __unused
)
1652 return (cpus_have_const_cap(ARM64_HAS_PAN
) && !cpus_have_const_cap(ARM64_HAS_UAO
));
1656 * We emulate only the following system register space.
1657 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1658 * See Table C5-6 System instruction encodings for System register accesses,
1659 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1661 static inline bool __attribute_const__
is_emulated(u32 id
)
1663 return (sys_reg_Op0(id
) == 0x3 &&
1664 sys_reg_CRn(id
) == 0x0 &&
1665 sys_reg_Op1(id
) == 0x0 &&
1666 (sys_reg_CRm(id
) == 0 ||
1667 ((sys_reg_CRm(id
) >= 4) && (sys_reg_CRm(id
) <= 7))));
1671 * With CRm == 0, reg should be one of :
1672 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1674 static inline int emulate_id_reg(u32 id
, u64
*valp
)
1678 *valp
= read_cpuid_id();
1681 *valp
= SYS_MPIDR_SAFE_VAL
;
1683 case SYS_REVIDR_EL1
:
1684 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1694 static int emulate_sys_reg(u32 id
, u64
*valp
)
1696 struct arm64_ftr_reg
*regp
;
1698 if (!is_emulated(id
))
1701 if (sys_reg_CRm(id
) == 0)
1702 return emulate_id_reg(id
, valp
);
1704 regp
= get_arm64_ftr_reg(id
);
1706 *valp
= arm64_ftr_reg_user_value(regp
);
1709 * The untracked registers are either IMPLEMENTATION DEFINED
1710 * (e.g, ID_AFR0_EL1) or reserved RAZ.
1716 static int emulate_mrs(struct pt_regs
*regs
, u32 insn
)
1723 * sys_reg values are defined as used in mrs/msr instruction.
1724 * shift the imm value to get the encoding.
1726 sys_reg
= (u32
)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16
, insn
) << 5;
1727 rc
= emulate_sys_reg(sys_reg
, &val
);
1729 dst
= aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT
, insn
);
1730 pt_regs_write_reg(regs
, dst
, val
);
1731 arm64_skip_faulting_instruction(regs
, AARCH64_INSN_SIZE
);
1737 static struct undef_hook mrs_hook
= {
1738 .instr_mask
= 0xfff00000,
1739 .instr_val
= 0xd5300000,
1740 .pstate_mask
= COMPAT_PSR_MODE_MASK
,
1741 .pstate_val
= PSR_MODE_EL0t
,
1745 static int __init
enable_mrs_emulation(void)
1747 register_undef_hook(&mrs_hook
);
1751 core_initcall(enable_mrs_emulation
);
1753 void cpu_clear_disr(const struct arm64_cpu_capabilities
*__unused
)
1755 /* Firmware may have left a deferred SError in this register. */
1756 write_sysreg_s(0, SYS_DISR_EL1
);
1759 ssize_t
cpu_show_meltdown(struct device
*dev
, struct device_attribute
*attr
,
1762 if (__meltdown_safe
)
1763 return sprintf(buf
, "Not affected\n");
1765 if (arm64_kernel_unmapped_at_el0())
1766 return sprintf(buf
, "Mitigation: PTI\n");
1768 return sprintf(buf
, "Vulnerable\n");