2 * Record and handle CPU attributes.
4 * Copyright (C) 2014 ARM Ltd.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <asm/arch_timer.h>
18 #include <asm/cachetype.h>
20 #include <asm/cputype.h>
21 #include <asm/cpufeature.h>
23 #include <linux/bitops.h>
24 #include <linux/bug.h>
25 #include <linux/init.h>
26 #include <linux/kernel.h>
27 #include <linux/preempt.h>
28 #include <linux/printk.h>
29 #include <linux/smp.h>
32 * In case the boot CPU is hotpluggable, we record its initial state and
33 * current state separately. Certain system registers may contain different
34 * values depending on configuration at or after reset.
36 DEFINE_PER_CPU(struct cpuinfo_arm64
, cpu_data
);
37 static struct cpuinfo_arm64 boot_cpu_data
;
39 static char *icache_policy_str
[] = {
40 [ICACHE_POLICY_RESERVED
] = "RESERVED/UNKNOWN",
41 [ICACHE_POLICY_AIVIVT
] = "AIVIVT",
42 [ICACHE_POLICY_VIPT
] = "VIPT",
43 [ICACHE_POLICY_PIPT
] = "PIPT",
46 unsigned long __icache_flags
;
48 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64
*info
)
50 unsigned int cpu
= smp_processor_id();
51 u32 l1ip
= CTR_L1IP(info
->reg_ctr
);
53 if (l1ip
!= ICACHE_POLICY_PIPT
) {
55 * VIPT caches are non-aliasing if the VA always equals the PA
56 * in all bit positions that are covered by the index. This is
57 * the case if the size of a way (# of sets * line size) does
58 * not exceed PAGE_SIZE.
60 u32 waysize
= icache_get_numsets() * icache_get_linesize();
62 if (l1ip
!= ICACHE_POLICY_VIPT
|| waysize
> PAGE_SIZE
)
63 set_bit(ICACHEF_ALIASING
, &__icache_flags
);
65 if (l1ip
== ICACHE_POLICY_AIVIVT
)
66 set_bit(ICACHEF_AIVIVT
, &__icache_flags
);
68 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str
[l1ip
], cpu
);
71 static int check_reg_mask(char *name
, u64 mask
, u64 boot
, u64 cur
, int cpu
)
73 if ((boot
& mask
) == (cur
& mask
))
76 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016lx, CPU%d: %#016lx\n",
77 name
, (unsigned long)boot
, cpu
, (unsigned long)cur
);
82 #define CHECK_MASK(field, mask, boot, cur, cpu) \
83 check_reg_mask(#field, mask, (boot)->reg_ ## field, (cur)->reg_ ## field, cpu)
85 #define CHECK(field, boot, cur, cpu) \
86 CHECK_MASK(field, ~0ULL, boot, cur, cpu)
89 * Verify that CPUs don't have unexpected differences that will cause problems.
91 static void cpuinfo_sanity_check(struct cpuinfo_arm64
*cur
)
93 unsigned int cpu
= smp_processor_id();
94 struct cpuinfo_arm64
*boot
= &boot_cpu_data
;
95 unsigned int diff
= 0;
98 * The kernel can handle differing I-cache policies, but otherwise
99 * caches should look identical. Userspace JITs will make use of
102 diff
|= CHECK_MASK(ctr
, 0xffff3fff, boot
, cur
, cpu
);
105 * Userspace may perform DC ZVA instructions. Mismatched block sizes
106 * could result in too much or too little memory being zeroed if a
107 * process is preempted and migrated between CPUs.
109 diff
|= CHECK(dczid
, boot
, cur
, cpu
);
111 /* If different, timekeeping will be broken (especially with KVM) */
112 diff
|= CHECK(cntfrq
, boot
, cur
, cpu
);
115 * The kernel uses self-hosted debug features and expects CPUs to
116 * support identical debug features. We presently need CTX_CMPs, WRPs,
117 * and BRPs to be identical.
118 * ID_AA64DFR1 is currently RES0.
120 diff
|= CHECK(id_aa64dfr0
, boot
, cur
, cpu
);
121 diff
|= CHECK(id_aa64dfr1
, boot
, cur
, cpu
);
124 * Even in big.LITTLE, processors should be identical instruction-set
127 diff
|= CHECK(id_aa64isar0
, boot
, cur
, cpu
);
128 diff
|= CHECK(id_aa64isar1
, boot
, cur
, cpu
);
131 * Differing PARange support is fine as long as all peripherals and
132 * memory are mapped within the minimum PARange of all CPUs.
133 * Linux should not care about secure memory.
134 * ID_AA64MMFR1 is currently RES0.
136 diff
|= CHECK_MASK(id_aa64mmfr0
, 0xffffffffffff0ff0, boot
, cur
, cpu
);
137 diff
|= CHECK(id_aa64mmfr1
, boot
, cur
, cpu
);
140 * EL3 is not our concern.
141 * ID_AA64PFR1 is currently RES0.
143 diff
|= CHECK_MASK(id_aa64pfr0
, 0xffffffffffff0fff, boot
, cur
, cpu
);
144 diff
|= CHECK(id_aa64pfr1
, boot
, cur
, cpu
);
147 * If we have AArch32, we care about 32-bit features for compat. These
148 * registers should be RES0 otherwise.
150 diff
|= CHECK(id_isar0
, boot
, cur
, cpu
);
151 diff
|= CHECK(id_isar1
, boot
, cur
, cpu
);
152 diff
|= CHECK(id_isar2
, boot
, cur
, cpu
);
153 diff
|= CHECK(id_isar3
, boot
, cur
, cpu
);
154 diff
|= CHECK(id_isar4
, boot
, cur
, cpu
);
155 diff
|= CHECK(id_isar5
, boot
, cur
, cpu
);
157 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
158 * ACTLR formats could differ across CPUs and therefore would have to
159 * be trapped for virtualization anyway.
161 diff
|= CHECK_MASK(id_mmfr0
, 0xff0fffff, boot
, cur
, cpu
);
162 diff
|= CHECK(id_mmfr1
, boot
, cur
, cpu
);
163 diff
|= CHECK(id_mmfr2
, boot
, cur
, cpu
);
164 diff
|= CHECK(id_mmfr3
, boot
, cur
, cpu
);
165 diff
|= CHECK(id_pfr0
, boot
, cur
, cpu
);
166 diff
|= CHECK(id_pfr1
, boot
, cur
, cpu
);
169 * Mismatched CPU features are a recipe for disaster. Don't even
170 * pretend to support them.
172 WARN_TAINT_ONCE(diff
, TAINT_CPU_OUT_OF_SPEC
,
173 "Unsupported CPU feature variation.\n");
176 static void __cpuinfo_store_cpu(struct cpuinfo_arm64
*info
)
178 info
->reg_cntfrq
= arch_timer_get_cntfrq();
179 info
->reg_ctr
= read_cpuid_cachetype();
180 info
->reg_dczid
= read_cpuid(DCZID_EL0
);
181 info
->reg_midr
= read_cpuid_id();
183 info
->reg_id_aa64dfr0
= read_cpuid(ID_AA64DFR0_EL1
);
184 info
->reg_id_aa64dfr1
= read_cpuid(ID_AA64DFR1_EL1
);
185 info
->reg_id_aa64isar0
= read_cpuid(ID_AA64ISAR0_EL1
);
186 info
->reg_id_aa64isar1
= read_cpuid(ID_AA64ISAR1_EL1
);
187 info
->reg_id_aa64mmfr0
= read_cpuid(ID_AA64MMFR0_EL1
);
188 info
->reg_id_aa64mmfr1
= read_cpuid(ID_AA64MMFR1_EL1
);
189 info
->reg_id_aa64pfr0
= read_cpuid(ID_AA64PFR0_EL1
);
190 info
->reg_id_aa64pfr1
= read_cpuid(ID_AA64PFR1_EL1
);
192 info
->reg_id_isar0
= read_cpuid(ID_ISAR0_EL1
);
193 info
->reg_id_isar1
= read_cpuid(ID_ISAR1_EL1
);
194 info
->reg_id_isar2
= read_cpuid(ID_ISAR2_EL1
);
195 info
->reg_id_isar3
= read_cpuid(ID_ISAR3_EL1
);
196 info
->reg_id_isar4
= read_cpuid(ID_ISAR4_EL1
);
197 info
->reg_id_isar5
= read_cpuid(ID_ISAR5_EL1
);
198 info
->reg_id_mmfr0
= read_cpuid(ID_MMFR0_EL1
);
199 info
->reg_id_mmfr1
= read_cpuid(ID_MMFR1_EL1
);
200 info
->reg_id_mmfr2
= read_cpuid(ID_MMFR2_EL1
);
201 info
->reg_id_mmfr3
= read_cpuid(ID_MMFR3_EL1
);
202 info
->reg_id_pfr0
= read_cpuid(ID_PFR0_EL1
);
203 info
->reg_id_pfr1
= read_cpuid(ID_PFR1_EL1
);
205 cpuinfo_detect_icache_policy(info
);
207 check_local_cpu_errata();
210 void cpuinfo_store_cpu(void)
212 struct cpuinfo_arm64
*info
= this_cpu_ptr(&cpu_data
);
213 __cpuinfo_store_cpu(info
);
214 cpuinfo_sanity_check(info
);
217 void __init
cpuinfo_store_boot_cpu(void)
219 struct cpuinfo_arm64
*info
= &per_cpu(cpu_data
, 0);
220 __cpuinfo_store_cpu(info
);
222 boot_cpu_data
= *info
;
225 u64 __attribute_const__
icache_get_ccsidr(void)
229 WARN_ON(preemptible());
231 /* Select L1 I-cache and read its size ID register */
232 asm("msr csselr_el1, %1; isb; mrs %0, ccsidr_el1"
233 : "=r"(ccsidr
) : "r"(1L));