2 * Low-level exception handling code
4 * Copyright (C) 2012 ARM Ltd.
5 * Authors: Catalin Marinas <catalin.marinas@arm.com>
6 * Will Deacon <will.deacon@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/init.h>
22 #include <linux/linkage.h>
24 #include <asm/alternative.h>
25 #include <asm/assembler.h>
26 #include <asm/asm-offsets.h>
27 #include <asm/cpufeature.h>
28 #include <asm/errno.h>
31 #include <asm/memory.h>
33 #include <asm/processor.h>
34 #include <asm/ptrace.h>
35 #include <asm/thread_info.h>
36 #include <asm/asm-uaccess.h>
37 #include <asm/unistd.h>
40 * Context tracking subsystem. Used to instrument transitions
41 * between user and kernel mode.
43 .macro ct_user_exit, syscall = 0
44 #ifdef CONFIG_CONTEXT_TRACKING
45 bl context_tracking_user_exit
48 * Save/restore needed during syscalls. Restore syscall arguments from
49 * the values already saved on stack during kernel_entry.
52 ldp x2, x3, [sp, #S_X2]
53 ldp x4, x5, [sp, #S_X4]
54 ldp x6, x7, [sp, #S_X6]
60 #ifdef CONFIG_CONTEXT_TRACKING
61 bl context_tracking_user_enter
74 .macro kernel_ventry, el, label, regsize = 64
76 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
77 alternative_if ARM64_UNMAP_KERNEL_AT_EL0
86 alternative_else_nop_endif
89 sub sp, sp, #S_FRAME_SIZE
90 #ifdef CONFIG_VMAP_STACK
92 * Test whether the SP has overflowed, without corrupting a GPR.
93 * Task and IRQ stacks are aligned to (1 << THREAD_SHIFT).
95 add sp, sp, x0 // sp' = sp + x0
96 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
97 tbnz x0, #THREAD_SHIFT, 0f
98 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
99 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
104 * Either we've just detected an overflow, or we've taken an exception
105 * while on the overflow stack. Either way, we won't return to
106 * userspace, and can clobber EL0 registers to free up GPRs.
109 /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */
112 /* Recover the original x0 value and stash it in tpidrro_el0 */
116 /* Switch to the overflow stack */
117 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0
120 * Check whether we were already on the overflow stack. This may happen
121 * after panic() re-enables interrupts.
123 mrs x0, tpidr_el0 // sp of interrupted context
124 sub x0, sp, x0 // delta with top of overflow stack
125 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
126 b.ne __bad_stack // no? -> bad stack pointer
128 /* We were already on the overflow stack. Restore sp/x0 and carry on. */
135 .macro tramp_alias, dst, sym
136 mov_q \dst, TRAMP_VALIAS
137 add \dst, \dst, #(\sym - .entry.tramp.text)
140 .macro kernel_entry, el, regsize = 64
142 mov w0, w0 // zero upper 32 bits of x0
144 stp x0, x1, [sp, #16 * 0]
145 stp x2, x3, [sp, #16 * 1]
146 stp x4, x5, [sp, #16 * 2]
147 stp x6, x7, [sp, #16 * 3]
148 stp x8, x9, [sp, #16 * 4]
149 stp x10, x11, [sp, #16 * 5]
150 stp x12, x13, [sp, #16 * 6]
151 stp x14, x15, [sp, #16 * 7]
152 stp x16, x17, [sp, #16 * 8]
153 stp x18, x19, [sp, #16 * 9]
154 stp x20, x21, [sp, #16 * 10]
155 stp x22, x23, [sp, #16 * 11]
156 stp x24, x25, [sp, #16 * 12]
157 stp x26, x27, [sp, #16 * 13]
158 stp x28, x29, [sp, #16 * 14]
162 ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear,
163 ldr x19, [tsk, #TSK_TI_FLAGS] // since we can unmask debug
164 disable_step_tsk x19, x20 // exceptions when scheduling.
166 mov x29, xzr // fp pointed to user-space
168 add x21, sp, #S_FRAME_SIZE
170 /* Save the task's original addr_limit and set USER_DS */
171 ldr x20, [tsk, #TSK_TI_ADDR_LIMIT]
172 str x20, [sp, #S_ORIG_ADDR_LIMIT]
174 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
175 /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */
176 .endif /* \el == 0 */
179 stp lr, x21, [sp, #S_LR]
182 * In order to be able to dump the contents of struct pt_regs at the
183 * time the exception was taken (in case we attempt to walk the call
184 * stack later), chain it together with the stack frames.
187 stp xzr, xzr, [sp, #S_STACKFRAME]
189 stp x29, x22, [sp, #S_STACKFRAME]
191 add x29, sp, #S_STACKFRAME
193 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
195 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
196 * EL0, there is no need to check the state of TTBR0_EL1 since
197 * accesses are always enabled.
198 * Note that the meaning of this bit differs from the ARMv8.1 PAN
199 * feature as all TTBR0_EL1 accesses are disabled, not just those to
202 alternative_if ARM64_HAS_PAN
203 b 1f // skip TTBR0 PAN
204 alternative_else_nop_endif
208 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID
209 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
210 b.eq 1f // TTBR0 access already disabled
211 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
214 __uaccess_ttbr0_disable x21
218 stp x22, x23, [sp, #S_PC]
220 /* Not in a syscall by default (el0_svc overwrites for real syscall) */
223 str w21, [sp, #S_SYSCALLNO]
227 * Set sp_el0 to current thread_info.
234 * Registers that may be useful after this macro is invoked:
238 * x23 - aborted PSTATE
242 .macro kernel_exit, el
246 /* Restore the task's original addr_limit. */
247 ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
248 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
250 /* No need to restore UAO, it will be restored from SPSR_EL1 */
253 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
258 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
260 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
263 alternative_if ARM64_HAS_PAN
264 b 2f // skip TTBR0 PAN
265 alternative_else_nop_endif
268 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
271 __uaccess_ttbr0_enable x0, x1
275 * Enable errata workarounds only if returning to user. The only
276 * workaround currently required for TTBR0_EL1 changes are for the
277 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
280 bl post_ttbr_update_workaround
284 and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
290 ldr x23, [sp, #S_SP] // load return stack pointer
292 tst x22, #PSR_MODE32_BIT // native task?
295 #ifdef CONFIG_ARM64_ERRATUM_845719
296 alternative_if ARM64_WORKAROUND_845719
297 #ifdef CONFIG_PID_IN_CONTEXTIDR
298 mrs x29, contextidr_el1
299 msr contextidr_el1, x29
301 msr contextidr_el1, xzr
303 alternative_else_nop_endif
308 msr elr_el1, x21 // set up the return data
310 ldp x0, x1, [sp, #16 * 0]
311 ldp x2, x3, [sp, #16 * 1]
312 ldp x4, x5, [sp, #16 * 2]
313 ldp x6, x7, [sp, #16 * 3]
314 ldp x8, x9, [sp, #16 * 4]
315 ldp x10, x11, [sp, #16 * 5]
316 ldp x12, x13, [sp, #16 * 6]
317 ldp x14, x15, [sp, #16 * 7]
318 ldp x16, x17, [sp, #16 * 8]
319 ldp x18, x19, [sp, #16 * 9]
320 ldp x20, x21, [sp, #16 * 10]
321 ldp x22, x23, [sp, #16 * 11]
322 ldp x24, x25, [sp, #16 * 12]
323 ldp x26, x27, [sp, #16 * 13]
324 ldp x28, x29, [sp, #16 * 14]
326 add sp, sp, #S_FRAME_SIZE // restore sp
329 alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
330 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
333 tramp_alias x30, tramp_exit_native
336 tramp_alias x30, tramp_exit_compat
344 .macro irq_stack_entry
345 mov x19, sp // preserve the original sp
348 * Compare sp with the base of the task stack.
349 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
350 * and should switch to the irq stack.
352 ldr x25, [tsk, TSK_STACK]
354 and x25, x25, #~(THREAD_SIZE - 1)
357 ldr_this_cpu x25, irq_stack_ptr, x26
358 mov x26, #IRQ_STACK_SIZE
361 /* switch to the irq stack */
367 * x19 should be preserved between irq_stack_entry and
370 .macro irq_stack_exit
375 * These are the registers used in the syscall handler, and allow us to
376 * have in theory up to 7 arguments to a function - x0 to x6.
378 * x7 is reserved for the system call number in 32-bit mode.
380 wsc_nr .req w25 // number of system calls
381 xsc_nr .req x25 // number of system calls (zero-extended)
382 wscno .req w26 // syscall number
383 xscno .req x26 // syscall number (zero-extended)
384 stbl .req x27 // syscall table pointer
385 tsk .req x28 // current thread_info
388 * Interrupt handling.
391 ldr_l x1, handle_arch_irq
403 .pushsection ".entry.text", "ax"
407 kernel_ventry 1, sync_invalid // Synchronous EL1t
408 kernel_ventry 1, irq_invalid // IRQ EL1t
409 kernel_ventry 1, fiq_invalid // FIQ EL1t
410 kernel_ventry 1, error_invalid // Error EL1t
412 kernel_ventry 1, sync // Synchronous EL1h
413 kernel_ventry 1, irq // IRQ EL1h
414 kernel_ventry 1, fiq_invalid // FIQ EL1h
415 kernel_ventry 1, error // Error EL1h
417 kernel_ventry 0, sync // Synchronous 64-bit EL0
418 kernel_ventry 0, irq // IRQ 64-bit EL0
419 kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0
420 kernel_ventry 0, error // Error 64-bit EL0
423 kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0
424 kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0
425 kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0
426 kernel_ventry 0, error_compat, 32 // Error 32-bit EL0
428 kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0
429 kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0
430 kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0
431 kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0
435 #ifdef CONFIG_VMAP_STACK
437 * We detected an overflow in kernel_ventry, which switched to the
438 * overflow stack. Stash the exception regs, and head to our overflow
442 /* Restore the original x0 value */
446 * Store the original GPRs to the new stack. The orginal SP (minus
447 * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry.
449 sub sp, sp, #S_FRAME_SIZE
452 add x0, x0, #S_FRAME_SIZE
455 /* Stash the regs for handle_bad_stack */
461 #endif /* CONFIG_VMAP_STACK */
464 * Invalid mode handlers
466 .macro inv_entry, el, reason, regsize = 64
467 kernel_entry \el, \regsize
476 inv_entry 0, BAD_SYNC
477 ENDPROC(el0_sync_invalid)
481 ENDPROC(el0_irq_invalid)
485 ENDPROC(el0_fiq_invalid)
488 inv_entry 0, BAD_ERROR
489 ENDPROC(el0_error_invalid)
492 el0_fiq_invalid_compat:
493 inv_entry 0, BAD_FIQ, 32
494 ENDPROC(el0_fiq_invalid_compat)
498 inv_entry 1, BAD_SYNC
499 ENDPROC(el1_sync_invalid)
503 ENDPROC(el1_irq_invalid)
507 ENDPROC(el1_fiq_invalid)
510 inv_entry 1, BAD_ERROR
511 ENDPROC(el1_error_invalid)
519 mrs x1, esr_el1 // read the syndrome register
520 lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
521 cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
523 cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1
525 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
527 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
529 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
531 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1
533 cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1
539 * Fall through to the Data abort case
543 * Data abort handling
546 inherit_daif pstate=x23, tmp=x2
547 clear_address_tag x0, x3
548 mov x2, sp // struct pt_regs
554 * Stack or PC alignment exception handling
557 inherit_daif pstate=x23, tmp=x2
563 * Undefined instruction
565 inherit_daif pstate=x23, tmp=x2
571 * Debug exception handling
573 cmp x24, #ESR_ELx_EC_BRK64 // if BRK64
574 cinc x24, x24, eq // set bit '0'
575 tbz x24, #0, el1_inv // EL1 only
577 mov x2, sp // struct pt_regs
578 bl do_debug_exception
581 // TODO: add support for undefined instructions in kernel mode
582 inherit_daif pstate=x23, tmp=x2
594 #ifdef CONFIG_TRACE_IRQFLAGS
595 bl trace_hardirqs_off
600 #ifdef CONFIG_PREEMPT
601 ldr w24, [tsk, #TSK_TI_PREEMPT] // get preempt count
602 cbnz w24, 1f // preempt count != 0
603 ldr x0, [tsk, #TSK_TI_FLAGS] // get flags
604 tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
608 #ifdef CONFIG_TRACE_IRQFLAGS
614 #ifdef CONFIG_PREEMPT
617 1: bl preempt_schedule_irq // irq en/disable is done inside
618 ldr x0, [tsk, #TSK_TI_FLAGS] // get new tasks TI_FLAGS
619 tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
629 mrs x25, esr_el1 // read the syndrome register
630 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
631 cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state
633 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
635 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
637 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
639 cmp x24, #ESR_ELx_EC_SVE // SVE access
641 cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception
643 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
645 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
647 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
649 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
651 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
659 mrs x25, esr_el1 // read the syndrome register
660 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
661 cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state
663 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
665 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
667 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
669 cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception
671 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
673 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
675 cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap
677 cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap
679 cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap
681 cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap
683 cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap
685 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
690 * AArch32 syscall handling
692 ldr x16, [tsk, #TSK_TI_FLAGS] // load thread flags
693 adrp stbl, compat_sys_call_table // load compat syscall table pointer
694 mov wscno, w7 // syscall number in w7 (r7)
695 mov wsc_nr, #__NR_compat_syscalls
710 * Data abort handling
715 clear_address_tag x0, x26
722 * Instruction abort handling
726 #ifdef CONFIG_TRACE_IRQFLAGS
727 bl trace_hardirqs_off
733 bl do_el0_ia_bp_hardening
737 * Floating Point or Advanced SIMD access
747 * Scalable Vector Extension access
757 * Floating Point, Advanced SIMD or SVE exception
767 * Stack or PC alignment exception handling
771 #ifdef CONFIG_TRACE_IRQFLAGS
772 bl trace_hardirqs_off
782 * Undefined instruction
791 * System instructions, for trapped cache maintenance instructions
801 * Debug exception handling
803 tbnz x24, #0, el0_inv // EL0 only
807 bl do_debug_exception
826 #ifdef CONFIG_TRACE_IRQFLAGS
827 bl trace_hardirqs_off
831 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
833 bl do_el0_irq_bp_hardening
838 #ifdef CONFIG_TRACE_IRQFLAGS
867 * This is the fast syscall return path. We do as little as possible here,
868 * and this includes saving x0 back into the kernel stack.
872 str x0, [sp, #S_X0] // returned x0
873 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for syscall tracing
874 and x2, x1, #_TIF_SYSCALL_WORK
875 cbnz x2, ret_fast_syscall_trace
876 and x2, x1, #_TIF_WORK_MASK
877 cbnz x2, work_pending
878 enable_step_tsk x1, x2
880 ret_fast_syscall_trace:
882 b __sys_trace_return_skipped // we already saved x0
885 * Ok, we need to do extra processing, enter the slow path.
890 #ifdef CONFIG_TRACE_IRQFLAGS
891 bl trace_hardirqs_on // enabled while in userspace
893 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step
896 * "slow" syscall return path.
900 ldr x1, [tsk, #TSK_TI_FLAGS]
901 and x2, x1, #_TIF_WORK_MASK
902 cbnz x2, work_pending
904 enable_step_tsk x1, x2
913 ldr x16, [tsk, #TSK_TI_FLAGS] // load thread flags
914 adrp stbl, sys_call_table // load syscall table pointer
915 mov wscno, w8 // syscall number in w8
916 mov wsc_nr, #__NR_syscalls
918 #ifdef CONFIG_ARM64_SVE
919 alternative_if_not ARM64_SVE
921 alternative_else_nop_endif
922 tbz x16, #TIF_SVE, el0_svc_naked // Skip unless TIF_SVE set:
923 bic x16, x16, #_TIF_SVE // discard SVE state
924 str x16, [tsk, #TSK_TI_FLAGS]
927 * task_fpsimd_load() won't be called to update CPACR_EL1 in
928 * ret_to_user unless TIF_FOREIGN_FPSTATE is still set, which only
929 * happens if a context switch or kernel_neon_begin() or context
930 * modification (sigreturn, ptrace) intervenes.
931 * So, ensure that CPACR_EL1 is already correct for the fast-path case:
934 bic x9, x9, #CPACR_EL1_ZEN_EL0EN // disable SVE for el0
935 msr cpacr_el1, x9 // synchronised by eret to el0
938 el0_svc_naked: // compat entry point
939 stp x0, xscno, [sp, #S_ORIG_X0] // save the original x0 and syscall number
943 tst x16, #_TIF_SYSCALL_WORK // check for syscall hooks
945 cmp wscno, wsc_nr // check upper syscall limit
947 mask_nospec64 xscno, xsc_nr, x19 // enforce bounds for syscall number
948 ldr x16, [stbl, xscno, lsl #3] // address in the syscall table
949 blr x16 // call sys_* routine
958 * This is the really slow path. We're going to be doing context
959 * switches, and waiting for our parent to respond.
962 cmp wscno, #NO_SYSCALL // user-issued syscall(-1)?
964 mov x0, #-ENOSYS // set default errno if so
967 bl syscall_trace_enter
968 cmp w0, #NO_SYSCALL // skip the syscall?
969 b.eq __sys_trace_return_skipped
970 mov wscno, w0 // syscall number (possibly new)
971 mov x1, sp // pointer to regs
972 cmp wscno, wsc_nr // check upper syscall limit
974 ldp x0, x1, [sp] // restore the syscall args
975 ldp x2, x3, [sp, #S_X2]
976 ldp x4, x5, [sp, #S_X4]
977 ldp x6, x7, [sp, #S_X6]
978 ldr x16, [stbl, xscno, lsl #3] // address in the syscall table
979 blr x16 // call sys_* routine
982 str x0, [sp, #S_X0] // save returned x0
983 __sys_trace_return_skipped:
985 bl syscall_trace_exit
993 .popsection // .entry.text
995 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
997 * Exception vectors trampoline.
999 .pushsection ".entry.tramp.text", "ax"
1001 .macro tramp_map_kernel, tmp
1003 sub \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
1004 bic \tmp, \tmp, #USER_ASID_FLAG
1006 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
1007 alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
1008 /* ASID already in \tmp[63:48] */
1009 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12)
1010 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12)
1011 /* 2MB boundary containing the vectors, so we nobble the walk cache */
1012 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
1016 alternative_else_nop_endif
1017 #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */
1020 .macro tramp_unmap_kernel, tmp
1022 add \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
1023 orr \tmp, \tmp, #USER_ASID_FLAG
1026 * We avoid running the post_ttbr_update_workaround here because
1027 * it's only needed by Cavium ThunderX, which requires KPTI to be
1032 .macro tramp_ventry, regsize = 64
1036 msr tpidrro_el0, x30 // Restored in kernel_ventry
1039 * Defend against branch aliasing attacks by pushing a dummy
1040 * entry onto the return stack and using a RET instruction to
1041 * enter the full-fat kernel vectors.
1046 tramp_map_kernel x30
1047 #ifdef CONFIG_RANDOMIZE_BASE
1048 adr x30, tramp_vectors + PAGE_SIZE
1049 alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
1054 prfm plil1strm, [x30, #(1b - tramp_vectors)]
1056 add x30, x30, #(1b - tramp_vectors)
1061 .macro tramp_exit, regsize = 64
1062 adr x30, tramp_vectors
1064 tramp_unmap_kernel x30
1072 ENTRY(tramp_vectors)
1086 ENTRY(tramp_exit_native)
1088 END(tramp_exit_native)
1090 ENTRY(tramp_exit_compat)
1092 END(tramp_exit_compat)
1095 .popsection // .entry.tramp.text
1096 #ifdef CONFIG_RANDOMIZE_BASE
1097 .pushsection ".rodata", "a"
1099 .globl __entry_tramp_data_start
1100 __entry_tramp_data_start:
1102 .popsection // .rodata
1103 #endif /* CONFIG_RANDOMIZE_BASE */
1104 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1107 * Special system call wrappers.
1109 ENTRY(sys_rt_sigreturn_wrapper)
1112 ENDPROC(sys_rt_sigreturn_wrapper)
1115 * Register switch for AArch64. The callee-saved registers need to be saved
1116 * and restored. On entry:
1117 * x0 = previous task_struct (must be preserved across the switch)
1118 * x1 = next task_struct
1119 * Previous and next are guaranteed not to be the same.
1122 ENTRY(cpu_switch_to)
1123 mov x10, #THREAD_CPU_CONTEXT
1126 stp x19, x20, [x8], #16 // store callee-saved registers
1127 stp x21, x22, [x8], #16
1128 stp x23, x24, [x8], #16
1129 stp x25, x26, [x8], #16
1130 stp x27, x28, [x8], #16
1131 stp x29, x9, [x8], #16
1134 ldp x19, x20, [x8], #16 // restore callee-saved registers
1135 ldp x21, x22, [x8], #16
1136 ldp x23, x24, [x8], #16
1137 ldp x25, x26, [x8], #16
1138 ldp x27, x28, [x8], #16
1139 ldp x29, x9, [x8], #16
1144 ENDPROC(cpu_switch_to)
1145 NOKPROBE(cpu_switch_to)
1148 * This is how we return from a fork.
1150 ENTRY(ret_from_fork)
1152 cbz x19, 1f // not a kernel thread
1155 1: get_thread_info tsk
1157 ENDPROC(ret_from_fork)
1158 NOKPROBE(ret_from_fork)
1160 #ifdef CONFIG_ARM_SDE_INTERFACE
1162 #include <asm/sdei.h>
1163 #include <uapi/linux/arm_sdei.h>
1166 * Software Delegated Exception entry point.
1169 * x1: struct sdei_registered_event argument from registration time.
1170 * x2: interrupted PC
1171 * x3: interrupted PSTATE
1173 * Firmware has preserved x0->x17 for us, we must save/restore the rest to
1174 * follow SMC-CC. We save (or retrieve) all the registers as the handler may
1177 ENTRY(__sdei_asm_handler)
1178 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC]
1179 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2]
1180 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3]
1181 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4]
1182 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5]
1183 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6]
1184 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7]
1185 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8]
1186 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9]
1187 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]
1188 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11]
1189 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12]
1190 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13]
1191 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
1193 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR]
1197 #ifdef CONFIG_VMAP_STACK
1199 * entry.S may have been using sp as a scratch register, find whether
1200 * this is a normal or critical event and switch to the appropriate
1201 * stack for this CPU.
1203 ldrb w4, [x19, #SDEI_EVENT_PRIORITY]
1205 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6
1207 1: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6
1208 2: mov x6, #SDEI_STACK_SIZE
1214 * We may have interrupted userspace, or a guest, or exit-from or
1215 * return-to either of these. We can't trust sp_el0, restore it.
1218 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1
1221 /* If we interrupted the kernel point to the previous stack/frame. */
1225 csel x29, x29, xzr, eq // fp, or zero
1226 csel x4, x2, xzr, eq // elr, or zero
1228 stp x29, x4, [sp, #-16]!
1231 add x0, x19, #SDEI_EVENT_INTREGS
1236 /* restore regs >x17 that we clobbered */
1237 ldp x28, x29, [x19, #SDEI_EVENT_INTREGS + 16 * 14]
1238 ldp lr, x4, [x19, #SDEI_EVENT_INTREGS + S_LR]
1240 ldp x18, x19, [x19, #SDEI_EVENT_INTREGS + 16 * 9]
1242 mov x1, x0 // address to complete_and_resume
1243 /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */
1245 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE
1246 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME
1249 /* On success, this call never returns... */
1250 ldr_l x2, sdei_exit_mode
1251 cmp x2, #SDEI_EXIT_SMC
1257 ENDPROC(__sdei_asm_handler)
1258 NOKPROBE(__sdei_asm_handler)
1259 #endif /* CONFIG_ARM_SDE_INTERFACE */