arch/arm64/kernel/entry.S

   1 /*
   2  * Low-level exception handling code
   3  *
   4  * Copyright (C) 2012 ARM Ltd.
   5  * Authors:     Catalin Marinas <catalin.marinas@arm.com>
   6  *              Will Deacon <will.deacon@arm.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <linux/init.h>
  22 #include <linux/linkage.h>
  23
  24 #include <asm/alternative.h>
  25 #include <asm/assembler.h>
  26 #include <asm/asm-offsets.h>
  27 #include <asm/cpufeature.h>
  28 #include <asm/errno.h>
  29 #include <asm/esr.h>
  30 #include <asm/irq.h>
  31 #include <asm/memory.h>
  32 #include <asm/mmu.h>
  33 #include <asm/processor.h>
  34 #include <asm/ptrace.h>
  35 #include <asm/thread_info.h>
  36 #include <asm/asm-uaccess.h>
  37 #include <asm/unistd.h>
  38
  39 /*
  40  * Context tracking subsystem.  Used to instrument transitions
  41  * between user and kernel mode.
  42  */
  43         .macro ct_user_exit, syscall = 0
  44 #ifdef CONFIG_CONTEXT_TRACKING
  45         bl      context_tracking_user_exit
  46         .if \syscall == 1
  47         /*
  48          * Save/restore needed during syscalls.  Restore syscall arguments from
  49          * the values already saved on stack during kernel_entry.
  50          */
  51         ldp     x0, x1, [sp]
  52         ldp     x2, x3, [sp, #S_X2]
  53         ldp     x4, x5, [sp, #S_X4]
  54         ldp     x6, x7, [sp, #S_X6]
  55         .endif
  56 #endif
  57         .endm
  58
  59         .macro ct_user_enter
  60 #ifdef CONFIG_CONTEXT_TRACKING
  61         bl      context_tracking_user_enter
  62 #endif
  63         .endm
  64
  65 /*
  66  * Bad Abort numbers
  67  *-----------------
  68  */
  69 #define BAD_SYNC        0
  70 #define BAD_IRQ         1
  71 #define BAD_FIQ         2
  72 #define BAD_ERROR       3
  73
  74         .macro kernel_ventry, el, label, regsize = 64
  75         .align 7
  76 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
  77 alternative_if ARM64_UNMAP_KERNEL_AT_EL0
  78         .if     \el == 0
  79         .if     \regsize == 64
  80         mrs     x30, tpidrro_el0
  81         msr     tpidrro_el0, xzr
  82         .else
  83         mov     x30, xzr
  84         .endif
  85         .endif
  86 alternative_else_nop_endif
  87 #endif
  88
  89         sub     sp, sp, #S_FRAME_SIZE
  90 #ifdef CONFIG_VMAP_STACK
  91         /*
  92          * Test whether the SP has overflowed, without corrupting a GPR.
  93          * Task and IRQ stacks are aligned to (1 << THREAD_SHIFT).
  94          */
  95         add     sp, sp, x0                      // sp' = sp + x0
  96         sub     x0, sp, x0                      // x0' = sp' - x0 = (sp + x0) - x0 = sp
  97         tbnz    x0, #THREAD_SHIFT, 0f
  98         sub     x0, sp, x0                      // x0'' = sp' - x0' = (sp + x0) - sp = x0
  99         sub     sp, sp, x0                      // sp'' = sp' - x0 = (sp + x0) - x0 = sp
 100         b       el\()\el\()_\label
 101
 102 0:
 103         /*
 104          * Either we've just detected an overflow, or we've taken an exception
 105          * while on the overflow stack. Either way, we won't return to
 106          * userspace, and can clobber EL0 registers to free up GPRs.
 107          */
 108
 109         /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */
 110         msr     tpidr_el0, x0
 111
 112         /* Recover the original x0 value and stash it in tpidrro_el0 */
 113         sub     x0, sp, x0
 114         msr     tpidrro_el0, x0
 115
 116         /* Switch to the overflow stack */
 117         adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0
 118
 119         /*
 120          * Check whether we were already on the overflow stack. This may happen
 121          * after panic() re-enables interrupts.
 122          */
 123         mrs     x0, tpidr_el0                   // sp of interrupted context
 124         sub     x0, sp, x0                      // delta with top of overflow stack
 125         tst     x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
 126         b.ne    __bad_stack                     // no? -> bad stack pointer
 127
 128         /* We were already on the overflow stack. Restore sp/x0 and carry on. */
 129         sub     sp, sp, x0
 130         mrs     x0, tpidrro_el0
 131 #endif
 132         b       el\()\el\()_\label
 133         .endm
 134
 135         .macro tramp_alias, dst, sym
 136         mov_q   \dst, TRAMP_VALIAS
 137         add     \dst, \dst, #(\sym - .entry.tramp.text)
 138         .endm
 139
 140         .macro  kernel_entry, el, regsize = 64
 141         .if     \regsize == 32
 142         mov     w0, w0                          // zero upper 32 bits of x0
 143         .endif
 144         stp     x0, x1, [sp, #16 * 0]
 145         stp     x2, x3, [sp, #16 * 1]
 146         stp     x4, x5, [sp, #16 * 2]
 147         stp     x6, x7, [sp, #16 * 3]
 148         stp     x8, x9, [sp, #16 * 4]
 149         stp     x10, x11, [sp, #16 * 5]
 150         stp     x12, x13, [sp, #16 * 6]
 151         stp     x14, x15, [sp, #16 * 7]
 152         stp     x16, x17, [sp, #16 * 8]
 153         stp     x18, x19, [sp, #16 * 9]
 154         stp     x20, x21, [sp, #16 * 10]
 155         stp     x22, x23, [sp, #16 * 11]
 156         stp     x24, x25, [sp, #16 * 12]
 157         stp     x26, x27, [sp, #16 * 13]
 158         stp     x28, x29, [sp, #16 * 14]
 159
 160         .if     \el == 0
 161         mrs     x21, sp_el0
 162         ldr_this_cpu    tsk, __entry_task, x20  // Ensure MDSCR_EL1.SS is clear,
 163         ldr     x19, [tsk, #TSK_TI_FLAGS]       // since we can unmask debug
 164         disable_step_tsk x19, x20               // exceptions when scheduling.
 165
 166         mov     x29, xzr                        // fp pointed to user-space
 167         .else
 168         add     x21, sp, #S_FRAME_SIZE
 169         get_thread_info tsk
 170         /* Save the task's original addr_limit and set USER_DS */
 171         ldr     x20, [tsk, #TSK_TI_ADDR_LIMIT]
 172         str     x20, [sp, #S_ORIG_ADDR_LIMIT]
 173         mov     x20, #USER_DS
 174         str     x20, [tsk, #TSK_TI_ADDR_LIMIT]
 175         /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */
 176         .endif /* \el == 0 */
 177         mrs     x22, elr_el1
 178         mrs     x23, spsr_el1
 179         stp     lr, x21, [sp, #S_LR]
 180
 181         /*
 182          * In order to be able to dump the contents of struct pt_regs at the
 183          * time the exception was taken (in case we attempt to walk the call
 184          * stack later), chain it together with the stack frames.
 185          */
 186         .if \el == 0
 187         stp     xzr, xzr, [sp, #S_STACKFRAME]
 188         .else
 189         stp     x29, x22, [sp, #S_STACKFRAME]
 190         .endif
 191         add     x29, sp, #S_STACKFRAME
 192
 193 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
 194         /*
 195          * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
 196          * EL0, there is no need to check the state of TTBR0_EL1 since
 197          * accesses are always enabled.
 198          * Note that the meaning of this bit differs from the ARMv8.1 PAN
 199          * feature as all TTBR0_EL1 accesses are disabled, not just those to
 200          * user mappings.
 201          */
 202 alternative_if ARM64_HAS_PAN
 203         b       1f                              // skip TTBR0 PAN
 204 alternative_else_nop_endif
 205
 206         .if     \el != 0
 207         mrs     x21, ttbr0_el1
 208         tst     x21, #TTBR_ASID_MASK            // Check for the reserved ASID
 209         orr     x23, x23, #PSR_PAN_BIT          // Set the emulated PAN in the saved SPSR
 210         b.eq    1f                              // TTBR0 access already disabled
 211         and     x23, x23, #~PSR_PAN_BIT         // Clear the emulated PAN in the saved SPSR
 212         .endif
 213
 214         __uaccess_ttbr0_disable x21
 215 1:
 216 #endif
 217
 218         stp     x22, x23, [sp, #S_PC]
 219
 220         /*
 221          * Set syscallno to -1 by default (overridden later if real syscall).
 222          */
 223         .if     \el == 0
 224         mvn     w21, wzr
 225         str     w21, [sp, #S_SYSCALLNO]
 226         .endif
 227
 228         /*
 229          * Set sp_el0 to current thread_info.
 230          */
 231         .if     \el == 0
 232         msr     sp_el0, tsk
 233         .endif
 234
 235         /*
 236          * Registers that may be useful after this macro is invoked:
 237          *
 238          * x21 - aborted SP
 239          * x22 - aborted PC
 240          * x23 - aborted PSTATE
 241         */
 242         .endm
 243
 244         .macro  kernel_exit, el
 245         .if     \el != 0
 246         /* Restore the task's original addr_limit. */
 247         ldr     x20, [sp, #S_ORIG_ADDR_LIMIT]
 248         str     x20, [tsk, #TSK_TI_ADDR_LIMIT]
 249
 250         /* No need to restore UAO, it will be restored from SPSR_EL1 */
 251         .endif
 252
 253         ldp     x21, x22, [sp, #S_PC]           // load ELR, SPSR
 254         .if     \el == 0
 255         ct_user_enter
 256         .endif
 257
 258 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
 259         /*
 260          * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
 261          * PAN bit checking.
 262          */
 263 alternative_if ARM64_HAS_PAN
 264         b       2f                              // skip TTBR0 PAN
 265 alternative_else_nop_endif
 266
 267         .if     \el != 0
 268         tbnz    x22, #22, 1f                    // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
 269         .endif
 270
 271         __uaccess_ttbr0_enable x0, x1
 272
 273         .if     \el == 0
 274         /*
 275          * Enable errata workarounds only if returning to user. The only
 276          * workaround currently required for TTBR0_EL1 changes are for the
 277          * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
 278          * corruption).
 279          */
 280         post_ttbr_update_workaround
 281         .endif
 282 1:
 283         .if     \el != 0
 284         and     x22, x22, #~PSR_PAN_BIT         // ARMv8.0 CPUs do not understand this bit
 285         .endif
 286 2:
 287 #endif
 288
 289         .if     \el == 0
 290         ldr     x23, [sp, #S_SP]                // load return stack pointer
 291         msr     sp_el0, x23
 292         tst     x22, #PSR_MODE32_BIT            // native task?
 293         b.eq    3f
 294
 295 #ifdef CONFIG_ARM64_ERRATUM_845719
 296 alternative_if ARM64_WORKAROUND_845719
 297 #ifdef CONFIG_PID_IN_CONTEXTIDR
 298         mrs     x29, contextidr_el1
 299         msr     contextidr_el1, x29
 300 #else
 301         msr contextidr_el1, xzr
 302 #endif
 303 alternative_else_nop_endif
 304 #endif
 305 3:
 306         .endif
 307
 308         msr     elr_el1, x21                    // set up the return data
 309         msr     spsr_el1, x22
 310         ldp     x0, x1, [sp, #16 * 0]
 311         ldp     x2, x3, [sp, #16 * 1]
 312         ldp     x4, x5, [sp, #16 * 2]
 313         ldp     x6, x7, [sp, #16 * 3]
 314         ldp     x8, x9, [sp, #16 * 4]
 315         ldp     x10, x11, [sp, #16 * 5]
 316         ldp     x12, x13, [sp, #16 * 6]
 317         ldp     x14, x15, [sp, #16 * 7]
 318         ldp     x16, x17, [sp, #16 * 8]
 319         ldp     x18, x19, [sp, #16 * 9]
 320         ldp     x20, x21, [sp, #16 * 10]
 321         ldp     x22, x23, [sp, #16 * 11]
 322         ldp     x24, x25, [sp, #16 * 12]
 323         ldp     x26, x27, [sp, #16 * 13]
 324         ldp     x28, x29, [sp, #16 * 14]
 325         ldr     lr, [sp, #S_LR]
 326         add     sp, sp, #S_FRAME_SIZE           // restore sp
 327
 328         .if     \el == 0
 329 alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
 330 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
 331         bne     4f
 332         msr     far_el1, x30
 333         tramp_alias     x30, tramp_exit_native
 334         br      x30
 335 4:
 336         tramp_alias     x30, tramp_exit_compat
 337         br      x30
 338 #endif
 339         .else
 340         eret
 341         .endif
 342         .endm
 343
 344         .macro  irq_stack_entry
 345         mov     x19, sp                 // preserve the original sp
 346
 347         /*
 348          * Compare sp with the base of the task stack.
 349          * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
 350          * and should switch to the irq stack.
 351          */
 352         ldr     x25, [tsk, TSK_STACK]
 353         eor     x25, x25, x19
 354         and     x25, x25, #~(THREAD_SIZE - 1)
 355         cbnz    x25, 9998f
 356
 357         ldr_this_cpu x25, irq_stack_ptr, x26
 358         mov     x26, #IRQ_STACK_SIZE
 359         add     x26, x25, x26
 360
 361         /* switch to the irq stack */
 362         mov     sp, x26
 363 9998:
 364         .endm
 365
 366         /*
 367          * x19 should be preserved between irq_stack_entry and
 368          * irq_stack_exit.
 369          */
 370         .macro  irq_stack_exit
 371         mov     sp, x19
 372         .endm
 373
 374 /*
 375  * These are the registers used in the syscall handler, and allow us to
 376  * have in theory up to 7 arguments to a function - x0 to x6.
 377  *
 378  * x7 is reserved for the system call number in 32-bit mode.
 379  */
 380 wsc_nr  .req    w25             // number of system calls
 381 wscno   .req    w26             // syscall number
 382 xscno   .req    x26             // syscall number (zero-extended)
 383 stbl    .req    x27             // syscall table pointer
 384 tsk     .req    x28             // current thread_info
 385
 386 /*
 387  * Interrupt handling.
 388  */
 389         .macro  irq_handler
 390         ldr_l   x1, handle_arch_irq
 391         mov     x0, sp
 392         irq_stack_entry
 393         blr     x1
 394         irq_stack_exit
 395         .endm
 396
 397         .text
 398
 399 /*
 400  * Exception vectors.
 401  */
 402         .pushsection ".entry.text", "ax"
 403
 404         .align  11
 405 ENTRY(vectors)
 406         kernel_ventry   1, sync_invalid                 // Synchronous EL1t
 407         kernel_ventry   1, irq_invalid                  // IRQ EL1t
 408         kernel_ventry   1, fiq_invalid                  // FIQ EL1t
 409         kernel_ventry   1, error_invalid                // Error EL1t
 410
 411         kernel_ventry   1, sync                         // Synchronous EL1h
 412         kernel_ventry   1, irq                          // IRQ EL1h
 413         kernel_ventry   1, fiq_invalid                  // FIQ EL1h
 414         kernel_ventry   1, error_invalid                // Error EL1h
 415
 416         kernel_ventry   0, sync                         // Synchronous 64-bit EL0
 417         kernel_ventry   0, irq                          // IRQ 64-bit EL0
 418         kernel_ventry   0, fiq_invalid                  // FIQ 64-bit EL0
 419         kernel_ventry   0, error_invalid                // Error 64-bit EL0
 420
 421 #ifdef CONFIG_COMPAT
 422         kernel_ventry   0, sync_compat, 32              // Synchronous 32-bit EL0
 423         kernel_ventry   0, irq_compat, 32               // IRQ 32-bit EL0
 424         kernel_ventry   0, fiq_invalid_compat, 32       // FIQ 32-bit EL0
 425         kernel_ventry   0, error_invalid_compat, 32     // Error 32-bit EL0
 426 #else
 427         kernel_ventry   0, sync_invalid, 32             // Synchronous 32-bit EL0
 428         kernel_ventry   0, irq_invalid, 32              // IRQ 32-bit EL0
 429         kernel_ventry   0, fiq_invalid, 32              // FIQ 32-bit EL0
 430         kernel_ventry   0, error_invalid, 32            // Error 32-bit EL0
 431 #endif
 432 END(vectors)
 433
 434 #ifdef CONFIG_VMAP_STACK
 435         /*
 436          * We detected an overflow in kernel_ventry, which switched to the
 437          * overflow stack. Stash the exception regs, and head to our overflow
 438          * handler.
 439          */
 440 __bad_stack:
 441         /* Restore the original x0 value */
 442         mrs     x0, tpidrro_el0
 443
 444         /*
 445          * Store the original GPRs to the new stack. The orginal SP (minus
 446          * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry.
 447          */
 448         sub     sp, sp, #S_FRAME_SIZE
 449         kernel_entry 1
 450         mrs     x0, tpidr_el0
 451         add     x0, x0, #S_FRAME_SIZE
 452         str     x0, [sp, #S_SP]
 453
 454         /* Stash the regs for handle_bad_stack */
 455         mov     x0, sp
 456
 457         /* Time to die */
 458         bl      handle_bad_stack
 459         ASM_BUG()
 460 #endif /* CONFIG_VMAP_STACK */
 461
 462 /*
 463  * Invalid mode handlers
 464  */
 465         .macro  inv_entry, el, reason, regsize = 64
 466         kernel_entry \el, \regsize
 467         mov     x0, sp
 468         mov     x1, #\reason
 469         mrs     x2, esr_el1
 470         bl      bad_mode
 471         ASM_BUG()
 472         .endm
 473
 474 el0_sync_invalid:
 475         inv_entry 0, BAD_SYNC
 476 ENDPROC(el0_sync_invalid)
 477
 478 el0_irq_invalid:
 479         inv_entry 0, BAD_IRQ
 480 ENDPROC(el0_irq_invalid)
 481
 482 el0_fiq_invalid:
 483         inv_entry 0, BAD_FIQ
 484 ENDPROC(el0_fiq_invalid)
 485
 486 el0_error_invalid:
 487         inv_entry 0, BAD_ERROR
 488 ENDPROC(el0_error_invalid)
 489
 490 #ifdef CONFIG_COMPAT
 491 el0_fiq_invalid_compat:
 492         inv_entry 0, BAD_FIQ, 32
 493 ENDPROC(el0_fiq_invalid_compat)
 494
 495 el0_error_invalid_compat:
 496         inv_entry 0, BAD_ERROR, 32
 497 ENDPROC(el0_error_invalid_compat)
 498 #endif
 499
 500 el1_sync_invalid:
 501         inv_entry 1, BAD_SYNC
 502 ENDPROC(el1_sync_invalid)
 503
 504 el1_irq_invalid:
 505         inv_entry 1, BAD_IRQ
 506 ENDPROC(el1_irq_invalid)
 507
 508 el1_fiq_invalid:
 509         inv_entry 1, BAD_FIQ
 510 ENDPROC(el1_fiq_invalid)
 511
 512 el1_error_invalid:
 513         inv_entry 1, BAD_ERROR
 514 ENDPROC(el1_error_invalid)
 515
 516 /*
 517  * EL1 mode handlers.
 518  */
 519         .align  6
 520 el1_sync:
 521         kernel_entry 1
 522         mrs     x1, esr_el1                     // read the syndrome register
 523         lsr     x24, x1, #ESR_ELx_EC_SHIFT      // exception class
 524         cmp     x24, #ESR_ELx_EC_DABT_CUR       // data abort in EL1
 525         b.eq    el1_da
 526         cmp     x24, #ESR_ELx_EC_IABT_CUR       // instruction abort in EL1
 527         b.eq    el1_ia
 528         cmp     x24, #ESR_ELx_EC_SYS64          // configurable trap
 529         b.eq    el1_undef
 530         cmp     x24, #ESR_ELx_EC_SP_ALIGN       // stack alignment exception
 531         b.eq    el1_sp_pc
 532         cmp     x24, #ESR_ELx_EC_PC_ALIGN       // pc alignment exception
 533         b.eq    el1_sp_pc
 534         cmp     x24, #ESR_ELx_EC_UNKNOWN        // unknown exception in EL1
 535         b.eq    el1_undef
 536         cmp     x24, #ESR_ELx_EC_BREAKPT_CUR    // debug exception in EL1
 537         b.ge    el1_dbg
 538         b       el1_inv
 539
 540 el1_ia:
 541         /*
 542          * Fall through to the Data abort case
 543          */
 544 el1_da:
 545         /*
 546          * Data abort handling
 547          */
 548         mrs     x3, far_el1
 549         enable_dbg
 550         // re-enable interrupts if they were enabled in the aborted context
 551         tbnz    x23, #7, 1f                     // PSR_I_BIT
 552         enable_irq
 553 1:
 554         clear_address_tag x0, x3
 555         mov     x2, sp                          // struct pt_regs
 556         bl      do_mem_abort
 557
 558         // disable interrupts before pulling preserved data off the stack
 559         disable_irq
 560         kernel_exit 1
 561 el1_sp_pc:
 562         /*
 563          * Stack or PC alignment exception handling
 564          */
 565         mrs     x0, far_el1
 566         enable_dbg
 567         mov     x2, sp
 568         bl      do_sp_pc_abort
 569         ASM_BUG()
 570 el1_undef:
 571         /*
 572          * Undefined instruction
 573          */
 574         enable_dbg
 575         mov     x0, sp
 576         bl      do_undefinstr
 577         ASM_BUG()
 578 el1_dbg:
 579         /*
 580          * Debug exception handling
 581          */
 582         cmp     x24, #ESR_ELx_EC_BRK64          // if BRK64
 583         cinc    x24, x24, eq                    // set bit '0'
 584         tbz     x24, #0, el1_inv                // EL1 only
 585         mrs     x0, far_el1
 586         mov     x2, sp                          // struct pt_regs
 587         bl      do_debug_exception
 588         kernel_exit 1
 589 el1_inv:
 590         // TODO: add support for undefined instructions in kernel mode
 591         enable_dbg
 592         mov     x0, sp
 593         mov     x2, x1
 594         mov     x1, #BAD_SYNC
 595         bl      bad_mode
 596         ASM_BUG()
 597 ENDPROC(el1_sync)
 598
 599         .align  6
 600 el1_irq:
 601         kernel_entry 1
 602         enable_dbg
 603 #ifdef CONFIG_TRACE_IRQFLAGS
 604         bl      trace_hardirqs_off
 605 #endif
 606
 607         irq_handler
 608
 609 #ifdef CONFIG_PREEMPT
 610         ldr     w24, [tsk, #TSK_TI_PREEMPT]     // get preempt count
 611         cbnz    w24, 1f                         // preempt count != 0
 612         ldr     x0, [tsk, #TSK_TI_FLAGS]        // get flags
 613         tbz     x0, #TIF_NEED_RESCHED, 1f       // needs rescheduling?
 614         bl      el1_preempt
 615 1:
 616 #endif
 617 #ifdef CONFIG_TRACE_IRQFLAGS
 618         bl      trace_hardirqs_on
 619 #endif
 620         kernel_exit 1
 621 ENDPROC(el1_irq)
 622
 623 #ifdef CONFIG_PREEMPT
 624 el1_preempt:
 625         mov     x24, lr
 626 1:      bl      preempt_schedule_irq            // irq en/disable is done inside
 627         ldr     x0, [tsk, #TSK_TI_FLAGS]        // get new tasks TI_FLAGS
 628         tbnz    x0, #TIF_NEED_RESCHED, 1b       // needs rescheduling?
 629         ret     x24
 630 #endif
 631
 632 /*
 633  * EL0 mode handlers.
 634  */
 635         .align  6
 636 el0_sync:
 637         kernel_entry 0
 638         mrs     x25, esr_el1                    // read the syndrome register
 639         lsr     x24, x25, #ESR_ELx_EC_SHIFT     // exception class
 640         cmp     x24, #ESR_ELx_EC_SVC64          // SVC in 64-bit state
 641         b.eq    el0_svc
 642         cmp     x24, #ESR_ELx_EC_DABT_LOW       // data abort in EL0
 643         b.eq    el0_da
 644         cmp     x24, #ESR_ELx_EC_IABT_LOW       // instruction abort in EL0
 645         b.eq    el0_ia
 646         cmp     x24, #ESR_ELx_EC_FP_ASIMD       // FP/ASIMD access
 647         b.eq    el0_fpsimd_acc
 648         cmp     x24, #ESR_ELx_EC_FP_EXC64       // FP/ASIMD exception
 649         b.eq    el0_fpsimd_exc
 650         cmp     x24, #ESR_ELx_EC_SYS64          // configurable trap
 651         b.eq    el0_sys
 652         cmp     x24, #ESR_ELx_EC_SP_ALIGN       // stack alignment exception
 653         b.eq    el0_sp_pc
 654         cmp     x24, #ESR_ELx_EC_PC_ALIGN       // pc alignment exception
 655         b.eq    el0_sp_pc
 656         cmp     x24, #ESR_ELx_EC_UNKNOWN        // unknown exception in EL0
 657         b.eq    el0_undef
 658         cmp     x24, #ESR_ELx_EC_BREAKPT_LOW    // debug exception in EL0
 659         b.ge    el0_dbg
 660         b       el0_inv
 661
 662 #ifdef CONFIG_COMPAT
 663         .align  6
 664 el0_sync_compat:
 665         kernel_entry 0, 32
 666         mrs     x25, esr_el1                    // read the syndrome register
 667         lsr     x24, x25, #ESR_ELx_EC_SHIFT     // exception class
 668         cmp     x24, #ESR_ELx_EC_SVC32          // SVC in 32-bit state
 669         b.eq    el0_svc_compat
 670         cmp     x24, #ESR_ELx_EC_DABT_LOW       // data abort in EL0
 671         b.eq    el0_da
 672         cmp     x24, #ESR_ELx_EC_IABT_LOW       // instruction abort in EL0
 673         b.eq    el0_ia
 674         cmp     x24, #ESR_ELx_EC_FP_ASIMD       // FP/ASIMD access
 675         b.eq    el0_fpsimd_acc
 676         cmp     x24, #ESR_ELx_EC_FP_EXC32       // FP/ASIMD exception
 677         b.eq    el0_fpsimd_exc
 678         cmp     x24, #ESR_ELx_EC_PC_ALIGN       // pc alignment exception
 679         b.eq    el0_sp_pc
 680         cmp     x24, #ESR_ELx_EC_UNKNOWN        // unknown exception in EL0
 681         b.eq    el0_undef
 682         cmp     x24, #ESR_ELx_EC_CP15_32        // CP15 MRC/MCR trap
 683         b.eq    el0_undef
 684         cmp     x24, #ESR_ELx_EC_CP15_64        // CP15 MRRC/MCRR trap
 685         b.eq    el0_undef
 686         cmp     x24, #ESR_ELx_EC_CP14_MR        // CP14 MRC/MCR trap
 687         b.eq    el0_undef
 688         cmp     x24, #ESR_ELx_EC_CP14_LS        // CP14 LDC/STC trap
 689         b.eq    el0_undef
 690         cmp     x24, #ESR_ELx_EC_CP14_64        // CP14 MRRC/MCRR trap
 691         b.eq    el0_undef
 692         cmp     x24, #ESR_ELx_EC_BREAKPT_LOW    // debug exception in EL0
 693         b.ge    el0_dbg
 694         b       el0_inv
 695 el0_svc_compat:
 696         /*
 697          * AArch32 syscall handling
 698          */
 699         adrp    stbl, compat_sys_call_table     // load compat syscall table pointer
 700         mov     wscno, w7                       // syscall number in w7 (r7)
 701         mov     wsc_nr, #__NR_compat_syscalls
 702         b       el0_svc_naked
 703
 704         .align  6
 705 el0_irq_compat:
 706         kernel_entry 0, 32
 707         b       el0_irq_naked
 708 #endif
 709
 710 el0_da:
 711         /*
 712          * Data abort handling
 713          */
 714         mrs     x26, far_el1
 715         // enable interrupts before calling the main handler
 716         enable_dbg_and_irq
 717         ct_user_exit
 718         clear_address_tag x0, x26
 719         mov     x1, x25
 720         mov     x2, sp
 721         bl      do_mem_abort
 722         b       ret_to_user
 723 el0_ia:
 724         /*
 725          * Instruction abort handling
 726          */
 727         mrs     x26, far_el1
 728         // enable interrupts before calling the main handler
 729         enable_dbg_and_irq
 730         ct_user_exit
 731         mov     x0, x26
 732         mov     x1, x25
 733         mov     x2, sp
 734         bl      do_mem_abort
 735         b       ret_to_user
 736 el0_fpsimd_acc:
 737         /*
 738          * Floating Point or Advanced SIMD access
 739          */
 740         enable_dbg
 741         ct_user_exit
 742         mov     x0, x25
 743         mov     x1, sp
 744         bl      do_fpsimd_acc
 745         b       ret_to_user
 746 el0_fpsimd_exc:
 747         /*
 748          * Floating Point or Advanced SIMD exception
 749          */
 750         enable_dbg
 751         ct_user_exit
 752         mov     x0, x25
 753         mov     x1, sp
 754         bl      do_fpsimd_exc
 755         b       ret_to_user
 756 el0_sp_pc:
 757         /*
 758          * Stack or PC alignment exception handling
 759          */
 760         mrs     x26, far_el1
 761         // enable interrupts before calling the main handler
 762         enable_dbg_and_irq
 763         ct_user_exit
 764         mov     x0, x26
 765         mov     x1, x25
 766         mov     x2, sp
 767         bl      do_sp_pc_abort
 768         b       ret_to_user
 769 el0_undef:
 770         /*
 771          * Undefined instruction
 772          */
 773         // enable interrupts before calling the main handler
 774         enable_dbg_and_irq
 775         ct_user_exit
 776         mov     x0, sp
 777         bl      do_undefinstr
 778         b       ret_to_user
 779 el0_sys:
 780         /*
 781          * System instructions, for trapped cache maintenance instructions
 782          */
 783         enable_dbg_and_irq
 784         ct_user_exit
 785         mov     x0, x25
 786         mov     x1, sp
 787         bl      do_sysinstr
 788         b       ret_to_user
 789 el0_dbg:
 790         /*
 791          * Debug exception handling
 792          */
 793         tbnz    x24, #0, el0_inv                // EL0 only
 794         mrs     x0, far_el1
 795         mov     x1, x25
 796         mov     x2, sp
 797         bl      do_debug_exception
 798         enable_dbg
 799         ct_user_exit
 800         b       ret_to_user
 801 el0_inv:
 802         enable_dbg
 803         ct_user_exit
 804         mov     x0, sp
 805         mov     x1, #BAD_SYNC
 806         mov     x2, x25
 807         bl      bad_el0_sync
 808         b       ret_to_user
 809 ENDPROC(el0_sync)
 810
 811         .align  6
 812 el0_irq:
 813         kernel_entry 0
 814 el0_irq_naked:
 815         enable_dbg
 816 #ifdef CONFIG_TRACE_IRQFLAGS
 817         bl      trace_hardirqs_off
 818 #endif
 819
 820         ct_user_exit
 821         irq_handler
 822
 823 #ifdef CONFIG_TRACE_IRQFLAGS
 824         bl      trace_hardirqs_on
 825 #endif
 826         b       ret_to_user
 827 ENDPROC(el0_irq)
 828
 829 /*
 830  * This is the fast syscall return path.  We do as little as possible here,
 831  * and this includes saving x0 back into the kernel stack.
 832  */
 833 ret_fast_syscall:
 834         disable_irq                             // disable interrupts
 835         str     x0, [sp, #S_X0]                 // returned x0
 836         ldr     x1, [tsk, #TSK_TI_FLAGS]        // re-check for syscall tracing
 837         and     x2, x1, #_TIF_SYSCALL_WORK
 838         cbnz    x2, ret_fast_syscall_trace
 839         and     x2, x1, #_TIF_WORK_MASK
 840         cbnz    x2, work_pending
 841         enable_step_tsk x1, x2
 842         kernel_exit 0
 843 ret_fast_syscall_trace:
 844         enable_irq                              // enable interrupts
 845         b       __sys_trace_return_skipped      // we already saved x0
 846
 847 /*
 848  * Ok, we need to do extra processing, enter the slow path.
 849  */
 850 work_pending:
 851         mov     x0, sp                          // 'regs'
 852         bl      do_notify_resume
 853 #ifdef CONFIG_TRACE_IRQFLAGS
 854         bl      trace_hardirqs_on               // enabled while in userspace
 855 #endif
 856         ldr     x1, [tsk, #TSK_TI_FLAGS]        // re-check for single-step
 857         b       finish_ret_to_user
 858 /*
 859  * "slow" syscall return path.
 860  */
 861 ret_to_user:
 862         disable_irq                             // disable interrupts
 863         ldr     x1, [tsk, #TSK_TI_FLAGS]
 864         and     x2, x1, #_TIF_WORK_MASK
 865         cbnz    x2, work_pending
 866 finish_ret_to_user:
 867         enable_step_tsk x1, x2
 868         kernel_exit 0
 869 ENDPROC(ret_to_user)
 870
 871 /*
 872  * SVC handler.
 873  */
 874         .align  6
 875 el0_svc:
 876         adrp    stbl, sys_call_table            // load syscall table pointer
 877         mov     wscno, w8                       // syscall number in w8
 878         mov     wsc_nr, #__NR_syscalls
 879 el0_svc_naked:                                  // compat entry point
 880         stp     x0, xscno, [sp, #S_ORIG_X0]     // save the original x0 and syscall number
 881         enable_dbg_and_irq
 882         ct_user_exit 1
 883
 884         ldr     x16, [tsk, #TSK_TI_FLAGS]       // check for syscall hooks
 885         tst     x16, #_TIF_SYSCALL_WORK
 886         b.ne    __sys_trace
 887         cmp     wscno, wsc_nr                   // check upper syscall limit
 888         b.hs    ni_sys
 889         ldr     x16, [stbl, xscno, lsl #3]      // address in the syscall table
 890         blr     x16                             // call sys_* routine
 891         b       ret_fast_syscall
 892 ni_sys:
 893         mov     x0, sp
 894         bl      do_ni_syscall
 895         b       ret_fast_syscall
 896 ENDPROC(el0_svc)
 897
 898         /*
 899          * This is the really slow path.  We're going to be doing context
 900          * switches, and waiting for our parent to respond.
 901          */
 902 __sys_trace:
 903         cmp     wscno, #-1                      // user-issued syscall(-1)?
 904         b.ne    1f
 905         mov     x0, #-ENOSYS                    // set default errno if so
 906         str     x0, [sp, #S_X0]
 907 1:      mov     x0, sp
 908         bl      syscall_trace_enter
 909         cmp     w0, #-1                         // skip the syscall?
 910         b.eq    __sys_trace_return_skipped
 911         mov     wscno, w0                       // syscall number (possibly new)
 912         mov     x1, sp                          // pointer to regs
 913         cmp     wscno, wsc_nr                   // check upper syscall limit
 914         b.hs    __ni_sys_trace
 915         ldp     x0, x1, [sp]                    // restore the syscall args
 916         ldp     x2, x3, [sp, #S_X2]
 917         ldp     x4, x5, [sp, #S_X4]
 918         ldp     x6, x7, [sp, #S_X6]
 919         ldr     x16, [stbl, xscno, lsl #3]      // address in the syscall table
 920         blr     x16                             // call sys_* routine
 921
 922 __sys_trace_return:
 923         str     x0, [sp, #S_X0]                 // save returned x0
 924 __sys_trace_return_skipped:
 925         mov     x0, sp
 926         bl      syscall_trace_exit
 927         b       ret_to_user
 928
 929 __ni_sys_trace:
 930         mov     x0, sp
 931         bl      do_ni_syscall
 932         b       __sys_trace_return
 933
 934         .popsection                             // .entry.text
 935
 936 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
 937 /*
 938  * Exception vectors trampoline.
 939  */
 940         .pushsection ".entry.tramp.text", "ax"
 941
 942         .macro tramp_map_kernel, tmp
 943         mrs     \tmp, ttbr1_el1
 944         sub     \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
 945         bic     \tmp, \tmp, #USER_ASID_FLAG
 946         msr     ttbr1_el1, \tmp
 947 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
 948 alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
 949         /* ASID already in \tmp[63:48] */
 950         movk    \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12)
 951         movk    \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12)
 952         /* 2MB boundary containing the vectors, so we nobble the walk cache */
 953         movk    \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
 954         isb
 955         tlbi    vae1, \tmp
 956         dsb     nsh
 957 alternative_else_nop_endif
 958 #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */
 959         .endm
 960
 961         .macro tramp_unmap_kernel, tmp
 962         mrs     \tmp, ttbr1_el1
 963         add     \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
 964         orr     \tmp, \tmp, #USER_ASID_FLAG
 965         msr     ttbr1_el1, \tmp
 966         /*
 967          * We avoid running the post_ttbr_update_workaround here because
 968          * it's only needed by Cavium ThunderX, which requires KPTI to be
 969          * disabled.
 970          */
 971         .endm
 972
 973         .macro tramp_ventry, regsize = 64
 974         .align  7
 975 1:
 976         .if     \regsize == 64
 977         msr     tpidrro_el0, x30        // Restored in kernel_ventry
 978         .endif
 979         /*
 980          * Defend against branch aliasing attacks by pushing a dummy
 981          * entry onto the return stack and using a RET instruction to
 982          * enter the full-fat kernel vectors.
 983          */
 984         bl      2f
 985         b       .
 986 2:
 987         tramp_map_kernel        x30
 988 #ifdef CONFIG_RANDOMIZE_BASE
 989         adr     x30, tramp_vectors + PAGE_SIZE
 990 alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
 991         ldr     x30, [x30]
 992 #else
 993         ldr     x30, =vectors
 994 #endif
 995         prfm    plil1strm, [x30, #(1b - tramp_vectors)]
 996         msr     vbar_el1, x30
 997         add     x30, x30, #(1b - tramp_vectors)
 998         isb
 999         ret
1000         .endm
1001
1002         .macro tramp_exit, regsize = 64
1003         adr     x30, tramp_vectors
1004         msr     vbar_el1, x30
1005         tramp_unmap_kernel      x30
1006         .if     \regsize == 64
1007         mrs     x30, far_el1
1008         .endif
1009         eret
1010         .endm
1011
1012         .align  11
1013 ENTRY(tramp_vectors)
1014         .space  0x400
1015
1016         tramp_ventry
1017         tramp_ventry
1018         tramp_ventry
1019         tramp_ventry
1020
1021         tramp_ventry    32
1022         tramp_ventry    32
1023         tramp_ventry    32
1024         tramp_ventry    32
1025 END(tramp_vectors)
1026
1027 ENTRY(tramp_exit_native)
1028         tramp_exit
1029 END(tramp_exit_native)
1030
1031 ENTRY(tramp_exit_compat)
1032         tramp_exit      32
1033 END(tramp_exit_compat)
1034
1035         .ltorg
1036         .popsection                             // .entry.tramp.text
1037 #ifdef CONFIG_RANDOMIZE_BASE
1038         .pushsection ".rodata", "a"
1039         .align PAGE_SHIFT
1040         .globl  __entry_tramp_data_start
1041 __entry_tramp_data_start:
1042         .quad   vectors
1043         .popsection                             // .rodata
1044 #endif /* CONFIG_RANDOMIZE_BASE */
1045 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1046
1047 /*
1048  * Special system call wrappers.
1049  */
1050 ENTRY(sys_rt_sigreturn_wrapper)
1051         mov     x0, sp
1052         b       sys_rt_sigreturn
1053 ENDPROC(sys_rt_sigreturn_wrapper)
1054
1055 /*
1056  * Register switch for AArch64. The callee-saved registers need to be saved
1057  * and restored. On entry:
1058  *   x0 = previous task_struct (must be preserved across the switch)
1059  *   x1 = next task_struct
1060  * Previous and next are guaranteed not to be the same.
1061  *
1062  */
1063 ENTRY(cpu_switch_to)
1064         mov     x10, #THREAD_CPU_CONTEXT
1065         add     x8, x0, x10
1066         mov     x9, sp
1067         stp     x19, x20, [x8], #16             // store callee-saved registers
1068         stp     x21, x22, [x8], #16
1069         stp     x23, x24, [x8], #16
1070         stp     x25, x26, [x8], #16
1071         stp     x27, x28, [x8], #16
1072         stp     x29, x9, [x8], #16
1073         str     lr, [x8]
1074         add     x8, x1, x10
1075         ldp     x19, x20, [x8], #16             // restore callee-saved registers
1076         ldp     x21, x22, [x8], #16
1077         ldp     x23, x24, [x8], #16
1078         ldp     x25, x26, [x8], #16
1079         ldp     x27, x28, [x8], #16
1080         ldp     x29, x9, [x8], #16
1081         ldr     lr, [x8]
1082         mov     sp, x9
1083         msr     sp_el0, x1
1084         ret
1085 ENDPROC(cpu_switch_to)
1086 NOKPROBE(cpu_switch_to)
1087
1088 /*
1089  * This is how we return from a fork.
1090  */
1091 ENTRY(ret_from_fork)
1092         bl      schedule_tail
1093         cbz     x19, 1f                         // not a kernel thread
1094         mov     x0, x20
1095         blr     x19
1096 1:      get_thread_info tsk
1097         b       ret_to_user
1098 ENDPROC(ret_from_fork)
1099 NOKPROBE(ret_from_fork)