2 * Low-level exception handling code
4 * Copyright (C) 2012 ARM Ltd.
5 * Authors: Catalin Marinas <catalin.marinas@arm.com>
6 * Will Deacon <will.deacon@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/init.h>
22 #include <linux/linkage.h>
24 #include <asm/alternative.h>
25 #include <asm/assembler.h>
26 #include <asm/asm-offsets.h>
27 #include <asm/cpufeature.h>
28 #include <asm/errno.h>
31 #include <asm/memory.h>
33 #include <asm/processor.h>
34 #include <asm/ptrace.h>
35 #include <asm/thread_info.h>
36 #include <asm/asm-uaccess.h>
37 #include <asm/unistd.h>
40 * Context tracking subsystem. Used to instrument transitions
41 * between user and kernel mode.
43 .macro ct_user_exit, syscall = 0
44 #ifdef CONFIG_CONTEXT_TRACKING
45 bl context_tracking_user_exit
48 * Save/restore needed during syscalls. Restore syscall arguments from
49 * the values already saved on stack during kernel_entry.
52 ldp x2, x3, [sp, #S_X2]
53 ldp x4, x5, [sp, #S_X4]
54 ldp x6, x7, [sp, #S_X6]
60 #ifdef CONFIG_CONTEXT_TRACKING
61 bl context_tracking_user_enter
74 .macro kernel_ventry label
76 sub sp, sp, #S_FRAME_SIZE
77 #ifdef CONFIG_VMAP_STACK
79 * Test whether the SP has overflowed, without corrupting a GPR.
80 * Task and IRQ stacks are aligned to (1 << THREAD_SHIFT).
82 add sp, sp, x0 // sp' = sp + x0
83 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
84 tbnz x0, #THREAD_SHIFT, 0f
85 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
86 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
91 * Either we've just detected an overflow, or we've taken an exception
92 * while on the overflow stack. Either way, we won't return to
93 * userspace, and can clobber EL0 registers to free up GPRs.
96 /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */
99 /* Recover the original x0 value and stash it in tpidrro_el0 */
103 /* Switch to the overflow stack */
104 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0
107 * Check whether we were already on the overflow stack. This may happen
108 * after panic() re-enables interrupts.
110 mrs x0, tpidr_el0 // sp of interrupted context
111 sub x0, sp, x0 // delta with top of overflow stack
112 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
113 b.ne __bad_stack // no? -> bad stack pointer
115 /* We were already on the overflow stack. Restore sp/x0 and carry on. */
122 .macro kernel_entry, el, regsize = 64
124 mov w0, w0 // zero upper 32 bits of x0
126 stp x0, x1, [sp, #16 * 0]
127 stp x2, x3, [sp, #16 * 1]
128 stp x4, x5, [sp, #16 * 2]
129 stp x6, x7, [sp, #16 * 3]
130 stp x8, x9, [sp, #16 * 4]
131 stp x10, x11, [sp, #16 * 5]
132 stp x12, x13, [sp, #16 * 6]
133 stp x14, x15, [sp, #16 * 7]
134 stp x16, x17, [sp, #16 * 8]
135 stp x18, x19, [sp, #16 * 9]
136 stp x20, x21, [sp, #16 * 10]
137 stp x22, x23, [sp, #16 * 11]
138 stp x24, x25, [sp, #16 * 12]
139 stp x26, x27, [sp, #16 * 13]
140 stp x28, x29, [sp, #16 * 14]
144 ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear,
145 ldr x19, [tsk, #TSK_TI_FLAGS] // since we can unmask debug
146 disable_step_tsk x19, x20 // exceptions when scheduling.
148 mov x29, xzr // fp pointed to user-space
150 add x21, sp, #S_FRAME_SIZE
152 /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */
153 ldr x20, [tsk, #TSK_TI_ADDR_LIMIT]
154 str x20, [sp, #S_ORIG_ADDR_LIMIT]
155 mov x20, #TASK_SIZE_64
156 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
157 /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */
158 .endif /* \el == 0 */
161 stp lr, x21, [sp, #S_LR]
164 * In order to be able to dump the contents of struct pt_regs at the
165 * time the exception was taken (in case we attempt to walk the call
166 * stack later), chain it together with the stack frames.
169 stp xzr, xzr, [sp, #S_STACKFRAME]
171 stp x29, x22, [sp, #S_STACKFRAME]
173 add x29, sp, #S_STACKFRAME
175 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
177 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
178 * EL0, there is no need to check the state of TTBR0_EL1 since
179 * accesses are always enabled.
180 * Note that the meaning of this bit differs from the ARMv8.1 PAN
181 * feature as all TTBR0_EL1 accesses are disabled, not just those to
184 alternative_if ARM64_HAS_PAN
185 b 1f // skip TTBR0 PAN
186 alternative_else_nop_endif
190 tst x21, #0xffff << 48 // Check for the reserved ASID
191 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
192 b.eq 1f // TTBR0 access already disabled
193 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
196 __uaccess_ttbr0_disable x21
200 stp x22, x23, [sp, #S_PC]
203 * Set syscallno to -1 by default (overridden later if real syscall).
207 str w21, [sp, #S_SYSCALLNO]
211 * Set sp_el0 to current thread_info.
218 * Registers that may be useful after this macro is invoked:
222 * x23 - aborted PSTATE
226 .macro kernel_exit, el
228 /* Restore the task's original addr_limit. */
229 ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
230 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
232 /* No need to restore UAO, it will be restored from SPSR_EL1 */
235 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
240 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
242 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
245 alternative_if ARM64_HAS_PAN
246 b 2f // skip TTBR0 PAN
247 alternative_else_nop_endif
250 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
253 __uaccess_ttbr0_enable x0, x1
257 * Enable errata workarounds only if returning to user. The only
258 * workaround currently required for TTBR0_EL1 changes are for the
259 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
262 post_ttbr_update_workaround
266 and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
272 ldr x23, [sp, #S_SP] // load return stack pointer
274 #ifdef CONFIG_ARM64_ERRATUM_845719
275 alternative_if ARM64_WORKAROUND_845719
277 #ifdef CONFIG_PID_IN_CONTEXTIDR
278 mrs x29, contextidr_el1
279 msr contextidr_el1, x29
281 msr contextidr_el1, xzr
284 alternative_else_nop_endif
288 msr elr_el1, x21 // set up the return data
290 ldp x0, x1, [sp, #16 * 0]
291 ldp x2, x3, [sp, #16 * 1]
292 ldp x4, x5, [sp, #16 * 2]
293 ldp x6, x7, [sp, #16 * 3]
294 ldp x8, x9, [sp, #16 * 4]
295 ldp x10, x11, [sp, #16 * 5]
296 ldp x12, x13, [sp, #16 * 6]
297 ldp x14, x15, [sp, #16 * 7]
298 ldp x16, x17, [sp, #16 * 8]
299 ldp x18, x19, [sp, #16 * 9]
300 ldp x20, x21, [sp, #16 * 10]
301 ldp x22, x23, [sp, #16 * 11]
302 ldp x24, x25, [sp, #16 * 12]
303 ldp x26, x27, [sp, #16 * 13]
304 ldp x28, x29, [sp, #16 * 14]
306 add sp, sp, #S_FRAME_SIZE // restore sp
307 eret // return to kernel
310 .macro irq_stack_entry
311 mov x19, sp // preserve the original sp
314 * Compare sp with the base of the task stack.
315 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
316 * and should switch to the irq stack.
318 ldr x25, [tsk, TSK_STACK]
320 and x25, x25, #~(THREAD_SIZE - 1)
323 ldr_this_cpu x25, irq_stack_ptr, x26
324 mov x26, #IRQ_STACK_SIZE
327 /* switch to the irq stack */
333 * x19 should be preserved between irq_stack_entry and
336 .macro irq_stack_exit
341 * These are the registers used in the syscall handler, and allow us to
342 * have in theory up to 7 arguments to a function - x0 to x6.
344 * x7 is reserved for the system call number in 32-bit mode.
346 wsc_nr .req w25 // number of system calls
347 wscno .req w26 // syscall number
348 xscno .req x26 // syscall number (zero-extended)
349 stbl .req x27 // syscall table pointer
350 tsk .req x28 // current thread_info
353 * Interrupt handling.
356 ldr_l x1, handle_arch_irq
368 .pushsection ".entry.text", "ax"
372 kernel_ventry el1_sync_invalid // Synchronous EL1t
373 kernel_ventry el1_irq_invalid // IRQ EL1t
374 kernel_ventry el1_fiq_invalid // FIQ EL1t
375 kernel_ventry el1_error_invalid // Error EL1t
377 kernel_ventry el1_sync // Synchronous EL1h
378 kernel_ventry el1_irq // IRQ EL1h
379 kernel_ventry el1_fiq_invalid // FIQ EL1h
380 kernel_ventry el1_error_invalid // Error EL1h
382 kernel_ventry el0_sync // Synchronous 64-bit EL0
383 kernel_ventry el0_irq // IRQ 64-bit EL0
384 kernel_ventry el0_fiq_invalid // FIQ 64-bit EL0
385 kernel_ventry el0_error_invalid // Error 64-bit EL0
388 kernel_ventry el0_sync_compat // Synchronous 32-bit EL0
389 kernel_ventry el0_irq_compat // IRQ 32-bit EL0
390 kernel_ventry el0_fiq_invalid_compat // FIQ 32-bit EL0
391 kernel_ventry el0_error_invalid_compat // Error 32-bit EL0
393 kernel_ventry el0_sync_invalid // Synchronous 32-bit EL0
394 kernel_ventry el0_irq_invalid // IRQ 32-bit EL0
395 kernel_ventry el0_fiq_invalid // FIQ 32-bit EL0
396 kernel_ventry el0_error_invalid // Error 32-bit EL0
400 #ifdef CONFIG_VMAP_STACK
402 * We detected an overflow in kernel_ventry, which switched to the
403 * overflow stack. Stash the exception regs, and head to our overflow
407 /* Restore the original x0 value */
411 * Store the original GPRs to the new stack. The orginal SP (minus
412 * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry.
414 sub sp, sp, #S_FRAME_SIZE
417 add x0, x0, #S_FRAME_SIZE
420 /* Stash the regs for handle_bad_stack */
426 #endif /* CONFIG_VMAP_STACK */
429 * Invalid mode handlers
431 .macro inv_entry, el, reason, regsize = 64
432 kernel_entry \el, \regsize
441 inv_entry 0, BAD_SYNC
442 ENDPROC(el0_sync_invalid)
446 ENDPROC(el0_irq_invalid)
450 ENDPROC(el0_fiq_invalid)
453 inv_entry 0, BAD_ERROR
454 ENDPROC(el0_error_invalid)
457 el0_fiq_invalid_compat:
458 inv_entry 0, BAD_FIQ, 32
459 ENDPROC(el0_fiq_invalid_compat)
461 el0_error_invalid_compat:
462 inv_entry 0, BAD_ERROR, 32
463 ENDPROC(el0_error_invalid_compat)
467 inv_entry 1, BAD_SYNC
468 ENDPROC(el1_sync_invalid)
472 ENDPROC(el1_irq_invalid)
476 ENDPROC(el1_fiq_invalid)
479 inv_entry 1, BAD_ERROR
480 ENDPROC(el1_error_invalid)
488 mrs x1, esr_el1 // read the syndrome register
489 lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
490 cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
492 cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1
494 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
496 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
498 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
500 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1
502 cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1
508 * Fall through to the Data abort case
512 * Data abort handling
516 // re-enable interrupts if they were enabled in the aborted context
517 tbnz x23, #7, 1f // PSR_I_BIT
520 clear_address_tag x0, x3
521 mov x2, sp // struct pt_regs
524 // disable interrupts before pulling preserved data off the stack
529 * Stack or PC alignment exception handling
538 * Undefined instruction
546 * Debug exception handling
548 cmp x24, #ESR_ELx_EC_BRK64 // if BRK64
549 cinc x24, x24, eq // set bit '0'
550 tbz x24, #0, el1_inv // EL1 only
552 mov x2, sp // struct pt_regs
553 bl do_debug_exception
556 // TODO: add support for undefined instructions in kernel mode
569 #ifdef CONFIG_TRACE_IRQFLAGS
570 bl trace_hardirqs_off
575 #ifdef CONFIG_PREEMPT
576 ldr w24, [tsk, #TSK_TI_PREEMPT] // get preempt count
577 cbnz w24, 1f // preempt count != 0
578 ldr x0, [tsk, #TSK_TI_FLAGS] // get flags
579 tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
583 #ifdef CONFIG_TRACE_IRQFLAGS
589 #ifdef CONFIG_PREEMPT
592 1: bl preempt_schedule_irq // irq en/disable is done inside
593 ldr x0, [tsk, #TSK_TI_FLAGS] // get new tasks TI_FLAGS
594 tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
604 mrs x25, esr_el1 // read the syndrome register
605 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
606 cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state
608 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
610 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
612 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
614 cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception
616 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
618 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
620 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
622 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
624 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
632 mrs x25, esr_el1 // read the syndrome register
633 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
634 cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state
636 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
638 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
640 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
642 cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception
644 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
646 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
648 cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap
650 cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap
652 cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap
654 cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap
656 cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap
658 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
663 * AArch32 syscall handling
665 adrp stbl, compat_sys_call_table // load compat syscall table pointer
666 mov wscno, w7 // syscall number in w7 (r7)
667 mov wsc_nr, #__NR_compat_syscalls
678 * Data abort handling
681 // enable interrupts before calling the main handler
684 clear_address_tag x0, x26
691 * Instruction abort handling
694 // enable interrupts before calling the main handler
704 * Floating Point or Advanced SIMD access
714 * Floating Point or Advanced SIMD exception
724 * Stack or PC alignment exception handling
727 // enable interrupts before calling the main handler
737 * Undefined instruction
739 // enable interrupts before calling the main handler
747 * System instructions, for trapped cache maintenance instructions
757 * Debug exception handling
759 tbnz x24, #0, el0_inv // EL0 only
763 bl do_debug_exception
782 #ifdef CONFIG_TRACE_IRQFLAGS
783 bl trace_hardirqs_off
789 #ifdef CONFIG_TRACE_IRQFLAGS
796 * This is the fast syscall return path. We do as little as possible here,
797 * and this includes saving x0 back into the kernel stack.
800 disable_irq // disable interrupts
801 str x0, [sp, #S_X0] // returned x0
802 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for syscall tracing
803 and x2, x1, #_TIF_SYSCALL_WORK
804 cbnz x2, ret_fast_syscall_trace
805 and x2, x1, #_TIF_WORK_MASK
806 cbnz x2, work_pending
807 enable_step_tsk x1, x2
809 ret_fast_syscall_trace:
810 enable_irq // enable interrupts
811 b __sys_trace_return_skipped // we already saved x0
814 * Ok, we need to do extra processing, enter the slow path.
819 #ifdef CONFIG_TRACE_IRQFLAGS
820 bl trace_hardirqs_on // enabled while in userspace
822 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step
825 * "slow" syscall return path.
828 disable_irq // disable interrupts
829 ldr x1, [tsk, #TSK_TI_FLAGS]
830 and x2, x1, #_TIF_WORK_MASK
831 cbnz x2, work_pending
833 enable_step_tsk x1, x2
842 adrp stbl, sys_call_table // load syscall table pointer
843 mov wscno, w8 // syscall number in w8
844 mov wsc_nr, #__NR_syscalls
845 el0_svc_naked: // compat entry point
846 stp x0, xscno, [sp, #S_ORIG_X0] // save the original x0 and syscall number
850 ldr x16, [tsk, #TSK_TI_FLAGS] // check for syscall hooks
851 tst x16, #_TIF_SYSCALL_WORK
853 cmp wscno, wsc_nr // check upper syscall limit
855 ldr x16, [stbl, xscno, lsl #3] // address in the syscall table
856 blr x16 // call sys_* routine
865 * This is the really slow path. We're going to be doing context
866 * switches, and waiting for our parent to respond.
869 cmp wscno, #-1 // user-issued syscall(-1)?
871 mov x0, #-ENOSYS // set default errno if so
874 bl syscall_trace_enter
875 cmp w0, #-1 // skip the syscall?
876 b.eq __sys_trace_return_skipped
877 mov wscno, w0 // syscall number (possibly new)
878 mov x1, sp // pointer to regs
879 cmp wscno, wsc_nr // check upper syscall limit
881 ldp x0, x1, [sp] // restore the syscall args
882 ldp x2, x3, [sp, #S_X2]
883 ldp x4, x5, [sp, #S_X4]
884 ldp x6, x7, [sp, #S_X6]
885 ldr x16, [stbl, xscno, lsl #3] // address in the syscall table
886 blr x16 // call sys_* routine
889 str x0, [sp, #S_X0] // save returned x0
890 __sys_trace_return_skipped:
892 bl syscall_trace_exit
900 .popsection // .entry.text
902 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
904 * Exception vectors trampoline.
906 .pushsection ".entry.tramp.text", "ax"
908 .macro tramp_map_kernel, tmp
910 sub \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
911 bic \tmp, \tmp, #USER_ASID_FLAG
915 .macro tramp_unmap_kernel, tmp
917 add \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
918 orr \tmp, \tmp, #USER_ASID_FLAG
921 * We avoid running the post_ttbr_update_workaround here because the
922 * user and kernel ASIDs don't have conflicting mappings, so any
923 * "blessing" as described in:
925 * http://lkml.kernel.org/r/56BB848A.6060603@caviumnetworks.com
927 * will not hurt correctness. Whilst this may partially defeat the
928 * point of using split ASIDs in the first place, it avoids
929 * the hit of invalidating the entire I-cache on every return to
934 .macro tramp_ventry, regsize = 64
938 msr tpidrro_el0, x30 // Restored in kernel_ventry
942 prfm plil1strm, [x30, #(1b - tramp_vectors)]
944 add x30, x30, #(1b - tramp_vectors)
949 .macro tramp_exit, regsize = 64
950 adr x30, tramp_vectors
952 tramp_unmap_kernel x30
974 ENTRY(tramp_exit_native)
976 END(tramp_exit_native)
978 ENTRY(tramp_exit_compat)
980 END(tramp_exit_compat)
983 .popsection // .entry.tramp.text
984 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
987 * Special system call wrappers.
989 ENTRY(sys_rt_sigreturn_wrapper)
992 ENDPROC(sys_rt_sigreturn_wrapper)
995 * Register switch for AArch64. The callee-saved registers need to be saved
996 * and restored. On entry:
997 * x0 = previous task_struct (must be preserved across the switch)
998 * x1 = next task_struct
999 * Previous and next are guaranteed not to be the same.
1002 ENTRY(cpu_switch_to)
1003 mov x10, #THREAD_CPU_CONTEXT
1006 stp x19, x20, [x8], #16 // store callee-saved registers
1007 stp x21, x22, [x8], #16
1008 stp x23, x24, [x8], #16
1009 stp x25, x26, [x8], #16
1010 stp x27, x28, [x8], #16
1011 stp x29, x9, [x8], #16
1014 ldp x19, x20, [x8], #16 // restore callee-saved registers
1015 ldp x21, x22, [x8], #16
1016 ldp x23, x24, [x8], #16
1017 ldp x25, x26, [x8], #16
1018 ldp x27, x28, [x8], #16
1019 ldp x29, x9, [x8], #16
1024 ENDPROC(cpu_switch_to)
1025 NOKPROBE(cpu_switch_to)
1028 * This is how we return from a fork.
1030 ENTRY(ret_from_fork)
1032 cbz x19, 1f // not a kernel thread
1035 1: get_thread_info tsk
1037 ENDPROC(ret_from_fork)
1038 NOKPROBE(ret_from_fork)