2 * Low-level exception handling code
4 * Copyright (C) 2012 ARM Ltd.
5 * Authors: Catalin Marinas <catalin.marinas@arm.com>
6 * Will Deacon <will.deacon@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/arm-smccc.h>
22 #include <linux/init.h>
23 #include <linux/linkage.h>
25 #include <asm/alternative.h>
26 #include <asm/assembler.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/cpufeature.h>
29 #include <asm/errno.h>
32 #include <asm/memory.h>
34 #include <asm/processor.h>
35 #include <asm/ptrace.h>
36 #include <asm/thread_info.h>
37 #include <asm/asm-uaccess.h>
38 #include <asm/unistd.h>
41 * Context tracking subsystem. Used to instrument transitions
42 * between user and kernel mode.
44 .macro ct_user_exit, syscall = 0
45 #ifdef CONFIG_CONTEXT_TRACKING
46 bl context_tracking_user_exit
49 * Save/restore needed during syscalls. Restore syscall arguments from
50 * the values already saved on stack during kernel_entry.
53 ldp x2, x3, [sp, #S_X2]
54 ldp x4, x5, [sp, #S_X4]
55 ldp x6, x7, [sp, #S_X6]
61 #ifdef CONFIG_CONTEXT_TRACKING
62 bl context_tracking_user_enter
75 .macro kernel_ventry, el, label, regsize = 64
77 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
78 alternative_if ARM64_UNMAP_KERNEL_AT_EL0
87 alternative_else_nop_endif
90 sub sp, sp, #S_FRAME_SIZE
91 #ifdef CONFIG_VMAP_STACK
93 * Test whether the SP has overflowed, without corrupting a GPR.
94 * Task and IRQ stacks are aligned to (1 << THREAD_SHIFT).
96 add sp, sp, x0 // sp' = sp + x0
97 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
98 tbnz x0, #THREAD_SHIFT, 0f
99 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
100 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
105 * Either we've just detected an overflow, or we've taken an exception
106 * while on the overflow stack. Either way, we won't return to
107 * userspace, and can clobber EL0 registers to free up GPRs.
110 /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */
113 /* Recover the original x0 value and stash it in tpidrro_el0 */
117 /* Switch to the overflow stack */
118 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0
121 * Check whether we were already on the overflow stack. This may happen
122 * after panic() re-enables interrupts.
124 mrs x0, tpidr_el0 // sp of interrupted context
125 sub x0, sp, x0 // delta with top of overflow stack
126 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
127 b.ne __bad_stack // no? -> bad stack pointer
129 /* We were already on the overflow stack. Restore sp/x0 and carry on. */
136 .macro tramp_alias, dst, sym
137 mov_q \dst, TRAMP_VALIAS
138 add \dst, \dst, #(\sym - .entry.tramp.text)
141 // This macro corrupts x0-x3. It is the caller's duty
142 // to save/restore them if required.
143 .macro apply_ssbd, state, targ, tmp1, tmp2
144 #ifdef CONFIG_ARM64_SSBD
145 alternative_cb arm64_enable_wa2_handling
148 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1
150 ldr \tmp2, [tsk, #TSK_TI_FLAGS]
151 tbnz \tmp2, #TIF_SSBD, \targ
152 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2
154 alternative_cb arm64_update_smccc_conduit
155 nop // Patched to SMC/HVC #0
160 .macro kernel_entry, el, regsize = 64
162 mov w0, w0 // zero upper 32 bits of x0
164 stp x0, x1, [sp, #16 * 0]
165 stp x2, x3, [sp, #16 * 1]
166 stp x4, x5, [sp, #16 * 2]
167 stp x6, x7, [sp, #16 * 3]
168 stp x8, x9, [sp, #16 * 4]
169 stp x10, x11, [sp, #16 * 5]
170 stp x12, x13, [sp, #16 * 6]
171 stp x14, x15, [sp, #16 * 7]
172 stp x16, x17, [sp, #16 * 8]
173 stp x18, x19, [sp, #16 * 9]
174 stp x20, x21, [sp, #16 * 10]
175 stp x22, x23, [sp, #16 * 11]
176 stp x24, x25, [sp, #16 * 12]
177 stp x26, x27, [sp, #16 * 13]
178 stp x28, x29, [sp, #16 * 14]
182 ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear,
183 ldr x19, [tsk, #TSK_TI_FLAGS] // since we can unmask debug
184 disable_step_tsk x19, x20 // exceptions when scheduling.
186 apply_ssbd 1, 1f, x22, x23
188 #ifdef CONFIG_ARM64_SSBD
189 ldp x0, x1, [sp, #16 * 0]
190 ldp x2, x3, [sp, #16 * 1]
194 mov x29, xzr // fp pointed to user-space
196 add x21, sp, #S_FRAME_SIZE
198 /* Save the task's original addr_limit and set USER_DS */
199 ldr x20, [tsk, #TSK_TI_ADDR_LIMIT]
200 str x20, [sp, #S_ORIG_ADDR_LIMIT]
202 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
203 /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */
204 .endif /* \el == 0 */
207 stp lr, x21, [sp, #S_LR]
210 * In order to be able to dump the contents of struct pt_regs at the
211 * time the exception was taken (in case we attempt to walk the call
212 * stack later), chain it together with the stack frames.
215 stp xzr, xzr, [sp, #S_STACKFRAME]
217 stp x29, x22, [sp, #S_STACKFRAME]
219 add x29, sp, #S_STACKFRAME
221 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
223 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
224 * EL0, there is no need to check the state of TTBR0_EL1 since
225 * accesses are always enabled.
226 * Note that the meaning of this bit differs from the ARMv8.1 PAN
227 * feature as all TTBR0_EL1 accesses are disabled, not just those to
230 alternative_if ARM64_HAS_PAN
231 b 1f // skip TTBR0 PAN
232 alternative_else_nop_endif
236 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID
237 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
238 b.eq 1f // TTBR0 access already disabled
239 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
242 __uaccess_ttbr0_disable x21
246 stp x22, x23, [sp, #S_PC]
248 /* Not in a syscall by default (el0_svc overwrites for real syscall) */
251 str w21, [sp, #S_SYSCALLNO]
255 * Set sp_el0 to current thread_info.
262 * Registers that may be useful after this macro is invoked:
266 * x23 - aborted PSTATE
270 .macro kernel_exit, el
274 /* Restore the task's original addr_limit. */
275 ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
276 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
278 /* No need to restore UAO, it will be restored from SPSR_EL1 */
281 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
286 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
288 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
291 alternative_if ARM64_HAS_PAN
292 b 2f // skip TTBR0 PAN
293 alternative_else_nop_endif
296 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
299 __uaccess_ttbr0_enable x0, x1
303 * Enable errata workarounds only if returning to user. The only
304 * workaround currently required for TTBR0_EL1 changes are for the
305 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
308 bl post_ttbr_update_workaround
312 and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
318 ldr x23, [sp, #S_SP] // load return stack pointer
320 tst x22, #PSR_MODE32_BIT // native task?
323 #ifdef CONFIG_ARM64_ERRATUM_845719
324 alternative_if ARM64_WORKAROUND_845719
325 #ifdef CONFIG_PID_IN_CONTEXTIDR
326 mrs x29, contextidr_el1
327 msr contextidr_el1, x29
329 msr contextidr_el1, xzr
331 alternative_else_nop_endif
334 apply_ssbd 0, 5f, x0, x1
338 msr elr_el1, x21 // set up the return data
340 ldp x0, x1, [sp, #16 * 0]
341 ldp x2, x3, [sp, #16 * 1]
342 ldp x4, x5, [sp, #16 * 2]
343 ldp x6, x7, [sp, #16 * 3]
344 ldp x8, x9, [sp, #16 * 4]
345 ldp x10, x11, [sp, #16 * 5]
346 ldp x12, x13, [sp, #16 * 6]
347 ldp x14, x15, [sp, #16 * 7]
348 ldp x16, x17, [sp, #16 * 8]
349 ldp x18, x19, [sp, #16 * 9]
350 ldp x20, x21, [sp, #16 * 10]
351 ldp x22, x23, [sp, #16 * 11]
352 ldp x24, x25, [sp, #16 * 12]
353 ldp x26, x27, [sp, #16 * 13]
354 ldp x28, x29, [sp, #16 * 14]
356 add sp, sp, #S_FRAME_SIZE // restore sp
359 alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
360 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
363 tramp_alias x30, tramp_exit_native
366 tramp_alias x30, tramp_exit_compat
374 .macro irq_stack_entry
375 mov x19, sp // preserve the original sp
378 * Compare sp with the base of the task stack.
379 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
380 * and should switch to the irq stack.
382 ldr x25, [tsk, TSK_STACK]
384 and x25, x25, #~(THREAD_SIZE - 1)
387 ldr_this_cpu x25, irq_stack_ptr, x26
388 mov x26, #IRQ_STACK_SIZE
391 /* switch to the irq stack */
397 * x19 should be preserved between irq_stack_entry and
400 .macro irq_stack_exit
405 * These are the registers used in the syscall handler, and allow us to
406 * have in theory up to 7 arguments to a function - x0 to x6.
408 * x7 is reserved for the system call number in 32-bit mode.
410 wsc_nr .req w25 // number of system calls
411 xsc_nr .req x25 // number of system calls (zero-extended)
412 wscno .req w26 // syscall number
413 xscno .req x26 // syscall number (zero-extended)
414 stbl .req x27 // syscall table pointer
415 tsk .req x28 // current thread_info
418 * Interrupt handling.
421 ldr_l x1, handle_arch_irq
433 .pushsection ".entry.text", "ax"
437 kernel_ventry 1, sync_invalid // Synchronous EL1t
438 kernel_ventry 1, irq_invalid // IRQ EL1t
439 kernel_ventry 1, fiq_invalid // FIQ EL1t
440 kernel_ventry 1, error_invalid // Error EL1t
442 kernel_ventry 1, sync // Synchronous EL1h
443 kernel_ventry 1, irq // IRQ EL1h
444 kernel_ventry 1, fiq_invalid // FIQ EL1h
445 kernel_ventry 1, error // Error EL1h
447 kernel_ventry 0, sync // Synchronous 64-bit EL0
448 kernel_ventry 0, irq // IRQ 64-bit EL0
449 kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0
450 kernel_ventry 0, error // Error 64-bit EL0
453 kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0
454 kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0
455 kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0
456 kernel_ventry 0, error_compat, 32 // Error 32-bit EL0
458 kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0
459 kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0
460 kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0
461 kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0
465 #ifdef CONFIG_VMAP_STACK
467 * We detected an overflow in kernel_ventry, which switched to the
468 * overflow stack. Stash the exception regs, and head to our overflow
472 /* Restore the original x0 value */
476 * Store the original GPRs to the new stack. The orginal SP (minus
477 * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry.
479 sub sp, sp, #S_FRAME_SIZE
482 add x0, x0, #S_FRAME_SIZE
485 /* Stash the regs for handle_bad_stack */
491 #endif /* CONFIG_VMAP_STACK */
494 * Invalid mode handlers
496 .macro inv_entry, el, reason, regsize = 64
497 kernel_entry \el, \regsize
506 inv_entry 0, BAD_SYNC
507 ENDPROC(el0_sync_invalid)
511 ENDPROC(el0_irq_invalid)
515 ENDPROC(el0_fiq_invalid)
518 inv_entry 0, BAD_ERROR
519 ENDPROC(el0_error_invalid)
522 el0_fiq_invalid_compat:
523 inv_entry 0, BAD_FIQ, 32
524 ENDPROC(el0_fiq_invalid_compat)
528 inv_entry 1, BAD_SYNC
529 ENDPROC(el1_sync_invalid)
533 ENDPROC(el1_irq_invalid)
537 ENDPROC(el1_fiq_invalid)
540 inv_entry 1, BAD_ERROR
541 ENDPROC(el1_error_invalid)
549 mrs x1, esr_el1 // read the syndrome register
550 lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
551 cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
553 cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1
555 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
557 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
559 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
561 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1
563 cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1
569 * Fall through to the Data abort case
573 * Data abort handling
576 inherit_daif pstate=x23, tmp=x2
577 clear_address_tag x0, x3
578 mov x2, sp // struct pt_regs
584 * Stack or PC alignment exception handling
587 inherit_daif pstate=x23, tmp=x2
593 * Undefined instruction
595 inherit_daif pstate=x23, tmp=x2
601 * Debug exception handling
603 cmp x24, #ESR_ELx_EC_BRK64 // if BRK64
604 cinc x24, x24, eq // set bit '0'
605 tbz x24, #0, el1_inv // EL1 only
607 mov x2, sp // struct pt_regs
608 bl do_debug_exception
611 // TODO: add support for undefined instructions in kernel mode
612 inherit_daif pstate=x23, tmp=x2
624 #ifdef CONFIG_TRACE_IRQFLAGS
625 bl trace_hardirqs_off
630 #ifdef CONFIG_PREEMPT
631 ldr w24, [tsk, #TSK_TI_PREEMPT] // get preempt count
632 cbnz w24, 1f // preempt count != 0
633 ldr x0, [tsk, #TSK_TI_FLAGS] // get flags
634 tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
638 #ifdef CONFIG_TRACE_IRQFLAGS
644 #ifdef CONFIG_PREEMPT
647 1: bl preempt_schedule_irq // irq en/disable is done inside
648 ldr x0, [tsk, #TSK_TI_FLAGS] // get new tasks TI_FLAGS
649 tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
659 mrs x25, esr_el1 // read the syndrome register
660 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
661 cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state
663 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
665 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
667 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
669 cmp x24, #ESR_ELx_EC_SVE // SVE access
671 cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception
673 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
675 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
677 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
679 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
681 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
689 mrs x25, esr_el1 // read the syndrome register
690 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
691 cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state
693 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
695 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
697 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
699 cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception
701 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
703 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
705 cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap
707 cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap
709 cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap
711 cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap
713 cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap
715 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
720 * AArch32 syscall handling
722 ldr x16, [tsk, #TSK_TI_FLAGS] // load thread flags
723 adrp stbl, compat_sys_call_table // load compat syscall table pointer
724 mov wscno, w7 // syscall number in w7 (r7)
725 mov wsc_nr, #__NR_compat_syscalls
740 * Data abort handling
745 clear_address_tag x0, x26
752 * Instruction abort handling
756 #ifdef CONFIG_TRACE_IRQFLAGS
757 bl trace_hardirqs_off
763 bl do_el0_ia_bp_hardening
767 * Floating Point or Advanced SIMD access
777 * Scalable Vector Extension access
787 * Floating Point, Advanced SIMD or SVE exception
797 * Stack or PC alignment exception handling
801 #ifdef CONFIG_TRACE_IRQFLAGS
802 bl trace_hardirqs_off
812 * Undefined instruction
821 * System instructions, for trapped cache maintenance instructions
831 * Debug exception handling
833 tbnz x24, #0, el0_inv // EL0 only
837 bl do_debug_exception
856 #ifdef CONFIG_TRACE_IRQFLAGS
857 bl trace_hardirqs_off
861 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
863 bl do_el0_irq_bp_hardening
868 #ifdef CONFIG_TRACE_IRQFLAGS
897 * This is the fast syscall return path. We do as little as possible here,
898 * and this includes saving x0 back into the kernel stack.
902 str x0, [sp, #S_X0] // returned x0
903 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for syscall tracing
904 and x2, x1, #_TIF_SYSCALL_WORK
905 cbnz x2, ret_fast_syscall_trace
906 and x2, x1, #_TIF_WORK_MASK
907 cbnz x2, work_pending
908 enable_step_tsk x1, x2
910 ret_fast_syscall_trace:
912 b __sys_trace_return_skipped // we already saved x0
915 * Ok, we need to do extra processing, enter the slow path.
920 #ifdef CONFIG_TRACE_IRQFLAGS
921 bl trace_hardirqs_on // enabled while in userspace
923 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step
926 * "slow" syscall return path.
930 ldr x1, [tsk, #TSK_TI_FLAGS]
931 and x2, x1, #_TIF_WORK_MASK
932 cbnz x2, work_pending
934 enable_step_tsk x1, x2
943 ldr x16, [tsk, #TSK_TI_FLAGS] // load thread flags
944 adrp stbl, sys_call_table // load syscall table pointer
945 mov wscno, w8 // syscall number in w8
946 mov wsc_nr, #__NR_syscalls
948 #ifdef CONFIG_ARM64_SVE
949 alternative_if_not ARM64_SVE
951 alternative_else_nop_endif
952 tbz x16, #TIF_SVE, el0_svc_naked // Skip unless TIF_SVE set:
953 bic x16, x16, #_TIF_SVE // discard SVE state
954 str x16, [tsk, #TSK_TI_FLAGS]
957 * task_fpsimd_load() won't be called to update CPACR_EL1 in
958 * ret_to_user unless TIF_FOREIGN_FPSTATE is still set, which only
959 * happens if a context switch or kernel_neon_begin() or context
960 * modification (sigreturn, ptrace) intervenes.
961 * So, ensure that CPACR_EL1 is already correct for the fast-path case:
964 bic x9, x9, #CPACR_EL1_ZEN_EL0EN // disable SVE for el0
965 msr cpacr_el1, x9 // synchronised by eret to el0
968 el0_svc_naked: // compat entry point
969 stp x0, xscno, [sp, #S_ORIG_X0] // save the original x0 and syscall number
973 tst x16, #_TIF_SYSCALL_WORK // check for syscall hooks
975 cmp wscno, wsc_nr // check upper syscall limit
977 mask_nospec64 xscno, xsc_nr, x19 // enforce bounds for syscall number
978 ldr x16, [stbl, xscno, lsl #3] // address in the syscall table
979 blr x16 // call sys_* routine
988 * This is the really slow path. We're going to be doing context
989 * switches, and waiting for our parent to respond.
992 cmp wscno, #NO_SYSCALL // user-issued syscall(-1)?
994 mov x0, #-ENOSYS // set default errno if so
997 bl syscall_trace_enter
998 cmp w0, #NO_SYSCALL // skip the syscall?
999 b.eq __sys_trace_return_skipped
1000 mov wscno, w0 // syscall number (possibly new)
1001 mov x1, sp // pointer to regs
1002 cmp wscno, wsc_nr // check upper syscall limit
1004 ldp x0, x1, [sp] // restore the syscall args
1005 ldp x2, x3, [sp, #S_X2]
1006 ldp x4, x5, [sp, #S_X4]
1007 ldp x6, x7, [sp, #S_X6]
1008 ldr x16, [stbl, xscno, lsl #3] // address in the syscall table
1009 blr x16 // call sys_* routine
1012 str x0, [sp, #S_X0] // save returned x0
1013 __sys_trace_return_skipped:
1015 bl syscall_trace_exit
1021 b __sys_trace_return
1023 .popsection // .entry.text
1025 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1027 * Exception vectors trampoline.
1029 .pushsection ".entry.tramp.text", "ax"
1031 .macro tramp_map_kernel, tmp
1033 sub \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
1034 bic \tmp, \tmp, #USER_ASID_FLAG
1036 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
1037 alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
1038 /* ASID already in \tmp[63:48] */
1039 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12)
1040 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12)
1041 /* 2MB boundary containing the vectors, so we nobble the walk cache */
1042 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
1046 alternative_else_nop_endif
1047 #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */
1050 .macro tramp_unmap_kernel, tmp
1052 add \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
1053 orr \tmp, \tmp, #USER_ASID_FLAG
1056 * We avoid running the post_ttbr_update_workaround here because
1057 * it's only needed by Cavium ThunderX, which requires KPTI to be
1062 .macro tramp_ventry, regsize = 64
1066 msr tpidrro_el0, x30 // Restored in kernel_ventry
1069 * Defend against branch aliasing attacks by pushing a dummy
1070 * entry onto the return stack and using a RET instruction to
1071 * enter the full-fat kernel vectors.
1076 tramp_map_kernel x30
1077 #ifdef CONFIG_RANDOMIZE_BASE
1078 adr x30, tramp_vectors + PAGE_SIZE
1079 alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
1084 prfm plil1strm, [x30, #(1b - tramp_vectors)]
1086 add x30, x30, #(1b - tramp_vectors)
1091 .macro tramp_exit, regsize = 64
1092 adr x30, tramp_vectors
1094 tramp_unmap_kernel x30
1102 ENTRY(tramp_vectors)
1116 ENTRY(tramp_exit_native)
1118 END(tramp_exit_native)
1120 ENTRY(tramp_exit_compat)
1122 END(tramp_exit_compat)
1125 .popsection // .entry.tramp.text
1126 #ifdef CONFIG_RANDOMIZE_BASE
1127 .pushsection ".rodata", "a"
1129 .globl __entry_tramp_data_start
1130 __entry_tramp_data_start:
1132 .popsection // .rodata
1133 #endif /* CONFIG_RANDOMIZE_BASE */
1134 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1137 * Special system call wrappers.
1139 ENTRY(sys_rt_sigreturn_wrapper)
1142 ENDPROC(sys_rt_sigreturn_wrapper)
1145 * Register switch for AArch64. The callee-saved registers need to be saved
1146 * and restored. On entry:
1147 * x0 = previous task_struct (must be preserved across the switch)
1148 * x1 = next task_struct
1149 * Previous and next are guaranteed not to be the same.
1152 ENTRY(cpu_switch_to)
1153 mov x10, #THREAD_CPU_CONTEXT
1156 stp x19, x20, [x8], #16 // store callee-saved registers
1157 stp x21, x22, [x8], #16
1158 stp x23, x24, [x8], #16
1159 stp x25, x26, [x8], #16
1160 stp x27, x28, [x8], #16
1161 stp x29, x9, [x8], #16
1164 ldp x19, x20, [x8], #16 // restore callee-saved registers
1165 ldp x21, x22, [x8], #16
1166 ldp x23, x24, [x8], #16
1167 ldp x25, x26, [x8], #16
1168 ldp x27, x28, [x8], #16
1169 ldp x29, x9, [x8], #16
1174 ENDPROC(cpu_switch_to)
1175 NOKPROBE(cpu_switch_to)
1178 * This is how we return from a fork.
1180 ENTRY(ret_from_fork)
1182 cbz x19, 1f // not a kernel thread
1185 1: get_thread_info tsk
1187 ENDPROC(ret_from_fork)
1188 NOKPROBE(ret_from_fork)
1190 #ifdef CONFIG_ARM_SDE_INTERFACE
1192 #include <asm/sdei.h>
1193 #include <uapi/linux/arm_sdei.h>
1195 .macro sdei_handler_exit exit_mode
1196 /* On success, this call never returns... */
1197 cmp \exit_mode, #SDEI_EXIT_SMC
1205 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1207 * The regular SDEI entry point may have been unmapped along with the rest of
1208 * the kernel. This trampoline restores the kernel mapping to make the x1 memory
1209 * argument accessible.
1211 * This clobbers x4, __sdei_handler() will restore this from firmware's
1215 .pushsection ".entry.tramp.text", "ax"
1216 ENTRY(__sdei_asm_entry_trampoline)
1218 tbz x4, #USER_ASID_BIT, 1f
1220 tramp_map_kernel tmp=x4
1225 * Use reg->interrupted_regs.addr_limit to remember whether to unmap
1226 * the kernel on exit.
1228 1: str x4, [x1, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)]
1230 #ifdef CONFIG_RANDOMIZE_BASE
1231 adr x4, tramp_vectors + PAGE_SIZE
1232 add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler
1235 ldr x4, =__sdei_asm_handler
1238 ENDPROC(__sdei_asm_entry_trampoline)
1239 NOKPROBE(__sdei_asm_entry_trampoline)
1242 * Make the exit call and restore the original ttbr1_el1
1244 * x0 & x1: setup for the exit API call
1246 * x4: struct sdei_registered_event argument from registration time.
1248 ENTRY(__sdei_asm_exit_trampoline)
1249 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)]
1252 tramp_unmap_kernel tmp=x4
1254 1: sdei_handler_exit exit_mode=x2
1255 ENDPROC(__sdei_asm_exit_trampoline)
1256 NOKPROBE(__sdei_asm_exit_trampoline)
1258 .popsection // .entry.tramp.text
1259 #ifdef CONFIG_RANDOMIZE_BASE
1260 .pushsection ".rodata", "a"
1261 __sdei_asm_trampoline_next_handler:
1262 .quad __sdei_asm_handler
1263 .popsection // .rodata
1264 #endif /* CONFIG_RANDOMIZE_BASE */
1265 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1268 * Software Delegated Exception entry point.
1271 * x1: struct sdei_registered_event argument from registration time.
1272 * x2: interrupted PC
1273 * x3: interrupted PSTATE
1274 * x4: maybe clobbered by the trampoline
1276 * Firmware has preserved x0->x17 for us, we must save/restore the rest to
1277 * follow SMC-CC. We save (or retrieve) all the registers as the handler may
1280 ENTRY(__sdei_asm_handler)
1281 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC]
1282 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2]
1283 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3]
1284 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4]
1285 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5]
1286 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6]
1287 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7]
1288 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8]
1289 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9]
1290 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]
1291 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11]
1292 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12]
1293 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13]
1294 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
1296 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR]
1300 #ifdef CONFIG_VMAP_STACK
1302 * entry.S may have been using sp as a scratch register, find whether
1303 * this is a normal or critical event and switch to the appropriate
1304 * stack for this CPU.
1306 ldrb w4, [x19, #SDEI_EVENT_PRIORITY]
1308 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6
1310 1: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6
1311 2: mov x6, #SDEI_STACK_SIZE
1317 * We may have interrupted userspace, or a guest, or exit-from or
1318 * return-to either of these. We can't trust sp_el0, restore it.
1321 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1
1324 /* If we interrupted the kernel point to the previous stack/frame. */
1328 csel x29, x29, xzr, eq // fp, or zero
1329 csel x4, x2, xzr, eq // elr, or zero
1331 stp x29, x4, [sp, #-16]!
1334 add x0, x19, #SDEI_EVENT_INTREGS
1339 /* restore regs >x17 that we clobbered */
1340 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline
1341 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]
1342 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9]
1343 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR]
1346 mov x1, x0 // address to complete_and_resume
1347 /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */
1349 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE
1350 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME
1353 ldr_l x2, sdei_exit_mode
1355 alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
1356 sdei_handler_exit exit_mode=x2
1357 alternative_else_nop_endif
1359 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1360 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline
1363 ENDPROC(__sdei_asm_handler)
1364 NOKPROBE(__sdei_asm_handler)
1365 #endif /* CONFIG_ARM_SDE_INTERFACE */