2 * Low-level CPU initialisation
3 * Based on arch/arm/kernel/head.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2012 ARM Ltd.
7 * Authors: Catalin Marinas <catalin.marinas@arm.com>
8 * Will Deacon <will.deacon@arm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <linux/irqchip/arm-gic-v3.h>
27 #include <asm/assembler.h>
28 #include <asm/ptrace.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/cache.h>
31 #include <asm/cputype.h>
32 #include <asm/memory.h>
33 #include <asm/thread_info.h>
34 #include <asm/pgtable-hwdef.h>
35 #include <asm/pgtable.h>
40 * swapper_pg_dir is the virtual address of the initial page table. We place
41 * the page tables 3 * PAGE_SIZE below KERNEL_RAM_VADDR. The idmap_pg_dir has
42 * 2 pages and is placed below swapper_pg_dir.
44 #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
46 #if (KERNEL_RAM_VADDR & 0xfffff) != 0x80000
47 #error KERNEL_RAM_VADDR must start at 0xXXX80000
50 #define SWAPPER_DIR_SIZE (3 * PAGE_SIZE)
51 #define IDMAP_DIR_SIZE (2 * PAGE_SIZE)
54 .equ swapper_pg_dir, KERNEL_RAM_VADDR - SWAPPER_DIR_SIZE
57 .equ idmap_pg_dir, swapper_pg_dir - IDMAP_DIR_SIZE
59 .macro pgtbl, ttb0, ttb1, phys
60 add \ttb1, \phys, #TEXT_OFFSET - SWAPPER_DIR_SIZE
61 sub \ttb0, \ttb1, #IDMAP_DIR_SIZE
64 #ifdef CONFIG_ARM64_64K_PAGES
65 #define BLOCK_SHIFT PAGE_SHIFT
66 #define BLOCK_SIZE PAGE_SIZE
68 #define BLOCK_SHIFT SECTION_SHIFT
69 #define BLOCK_SIZE SECTION_SIZE
72 #define KERNEL_START KERNEL_RAM_VADDR
73 #define KERNEL_END _end
76 * Initial memory map attributes.
79 #define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF
80 #define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF
82 #define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF | PTE_SHARED
83 #define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S
86 #ifdef CONFIG_ARM64_64K_PAGES
87 #define MM_MMUFLAGS PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS
89 #define MM_MMUFLAGS PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS
93 * Kernel startup entry point.
94 * ---------------------------
96 * The requirements are:
97 * MMU = off, D-cache = off, I-cache = on or off,
98 * x0 = physical address to the FDT blob.
100 * This code is mostly position independent so you call this at
101 * __pa(PAGE_OFFSET + TEXT_OFFSET).
103 * Note that the callee-saved registers are used for storing variables
104 * that are useful before the MMU is enabled. The allocations are described
105 * in the entry routines.
110 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
115 * This add instruction has no meaningful effect except that
116 * its opcode forms the magic "MZ" signature required by UEFI.
121 b stext // branch to kernel start, magic
124 .quad TEXT_OFFSET // Image load offset from start of RAM
130 .byte 0x41 // Magic number, "ARM\x64"
135 .long pe_header - efi_head // Offset to the PE header.
146 .short 0xaa64 // AArch64
147 .short 2 // nr_sections
148 .long 0 // TimeDateStamp
149 .long 0 // PointerToSymbolTable
150 .long 1 // NumberOfSymbols
151 .short section_table - optional_header // SizeOfOptionalHeader
152 .short 0x206 // Characteristics.
153 // IMAGE_FILE_DEBUG_STRIPPED |
154 // IMAGE_FILE_EXECUTABLE_IMAGE |
155 // IMAGE_FILE_LINE_NUMS_STRIPPED
157 .short 0x20b // PE32+ format
158 .byte 0x02 // MajorLinkerVersion
159 .byte 0x14 // MinorLinkerVersion
160 .long _edata - stext // SizeOfCode
161 .long 0 // SizeOfInitializedData
162 .long 0 // SizeOfUninitializedData
163 .long efi_stub_entry - efi_head // AddressOfEntryPoint
164 .long stext - efi_head // BaseOfCode
168 .long 0x20 // SectionAlignment
169 .long 0x8 // FileAlignment
170 .short 0 // MajorOperatingSystemVersion
171 .short 0 // MinorOperatingSystemVersion
172 .short 0 // MajorImageVersion
173 .short 0 // MinorImageVersion
174 .short 0 // MajorSubsystemVersion
175 .short 0 // MinorSubsystemVersion
176 .long 0 // Win32VersionValue
178 .long _edata - efi_head // SizeOfImage
180 // Everything before the kernel image is considered part of the header
181 .long stext - efi_head // SizeOfHeaders
183 .short 0xa // Subsystem (EFI application)
184 .short 0 // DllCharacteristics
185 .quad 0 // SizeOfStackReserve
186 .quad 0 // SizeOfStackCommit
187 .quad 0 // SizeOfHeapReserve
188 .quad 0 // SizeOfHeapCommit
189 .long 0 // LoaderFlags
190 .long 0x6 // NumberOfRvaAndSizes
192 .quad 0 // ExportTable
193 .quad 0 // ImportTable
194 .quad 0 // ResourceTable
195 .quad 0 // ExceptionTable
196 .quad 0 // CertificationTable
197 .quad 0 // BaseRelocationTable
203 * The EFI application loader requires a relocation section
204 * because EFI applications must be relocatable. This is a
205 * dummy section as far as we are concerned.
209 .byte 0 // end of 0 padding of section name
212 .long 0 // SizeOfRawData
213 .long 0 // PointerToRawData
214 .long 0 // PointerToRelocations
215 .long 0 // PointerToLineNumbers
216 .short 0 // NumberOfRelocations
217 .short 0 // NumberOfLineNumbers
218 .long 0x42100040 // Characteristics (section flags)
224 .byte 0 // end of 0 padding of section name
225 .long _edata - stext // VirtualSize
226 .long stext - efi_head // VirtualAddress
227 .long _edata - stext // SizeOfRawData
228 .long stext - efi_head // PointerToRawData
230 .long 0 // PointerToRelocations (0 for executables)
231 .long 0 // PointerToLineNumbers (0 for executables)
232 .short 0 // NumberOfRelocations (0 for executables)
233 .short 0 // NumberOfLineNumbers (0 for executables)
234 .long 0xe0500020 // Characteristics (section flags)
239 mov x21, x0 // x21=FDT
240 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
241 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
242 bl set_cpu_boot_mode_flag
243 mrs x22, midr_el1 // x22=cpuid
245 bl lookup_processor_type
246 mov x23, x0 // x23=current cpu_table
247 cbz x23, __error_p // invalid processor (x23=0)?
249 bl __create_page_tables // x25=TTBR0, x26=TTBR1
251 * The following calls CPU specific code in a position independent
252 * manner. See arch/arm64/mm/proc.S for details. x23 = base of
253 * cpu_info structure selected by lookup_processor_type above.
254 * On return, the CPU will be ready for the MMU to be turned on and
255 * the TCR will have been set.
257 ldr x27, __switch_data // address to jump to after
258 // MMU has been enabled
259 adr lr, __enable_mmu // return (PIC) address
260 ldr x12, [x23, #CPU_INFO_SETUP]
261 add x12, x12, x28 // __virt_to_phys
262 br x12 // initialise processor
266 * If we're fortunate enough to boot at EL2, ensure that the world is
267 * sane before dropping to EL1.
269 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if
270 * booted in EL1 or EL2 respectively.
274 cmp x0, #PSR_MODE_EL2t
275 ccmp x0, #PSR_MODE_EL2h, #0x4, ne
278 CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2
279 CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2
283 CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1
284 CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
286 mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
290 /* Hyp configuration. */
291 2: mov x0, #(1 << 31) // 64-bit EL1
294 /* Generic timers. */
296 orr x0, x0, #3 // Enable EL1 physical timers
298 msr cntvoff_el2, xzr // Clear virtual offset
300 #ifdef CONFIG_ARM_GIC_V3
301 /* GICv3 system register access */
302 mrs x0, id_aa64pfr0_el1
308 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
309 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
311 isb // Make sure SRE is now set
312 msr ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
317 /* Populate ID registers. */
324 mov x0, #0x0800 // Set/clear RES{1,0} bits
325 CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems
326 CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
329 /* Coprocessor traps. */
331 msr cptr_el2, x0 // Disable copro. traps to EL2
334 msr hstr_el2, xzr // Disable CP15 traps to EL2
337 /* Stage-2 translation */
340 /* Hypervisor stub */
341 adr x0, __hyp_stub_vectors
345 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
349 mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
354 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
355 * in x20. See arch/arm64/include/asm/virt.h for more info.
357 ENTRY(set_cpu_boot_mode_flag)
358 ldr x1, =__boot_cpu_mode // Compute __boot_cpu_mode
360 cmp w20, #BOOT_CPU_MODE_EL2
363 1: str w20, [x1] // This CPU has booted in EL1
365 dc ivac, x1 // Invalidate potentially stale cache line
367 ENDPROC(set_cpu_boot_mode_flag)
370 * We need to find out the CPU boot mode long after boot, so we need to
371 * store it in a writable variable.
373 * This is not in .bss, because we set it sufficiently early that the boot-time
374 * zeroing of .bss would clobber it.
376 .pushsection .data..cacheline_aligned
377 ENTRY(__boot_cpu_mode)
378 .align L1_CACHE_SHIFT
379 .long BOOT_CPU_MODE_EL2
390 .quad secondary_holding_pen_release
393 * This provides a "holding pen" for platforms to hold all secondary
394 * cores are held until we're ready for them to initialise.
396 ENTRY(secondary_holding_pen)
397 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
398 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
399 bl set_cpu_boot_mode_flag
401 ldr x1, =MPIDR_HWID_BITMASK
409 b.eq secondary_startup
412 ENDPROC(secondary_holding_pen)
415 * Secondary entry point that jumps straight into the kernel. Only to
416 * be used where CPUs are brought online dynamically by the kernel.
418 ENTRY(secondary_entry)
419 bl el2_setup // Drop to EL1
420 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
421 bl set_cpu_boot_mode_flag
423 ENDPROC(secondary_entry)
425 ENTRY(secondary_startup)
427 * Common entry point for secondary CPUs.
429 mrs x22, midr_el1 // x22=cpuid
431 bl lookup_processor_type
432 mov x23, x0 // x23=current cpu_table
433 cbz x23, __error_p // invalid processor (x23=0)?
435 pgtbl x25, x26, x24 // x25=TTBR0, x26=TTBR1
436 ldr x12, [x23, #CPU_INFO_SETUP]
437 add x12, x12, x28 // __virt_to_phys
438 blr x12 // initialise processor
440 ldr x21, =secondary_data
441 ldr x27, =__secondary_switched // address to jump to after enabling the MMU
443 ENDPROC(secondary_startup)
445 ENTRY(__secondary_switched)
446 ldr x0, [x21] // get secondary_data.stack
449 b secondary_start_kernel
450 ENDPROC(__secondary_switched)
451 #endif /* CONFIG_SMP */
454 * Setup common bits before finally enabling the MMU. Essentially this is just
455 * loading the page table pointer and vector base registers.
457 * On entry to this code, x0 must contain the SCTLR_EL1 value for turning on
463 msr ttbr0_el1, x25 // load TTBR0
464 msr ttbr1_el1, x26 // load TTBR1
467 ENDPROC(__enable_mmu)
470 * Enable the MMU. This completely changes the structure of the visible memory
471 * space. You will not be able to trace execution through this.
473 * x0 = system control register
474 * x27 = *virtual* address to jump to upon completion
476 * other registers depend on the function called upon completion
483 ENDPROC(__turn_mmu_on)
486 * Calculate the start of physical memory.
491 sub x28, x0, x1 // x28 = PHYS_OFFSET - PAGE_OFFSET
492 add x24, x2, x28 // x24 = PHYS_OFFSET
494 ENDPROC(__calc_phys_offset)
501 * Macro to populate the PGD for the corresponding block entry in the next
502 * level (tbl) for the given virtual address.
504 * Preserves: pgd, tbl, virt
505 * Corrupts: tmp1, tmp2
507 .macro create_pgd_entry, pgd, tbl, virt, tmp1, tmp2
508 lsr \tmp1, \virt, #PGDIR_SHIFT
509 and \tmp1, \tmp1, #PTRS_PER_PGD - 1 // PGD index
510 orr \tmp2, \tbl, #3 // PGD entry table type
511 str \tmp2, [\pgd, \tmp1, lsl #3]
515 * Macro to populate block entries in the page table for the start..end
516 * virtual range (inclusive).
518 * Preserves: tbl, flags
519 * Corrupts: phys, start, end, pstate
521 .macro create_block_map, tbl, flags, phys, start, end
522 lsr \phys, \phys, #BLOCK_SHIFT
523 lsr \start, \start, #BLOCK_SHIFT
524 and \start, \start, #PTRS_PER_PTE - 1 // table index
525 orr \phys, \flags, \phys, lsl #BLOCK_SHIFT // table entry
526 lsr \end, \end, #BLOCK_SHIFT
527 and \end, \end, #PTRS_PER_PTE - 1 // table end index
528 9999: str \phys, [\tbl, \start, lsl #3] // store the entry
529 add \start, \start, #1 // next entry
530 add \phys, \phys, #BLOCK_SIZE // next block
536 * Setup the initial page tables. We only setup the barest amount which is
537 * required to get the kernel running. The following sections are required:
538 * - identity mapping to enable the MMU (low address, TTBR0)
539 * - first few MB of the kernel linear mapping to jump to once the MMU has
540 * been enabled, including the FDT blob (TTBR1)
541 * - pgd entry for fixed mappings (TTBR1)
543 __create_page_tables:
544 pgtbl x25, x26, x24 // idmap_pg_dir and swapper_pg_dir addresses
548 * Invalidate the idmap and swapper page tables to avoid potential
549 * dirty cache lines being evicted.
552 add x1, x26, #SWAPPER_DIR_SIZE
553 bl __inval_cache_range
556 * Clear the idmap and swapper page tables.
559 add x6, x26, #SWAPPER_DIR_SIZE
560 1: stp xzr, xzr, [x0], #16
561 stp xzr, xzr, [x0], #16
562 stp xzr, xzr, [x0], #16
563 stp xzr, xzr, [x0], #16
570 * Create the identity mapping.
572 add x0, x25, #PAGE_SIZE // section table address
573 ldr x3, =KERNEL_START
574 add x3, x3, x28 // __pa(KERNEL_START)
575 create_pgd_entry x25, x0, x3, x5, x6
577 mov x5, x3 // __pa(KERNEL_START)
578 add x6, x6, x28 // __pa(KERNEL_END)
579 create_block_map x0, x7, x3, x5, x6
582 * Map the kernel image (starting with PHYS_OFFSET).
584 add x0, x26, #PAGE_SIZE // section table address
586 create_pgd_entry x26, x0, x5, x3, x6
588 mov x3, x24 // phys offset
589 create_block_map x0, x7, x3, x5, x6
592 * Map the FDT blob (maximum 2MB; must be within 512MB of
595 mov x3, x21 // FDT phys address
596 and x3, x3, #~((1 << 21) - 1) // 2MB aligned
598 sub x5, x3, x24 // subtract PHYS_OFFSET
599 tst x5, #~((1 << 29) - 1) // within 512MB?
600 csel x21, xzr, x21, ne // zero the FDT pointer
602 add x5, x5, x6 // __va(FDT blob)
603 add x6, x5, #1 << 21 // 2MB for the FDT blob
604 sub x6, x6, #1 // inclusive range
605 create_block_map x0, x7, x3, x5, x6
608 * Create the pgd entry for the fixed mappings.
610 ldr x5, =FIXADDR_TOP // Fixed mapping virtual address
611 add x0, x26, #2 * PAGE_SIZE // section table address
612 create_pgd_entry x26, x0, x5, x6, x7
615 * Since the page tables have been populated with non-cacheable
616 * accesses (MMU disabled), invalidate the idmap and swapper page
617 * tables again to remove any speculatively loaded cache lines.
620 add x1, x26, #SWAPPER_DIR_SIZE
621 bl __inval_cache_range
625 ENDPROC(__create_page_tables)
629 .type __switch_data, %object
631 .quad __mmap_switched
632 .quad __bss_start // x6
634 .quad processor_id // x4
635 .quad __fdt_pointer // x5
636 .quad memstart_addr // x6
637 .quad init_thread_union + THREAD_START_SP // sp
640 * The following fragment of code is executed with the MMU on in MMU mode, and
641 * uses absolute addresses; this is not position independent.
644 adr x3, __switch_data + 8
646 ldp x6, x7, [x3], #16
649 str xzr, [x6], #8 // Clear BSS
652 ldp x4, x5, [x3], #16
656 str x22, [x4] // Save processor ID
657 str x21, [x5] // Save FDT pointer
658 str x24, [x6] // Save PHYS_OFFSET
661 ENDPROC(__mmap_switched)
664 * Exception handling. Something went wrong and we can't proceed. We ought to
665 * tell the user, but since we don't have any guarantee that we're even
666 * running on the right architecture, we do virtually nothing.
677 * This function gets the processor ID in w0 and searches the cpu_table[] for
678 * a match. It returns a pointer to the struct cpu_info it found. The
679 * cpu_table[] must end with an empty (all zeros) structure.
681 * This routine can be called via C code and it needs to work with the MMU
682 * both disabled and enabled (the offset is calculated automatically).
684 ENTRY(lookup_processor_type)
685 adr x1, __lookup_processor_type_data
687 sub x1, x1, x2 // get offset between VA and PA
688 add x3, x3, x1 // convert VA to PA
690 ldp w5, w6, [x3] // load cpu_id_val and cpu_id_mask
691 cbz w5, 2f // end of list?
695 add x3, x3, #CPU_INFO_SZ
698 mov x3, #0 // unknown processor
702 ENDPROC(lookup_processor_type)
705 .type __lookup_processor_type_data, %object
706 __lookup_processor_type_data:
709 .size __lookup_processor_type_data, . - __lookup_processor_type_data
712 * Determine validity of the x21 FDT pointer.
713 * The dtb must be 8-byte aligned and live in the first 512M of memory.