2 * Low-level CPU initialisation
3 * Based on arch/arm/kernel/head.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2012 ARM Ltd.
7 * Authors: Catalin Marinas <catalin.marinas@arm.com>
8 * Will Deacon <will.deacon@arm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <linux/irqchip/arm-gic-v3.h>
27 #include <asm/assembler.h>
29 #include <asm/ptrace.h>
30 #include <asm/asm-offsets.h>
31 #include <asm/cache.h>
32 #include <asm/cputype.h>
34 #include <asm/kernel-pgtable.h>
35 #include <asm/kvm_arm.h>
36 #include <asm/memory.h>
37 #include <asm/pgtable-hwdef.h>
38 #include <asm/pgtable.h>
41 #include <asm/sysreg.h>
42 #include <asm/thread_info.h>
45 #include "efi-header.S"
47 #define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET)
49 #if (TEXT_OFFSET & 0xfff) != 0
50 #error TEXT_OFFSET must be at least 4KB aligned
51 #elif (PAGE_OFFSET & 0x1fffff) != 0
52 #error PAGE_OFFSET must be at least 2MB aligned
53 #elif TEXT_OFFSET > 0x1fffff
54 #error TEXT_OFFSET must be less than 2MB
58 * Kernel startup entry point.
59 * ---------------------------
61 * The requirements are:
62 * MMU = off, D-cache = off, I-cache = on or off,
63 * x0 = physical address to the FDT blob.
65 * This code is mostly position independent so you call this at
66 * __pa(PAGE_OFFSET + TEXT_OFFSET).
68 * Note that the callee-saved registers are used for storing variables
69 * that are useful before the MMU is enabled. The allocations are described
70 * in the entry routines.
75 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
79 * This add instruction has no meaningful effect except that
80 * its opcode forms the magic "MZ" signature required by UEFI.
85 b stext // branch to kernel start, magic
88 le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian
89 le64sym _kernel_size_le // Effective size of kernel image, little-endian
90 le64sym _kernel_flags_le // Informative flags, little-endian
94 .ascii "ARM\x64" // Magic number
96 .long pe_header - _head // Offset to the PE header.
107 * The following callee saved general purpose registers are used on the
108 * primary lowlevel boot path:
110 * Register Scope Purpose
111 * x21 stext() .. start_kernel() FDT pointer passed at boot in x0
112 * x23 stext() .. start_kernel() physical misalignment/KASLR offset
113 * x28 __create_page_tables() callee preserved temp register
114 * x19/x20 __primary_switch() callee preserved temp registers
117 bl preserve_boot_args
118 bl el2_setup // Drop to EL1, w0=cpu_boot_mode
119 adrp x23, __PHYS_OFFSET
120 and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0
121 bl set_cpu_boot_mode_flag
122 bl __create_page_tables
124 * The following calls CPU setup code, see arch/arm64/mm/proc.S for
126 * On return, the CPU will be ready for the MMU to be turned on and
127 * the TCR will have been set.
129 bl __cpu_setup // initialise processor
134 * Preserve the arguments passed by the bootloader in x0 .. x3
137 mov x21, x0 // x21=FDT
139 adr_l x0, boot_args // record the contents of
140 stp x21, x1, [x0] // x0 .. x3 at kernel entry
141 stp x2, x3, [x0, #16]
143 dmb sy // needed before dc ivac with
146 add x1, x0, #0x20 // 4 x 8 bytes
147 b __inval_cache_range // tail call
148 ENDPROC(preserve_boot_args)
151 * Macro to create a table entry to the next page.
153 * tbl: page table address
154 * virt: virtual address
155 * shift: #imm page table shift
156 * ptrs: #imm pointers per table page
159 * Corrupts: tmp1, tmp2
160 * Returns: tbl -> next level table page address
162 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
163 lsr \tmp1, \virt, #\shift
164 and \tmp1, \tmp1, #\ptrs - 1 // table index
165 add \tmp2, \tbl, #PAGE_SIZE
166 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type
167 str \tmp2, [\tbl, \tmp1, lsl #3]
168 add \tbl, \tbl, #PAGE_SIZE // next level table page
172 * Macro to populate the PGD (and possibily PUD) for the corresponding
173 * block entry in the next level (tbl) for the given virtual address.
175 * Preserves: tbl, next, virt
176 * Corrupts: tmp1, tmp2
178 .macro create_pgd_entry, tbl, virt, tmp1, tmp2
179 create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2
180 #if SWAPPER_PGTABLE_LEVELS > 3
181 create_table_entry \tbl, \virt, PUD_SHIFT, PTRS_PER_PUD, \tmp1, \tmp2
183 #if SWAPPER_PGTABLE_LEVELS > 2
184 create_table_entry \tbl, \virt, SWAPPER_TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2
189 * Macro to populate block entries in the page table for the start..end
190 * virtual range (inclusive).
192 * Preserves: tbl, flags
193 * Corrupts: phys, start, end, pstate
195 .macro create_block_map, tbl, flags, phys, start, end
196 lsr \phys, \phys, #SWAPPER_BLOCK_SHIFT
197 lsr \start, \start, #SWAPPER_BLOCK_SHIFT
198 and \start, \start, #PTRS_PER_PTE - 1 // table index
199 orr \phys, \flags, \phys, lsl #SWAPPER_BLOCK_SHIFT // table entry
200 lsr \end, \end, #SWAPPER_BLOCK_SHIFT
201 and \end, \end, #PTRS_PER_PTE - 1 // table end index
202 9999: str \phys, [\tbl, \start, lsl #3] // store the entry
203 add \start, \start, #1 // next entry
204 add \phys, \phys, #SWAPPER_BLOCK_SIZE // next block
210 * Setup the initial page tables. We only setup the barest amount which is
211 * required to get the kernel running. The following sections are required:
212 * - identity mapping to enable the MMU (low address, TTBR0)
213 * - first few MB of the kernel linear mapping to jump to once the MMU has
216 __create_page_tables:
220 * Invalidate the idmap and swapper page tables to avoid potential
221 * dirty cache lines being evicted.
223 adrp x0, idmap_pg_dir
224 adrp x1, swapper_pg_dir + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE
225 bl __inval_cache_range
228 * Clear the idmap and swapper page tables.
230 adrp x0, idmap_pg_dir
231 adrp x6, swapper_pg_dir + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE
232 1: stp xzr, xzr, [x0], #16
233 stp xzr, xzr, [x0], #16
234 stp xzr, xzr, [x0], #16
235 stp xzr, xzr, [x0], #16
239 mov x7, SWAPPER_MM_MMUFLAGS
242 * Create the identity mapping.
244 adrp x0, idmap_pg_dir
245 adrp x3, __idmap_text_start // __pa(__idmap_text_start)
247 #ifndef CONFIG_ARM64_VA_BITS_48
248 #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3)
249 #define EXTRA_PTRS (1 << (48 - EXTRA_SHIFT))
252 * If VA_BITS < 48, it may be too small to allow for an ID mapping to be
253 * created that covers system RAM if that is located sufficiently high
254 * in the physical address space. So for the ID map, use an extended
255 * virtual range in that case, by configuring an additional translation
257 * First, we have to verify our assumption that the current value of
258 * VA_BITS was chosen such that all translation levels are fully
259 * utilised, and that lowering T0SZ will always result in an additional
260 * translation level to be configured.
262 #if VA_BITS != EXTRA_SHIFT
263 #error "Mismatch between VA_BITS and page size/number of translation levels"
267 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the
268 * entire ID map region can be mapped. As T0SZ == (64 - #bits used),
269 * this number conveniently equals the number of leading zeroes in
270 * the physical address of __idmap_text_end.
272 adrp x5, __idmap_text_end
274 cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough?
275 b.ge 1f // .. then skip additional level
280 dc ivac, x6 // Invalidate potentially stale cache line
282 create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6
286 create_pgd_entry x0, x3, x5, x6
287 mov x5, x3 // __pa(__idmap_text_start)
288 adr_l x6, __idmap_text_end // __pa(__idmap_text_end)
289 create_block_map x0, x7, x3, x5, x6
292 * Map the kernel image (starting with PHYS_OFFSET).
294 adrp x0, swapper_pg_dir
295 mov_q x5, KIMAGE_VADDR + TEXT_OFFSET // compile time __va(_text)
296 add x5, x5, x23 // add KASLR displacement
297 create_pgd_entry x0, x5, x3, x6
298 adrp x6, _end // runtime __pa(_end)
299 adrp x3, _text // runtime __pa(_text)
300 sub x6, x6, x3 // _end - _text
301 add x6, x6, x5 // runtime __va(_end)
302 create_block_map x0, x7, x3, x5, x6
305 * Since the page tables have been populated with non-cacheable
306 * accesses (MMU disabled), invalidate the idmap and swapper page
307 * tables again to remove any speculatively loaded cache lines.
309 adrp x0, idmap_pg_dir
310 adrp x1, swapper_pg_dir + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE
312 bl __inval_cache_range
315 ENDPROC(__create_page_tables)
319 * The following fragment of code is executed with the MMU enabled.
324 adrp x4, init_thread_union
325 add sp, x4, #THREAD_SIZE
327 msr sp_el0, x5 // Save thread_info
329 adr_l x8, vectors // load VBAR_EL1 with virtual
330 msr vbar_el1, x8 // vector table address
333 stp xzr, x30, [sp, #-16]!
336 str_l x21, __fdt_pointer, x5 // Save FDT pointer
338 ldr_l x4, kimage_vaddr // Save the offset between
339 sub x4, x4, x0 // the kernel virtual and
340 str_l x4, kimage_voffset, x5 // physical mappings
343 adr_l x0, __bss_start
348 dsb ishst // Make zero page visible to PTW
353 #ifdef CONFIG_RANDOMIZE_BASE
354 tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized?
356 mov x0, x21 // pass FDT address in x0
357 bl kaslr_early_init // parse FDT for KASLR options
358 cbz x0, 0f // KASLR disabled? just proceed
359 orr x23, x23, x0 // record KASLR offset
360 ldp x29, x30, [sp], #16 // we must enable KASLR, return
361 ret // to __primary_switch()
365 ENDPROC(__primary_switched)
368 * end early head section, begin head code that is also used for
369 * hotplug and needs to have the same protections as the text region
371 .section ".idmap.text","ax"
374 .quad _text - TEXT_OFFSET
377 * If we're fortunate enough to boot at EL2, ensure that the world is
378 * sane before dropping to EL1.
380 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in w0 if
381 * booted in EL1 or EL2 respectively.
385 cmp x0, #CurrentEL_EL2
388 CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1
389 CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
391 mov w0, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
396 CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2
397 CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2
400 #ifdef CONFIG_ARM64_VHE
402 * Check for VHE being present. For the rest of the EL2 setup,
403 * x2 being non-zero indicates that we do have VHE, and that the
404 * kernel is intended to run at EL2.
406 mrs x2, id_aa64mmfr1_el1
412 /* Hyp configuration. */
413 mov x0, #HCR_RW // 64-bit EL1
415 orr x0, x0, #HCR_TGE // Enable Host Extensions
422 * Allow Non-secure EL1 and EL0 to access physical timer and counter.
423 * This is not necessary for VHE, since the host kernel runs in EL2,
424 * and EL0 accesses are configured in the later stage of boot process.
425 * Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout
426 * as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined
427 * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1
428 * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in
433 orr x0, x0, #3 // Enable EL1 physical timers
436 msr cntvoff_el2, xzr // Clear virtual offset
438 #ifdef CONFIG_ARM_GIC_V3
439 /* GICv3 system register access */
440 mrs x0, id_aa64pfr0_el1
445 mrs_s x0, SYS_ICC_SRE_EL2
446 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
447 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
448 msr_s SYS_ICC_SRE_EL2, x0
449 isb // Make sure SRE is now set
450 mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back,
451 tbz x0, #0, 3f // and check that it sticks
452 msr_s SYS_ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
457 /* Populate ID registers. */
464 msr hstr_el2, xzr // Disable CP15 traps to EL2
468 mrs x1, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
471 b.lt 4f // Skip if no PMU present
472 mrs x0, pmcr_el0 // Disable debug access traps
473 ubfx x0, x0, #11, #5 // to EL2 and allow access to
475 csel x3, xzr, x0, lt // all PMU counters from EL1
477 /* Statistical profiling */
478 ubfx x0, x1, #32, #4 // Check ID_AA64DFR0_EL1 PMSVer
479 cbz x0, 6f // Skip if SPE not present
481 mov x1, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
482 orr x3, x3, x1 // If we don't have VHE, then
483 b 6f // use EL1&0 translation.
484 5: // For VHE, use EL2 translation
485 orr x3, x3, #MDCR_EL2_TPMS // and disable access from EL1
487 msr mdcr_el2, x3 // Configure debug traps
489 /* Stage-2 translation */
492 cbz x2, install_el2_stub
494 mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
500 * When VHE is not in use, early init of EL2 and EL1 needs to be
502 * When VHE _is_ in use, EL1 will not be used in the host and
503 * requires no configuration, and all non-hyp-specific EL2 setup
504 * will be done via the _EL1 system register aliases in __cpu_setup.
507 mov x0, #0x0800 // Set/clear RES{1,0} bits
508 CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems
509 CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
512 /* Coprocessor traps. */
514 msr cptr_el2, x0 // Disable copro. traps to EL2
516 /* Hypervisor stub */
517 adr_l x0, __hyp_stub_vectors
521 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
525 mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
530 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
531 * in w0. See arch/arm64/include/asm/virt.h for more info.
533 set_cpu_boot_mode_flag:
534 adr_l x1, __boot_cpu_mode
535 cmp w0, #BOOT_CPU_MODE_EL2
538 1: str w0, [x1] // This CPU has booted in EL1
540 dc ivac, x1 // Invalidate potentially stale cache line
542 ENDPROC(set_cpu_boot_mode_flag)
545 * These values are written with the MMU off, but read with the MMU on.
546 * Writers will invalidate the corresponding address, discarding up to a
547 * 'Cache Writeback Granule' (CWG) worth of data. The linker script ensures
548 * sufficient alignment that the CWG doesn't overlap another section.
550 .pushsection ".mmuoff.data.write", "aw"
552 * We need to find out the CPU boot mode long after boot, so we need to
553 * store it in a writable variable.
555 * This is not in .bss, because we set it sufficiently early that the boot-time
556 * zeroing of .bss would clobber it.
558 ENTRY(__boot_cpu_mode)
559 .long BOOT_CPU_MODE_EL2
560 .long BOOT_CPU_MODE_EL1
562 * The booting CPU updates the failed status @__early_cpu_boot_status,
563 * with MMU turned off.
565 ENTRY(__early_cpu_boot_status)
571 * This provides a "holding pen" for platforms to hold all secondary
572 * cores are held until we're ready for them to initialise.
574 ENTRY(secondary_holding_pen)
575 bl el2_setup // Drop to EL1, w0=cpu_boot_mode
576 bl set_cpu_boot_mode_flag
578 mov_q x1, MPIDR_HWID_BITMASK
580 adr_l x3, secondary_holding_pen_release
583 b.eq secondary_startup
586 ENDPROC(secondary_holding_pen)
589 * Secondary entry point that jumps straight into the kernel. Only to
590 * be used where CPUs are brought online dynamically by the kernel.
592 ENTRY(secondary_entry)
593 bl el2_setup // Drop to EL1
594 bl set_cpu_boot_mode_flag
596 ENDPROC(secondary_entry)
600 * Common entry point for secondary CPUs.
602 bl __cpu_setup // initialise processor
604 ldr x8, =__secondary_switched
606 ENDPROC(secondary_startup)
608 __secondary_switched:
613 adr_l x0, secondary_data
614 ldr x1, [x0, #CPU_BOOT_STACK] // get secondary_data.stack
616 ldr x2, [x0, #CPU_BOOT_TASK]
619 b secondary_start_kernel
620 ENDPROC(__secondary_switched)
623 * The booting CPU updates the failed status @__early_cpu_boot_status,
624 * with MMU turned off.
626 * update_early_cpu_boot_status tmp, status
627 * - Corrupts tmp1, tmp2
628 * - Writes 'status' to __early_cpu_boot_status and makes sure
629 * it is committed to memory.
632 .macro update_early_cpu_boot_status status, tmp1, tmp2
634 adr_l \tmp1, __early_cpu_boot_status
637 dc ivac, \tmp1 // Invalidate potentially stale cache line
643 * x0 = SCTLR_EL1 value for turning on the MMU.
645 * Returns to the caller via x30/lr. This requires the caller to be covered
646 * by the .idmap.text section.
648 * Checks if the selected granule size is supported by the CPU.
649 * If it isn't, park the CPU
652 mrs x1, ID_AA64MMFR0_EL1
653 ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4
654 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED
655 b.ne __no_granule_support
656 update_early_cpu_boot_status 0, x1, x2
657 adrp x1, idmap_pg_dir
658 adrp x2, swapper_pg_dir
659 msr ttbr0_el1, x1 // load TTBR0
660 msr ttbr1_el1, x2 // load TTBR1
665 * Invalidate the local I-cache so that any instructions fetched
666 * speculatively from the PoC are discarded, since they may have
667 * been dynamically patched at the PoU.
673 ENDPROC(__enable_mmu)
675 __no_granule_support:
676 /* Indicate that this CPU can't boot and is stuck in the kernel */
677 update_early_cpu_boot_status CPU_STUCK_IN_KERNEL, x1, x2
682 ENDPROC(__no_granule_support)
684 #ifdef CONFIG_RELOCATABLE
687 * Iterate over each entry in the relocation table, and apply the
688 * relocations in place.
690 ldr w9, =__rela_offset // offset to reloc table
691 ldr w10, =__rela_size // size of reloc table
693 mov_q x11, KIMAGE_VADDR // default virtual offset
694 add x11, x11, x23 // actual virtual offset
695 add x9, x9, x11 // __va(.rela)
696 add x10, x9, x10 // __va(.rela) + sizeof(.rela)
700 ldp x11, x12, [x9], #24
702 cmp w12, #R_AARCH64_RELATIVE
704 add x13, x13, x23 // relocate
708 ENDPROC(__relocate_kernel)
712 #ifdef CONFIG_RANDOMIZE_BASE
713 mov x19, x0 // preserve new SCTLR_EL1 value
714 mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value
718 #ifdef CONFIG_RELOCATABLE
720 #ifdef CONFIG_RANDOMIZE_BASE
721 ldr x8, =__primary_switched
722 adrp x0, __PHYS_OFFSET
726 * If we return here, we have a KASLR displacement in x23 which we need
727 * to take into account by discarding the current kernel mapping and
728 * creating a new one.
730 msr sctlr_el1, x20 // disable the MMU
732 bl __create_page_tables // recreate kernel mapping
734 tlbi vmalle1 // Remove any stale TLB entries
737 msr sctlr_el1, x19 // re-enable the MMU
739 ic iallu // flush instructions fetched
740 dsb nsh // via old mapping
746 ldr x8, =__primary_switched
747 adrp x0, __PHYS_OFFSET
749 ENDPROC(__primary_switch)