2 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
3 * using the CPU's debug registers.
5 * Copyright (C) 2012 ARM Limited
6 * Author: Will Deacon <will.deacon@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #define pr_fmt(fmt) "hw-breakpoint: " fmt
23 #include <linux/compat.h>
24 #include <linux/cpu_pm.h>
25 #include <linux/errno.h>
26 #include <linux/hw_breakpoint.h>
27 #include <linux/kprobes.h>
28 #include <linux/perf_event.h>
29 #include <linux/ptrace.h>
30 #include <linux/smp.h>
32 #include <asm/compat.h>
33 #include <asm/current.h>
34 #include <asm/debug-monitors.h>
35 #include <asm/hw_breakpoint.h>
36 #include <asm/traps.h>
37 #include <asm/cputype.h>
38 #include <asm/system_misc.h>
40 /* Breakpoint currently in use for each BRP. */
41 static DEFINE_PER_CPU(struct perf_event
*, bp_on_reg
[ARM_MAX_BRP
]);
43 /* Watchpoint currently in use for each WRP. */
44 static DEFINE_PER_CPU(struct perf_event
*, wp_on_reg
[ARM_MAX_WRP
]);
46 /* Currently stepping a per-CPU kernel breakpoint. */
47 static DEFINE_PER_CPU(int, stepping_kernel_bp
);
49 /* Number of BRP/WRP registers on this CPU. */
50 static int core_num_brps
;
51 static int core_num_wrps
;
53 int hw_breakpoint_slots(int type
)
56 * We can be called early, so don't rely on
57 * our static variables being initialised.
61 return get_num_brps();
63 return get_num_wrps();
65 pr_warning("unknown slot type: %d\n", type
);
70 #define READ_WB_REG_CASE(OFF, N, REG, VAL) \
72 AARCH64_DBG_READ(N, REG, VAL); \
75 #define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \
77 AARCH64_DBG_WRITE(N, REG, VAL); \
80 #define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \
81 READ_WB_REG_CASE(OFF, 0, REG, VAL); \
82 READ_WB_REG_CASE(OFF, 1, REG, VAL); \
83 READ_WB_REG_CASE(OFF, 2, REG, VAL); \
84 READ_WB_REG_CASE(OFF, 3, REG, VAL); \
85 READ_WB_REG_CASE(OFF, 4, REG, VAL); \
86 READ_WB_REG_CASE(OFF, 5, REG, VAL); \
87 READ_WB_REG_CASE(OFF, 6, REG, VAL); \
88 READ_WB_REG_CASE(OFF, 7, REG, VAL); \
89 READ_WB_REG_CASE(OFF, 8, REG, VAL); \
90 READ_WB_REG_CASE(OFF, 9, REG, VAL); \
91 READ_WB_REG_CASE(OFF, 10, REG, VAL); \
92 READ_WB_REG_CASE(OFF, 11, REG, VAL); \
93 READ_WB_REG_CASE(OFF, 12, REG, VAL); \
94 READ_WB_REG_CASE(OFF, 13, REG, VAL); \
95 READ_WB_REG_CASE(OFF, 14, REG, VAL); \
96 READ_WB_REG_CASE(OFF, 15, REG, VAL)
98 #define GEN_WRITE_WB_REG_CASES(OFF, REG, VAL) \
99 WRITE_WB_REG_CASE(OFF, 0, REG, VAL); \
100 WRITE_WB_REG_CASE(OFF, 1, REG, VAL); \
101 WRITE_WB_REG_CASE(OFF, 2, REG, VAL); \
102 WRITE_WB_REG_CASE(OFF, 3, REG, VAL); \
103 WRITE_WB_REG_CASE(OFF, 4, REG, VAL); \
104 WRITE_WB_REG_CASE(OFF, 5, REG, VAL); \
105 WRITE_WB_REG_CASE(OFF, 6, REG, VAL); \
106 WRITE_WB_REG_CASE(OFF, 7, REG, VAL); \
107 WRITE_WB_REG_CASE(OFF, 8, REG, VAL); \
108 WRITE_WB_REG_CASE(OFF, 9, REG, VAL); \
109 WRITE_WB_REG_CASE(OFF, 10, REG, VAL); \
110 WRITE_WB_REG_CASE(OFF, 11, REG, VAL); \
111 WRITE_WB_REG_CASE(OFF, 12, REG, VAL); \
112 WRITE_WB_REG_CASE(OFF, 13, REG, VAL); \
113 WRITE_WB_REG_CASE(OFF, 14, REG, VAL); \
114 WRITE_WB_REG_CASE(OFF, 15, REG, VAL)
116 static u64
read_wb_reg(int reg
, int n
)
121 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BVR
, AARCH64_DBG_REG_NAME_BVR
, val
);
122 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BCR
, AARCH64_DBG_REG_NAME_BCR
, val
);
123 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WVR
, AARCH64_DBG_REG_NAME_WVR
, val
);
124 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WCR
, AARCH64_DBG_REG_NAME_WCR
, val
);
126 pr_warning("attempt to read from unknown breakpoint register %d\n", n
);
131 NOKPROBE_SYMBOL(read_wb_reg
);
133 static void write_wb_reg(int reg
, int n
, u64 val
)
136 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BVR
, AARCH64_DBG_REG_NAME_BVR
, val
);
137 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BCR
, AARCH64_DBG_REG_NAME_BCR
, val
);
138 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WVR
, AARCH64_DBG_REG_NAME_WVR
, val
);
139 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WCR
, AARCH64_DBG_REG_NAME_WCR
, val
);
141 pr_warning("attempt to write to unknown breakpoint register %d\n", n
);
145 NOKPROBE_SYMBOL(write_wb_reg
);
148 * Convert a breakpoint privilege level to the corresponding exception
151 static enum dbg_active_el
debug_exception_level(int privilege
)
154 case AARCH64_BREAKPOINT_EL0
:
155 return DBG_ACTIVE_EL0
;
156 case AARCH64_BREAKPOINT_EL1
:
157 return DBG_ACTIVE_EL1
;
159 pr_warning("invalid breakpoint privilege level %d\n", privilege
);
163 NOKPROBE_SYMBOL(debug_exception_level
);
165 enum hw_breakpoint_ops
{
166 HW_BREAKPOINT_INSTALL
,
167 HW_BREAKPOINT_UNINSTALL
,
168 HW_BREAKPOINT_RESTORE
171 static int is_compat_bp(struct perf_event
*bp
)
173 struct task_struct
*tsk
= bp
->hw
.target
;
176 * tsk can be NULL for per-cpu (non-ptrace) breakpoints.
177 * In this case, use the native interface, since we don't have
178 * the notion of a "compat CPU" and could end up relying on
179 * deprecated behaviour if we use unaligned watchpoints in
182 return tsk
&& is_compat_thread(task_thread_info(tsk
));
186 * hw_breakpoint_slot_setup - Find and setup a perf slot according to
189 * @slots: pointer to array of slots
190 * @max_slots: max number of slots
191 * @bp: perf_event to setup
192 * @ops: operation to be carried out on the slot
195 * slot index on success
196 * -ENOSPC if no slot is available/matches
197 * -EINVAL on wrong operations parameter
199 static int hw_breakpoint_slot_setup(struct perf_event
**slots
, int max_slots
,
200 struct perf_event
*bp
,
201 enum hw_breakpoint_ops ops
)
204 struct perf_event
**slot
;
206 for (i
= 0; i
< max_slots
; ++i
) {
209 case HW_BREAKPOINT_INSTALL
:
215 case HW_BREAKPOINT_UNINSTALL
:
221 case HW_BREAKPOINT_RESTORE
:
226 pr_warn_once("Unhandled hw breakpoint ops %d\n", ops
);
233 static int hw_breakpoint_control(struct perf_event
*bp
,
234 enum hw_breakpoint_ops ops
)
236 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
237 struct perf_event
**slots
;
238 struct debug_info
*debug_info
= ¤t
->thread
.debug
;
239 int i
, max_slots
, ctrl_reg
, val_reg
, reg_enable
;
240 enum dbg_active_el dbg_el
= debug_exception_level(info
->ctrl
.privilege
);
243 if (info
->ctrl
.type
== ARM_BREAKPOINT_EXECUTE
) {
245 ctrl_reg
= AARCH64_DBG_REG_BCR
;
246 val_reg
= AARCH64_DBG_REG_BVR
;
247 slots
= this_cpu_ptr(bp_on_reg
);
248 max_slots
= core_num_brps
;
249 reg_enable
= !debug_info
->bps_disabled
;
252 ctrl_reg
= AARCH64_DBG_REG_WCR
;
253 val_reg
= AARCH64_DBG_REG_WVR
;
254 slots
= this_cpu_ptr(wp_on_reg
);
255 max_slots
= core_num_wrps
;
256 reg_enable
= !debug_info
->wps_disabled
;
259 i
= hw_breakpoint_slot_setup(slots
, max_slots
, bp
, ops
);
261 if (WARN_ONCE(i
< 0, "Can't find any breakpoint slot"))
265 case HW_BREAKPOINT_INSTALL
:
267 * Ensure debug monitors are enabled at the correct exception
270 enable_debug_monitors(dbg_el
);
272 case HW_BREAKPOINT_RESTORE
:
273 /* Setup the address register. */
274 write_wb_reg(val_reg
, i
, info
->address
);
276 /* Setup the control register. */
277 ctrl
= encode_ctrl_reg(info
->ctrl
);
278 write_wb_reg(ctrl_reg
, i
,
279 reg_enable
? ctrl
| 0x1 : ctrl
& ~0x1);
281 case HW_BREAKPOINT_UNINSTALL
:
282 /* Reset the control register. */
283 write_wb_reg(ctrl_reg
, i
, 0);
286 * Release the debug monitors for the correct exception
289 disable_debug_monitors(dbg_el
);
297 * Install a perf counter breakpoint.
299 int arch_install_hw_breakpoint(struct perf_event
*bp
)
301 return hw_breakpoint_control(bp
, HW_BREAKPOINT_INSTALL
);
304 void arch_uninstall_hw_breakpoint(struct perf_event
*bp
)
306 hw_breakpoint_control(bp
, HW_BREAKPOINT_UNINSTALL
);
309 static int get_hbp_len(u8 hbp_len
)
311 unsigned int len_in_bytes
= 0;
314 case ARM_BREAKPOINT_LEN_1
:
317 case ARM_BREAKPOINT_LEN_2
:
320 case ARM_BREAKPOINT_LEN_4
:
323 case ARM_BREAKPOINT_LEN_8
:
332 * Check whether bp virtual address is in kernel space.
334 int arch_check_bp_in_kernelspace(struct perf_event
*bp
)
338 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
341 len
= get_hbp_len(info
->ctrl
.len
);
343 return (va
>= TASK_SIZE
) && ((va
+ len
- 1) >= TASK_SIZE
);
347 * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
348 * Hopefully this will disappear when ptrace can bypass the conversion
349 * to generic breakpoint descriptions.
351 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl
,
352 int *gen_len
, int *gen_type
)
356 case ARM_BREAKPOINT_EXECUTE
:
357 *gen_type
= HW_BREAKPOINT_X
;
359 case ARM_BREAKPOINT_LOAD
:
360 *gen_type
= HW_BREAKPOINT_R
;
362 case ARM_BREAKPOINT_STORE
:
363 *gen_type
= HW_BREAKPOINT_W
;
365 case ARM_BREAKPOINT_LOAD
| ARM_BREAKPOINT_STORE
:
366 *gen_type
= HW_BREAKPOINT_RW
;
374 case ARM_BREAKPOINT_LEN_1
:
375 *gen_len
= HW_BREAKPOINT_LEN_1
;
377 case ARM_BREAKPOINT_LEN_2
:
378 *gen_len
= HW_BREAKPOINT_LEN_2
;
380 case ARM_BREAKPOINT_LEN_4
:
381 *gen_len
= HW_BREAKPOINT_LEN_4
;
383 case ARM_BREAKPOINT_LEN_8
:
384 *gen_len
= HW_BREAKPOINT_LEN_8
;
394 * Construct an arch_hw_breakpoint from a perf_event.
396 static int arch_build_bp_info(struct perf_event
*bp
)
398 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
401 switch (bp
->attr
.bp_type
) {
402 case HW_BREAKPOINT_X
:
403 info
->ctrl
.type
= ARM_BREAKPOINT_EXECUTE
;
405 case HW_BREAKPOINT_R
:
406 info
->ctrl
.type
= ARM_BREAKPOINT_LOAD
;
408 case HW_BREAKPOINT_W
:
409 info
->ctrl
.type
= ARM_BREAKPOINT_STORE
;
411 case HW_BREAKPOINT_RW
:
412 info
->ctrl
.type
= ARM_BREAKPOINT_LOAD
| ARM_BREAKPOINT_STORE
;
419 switch (bp
->attr
.bp_len
) {
420 case HW_BREAKPOINT_LEN_1
:
421 info
->ctrl
.len
= ARM_BREAKPOINT_LEN_1
;
423 case HW_BREAKPOINT_LEN_2
:
424 info
->ctrl
.len
= ARM_BREAKPOINT_LEN_2
;
426 case HW_BREAKPOINT_LEN_4
:
427 info
->ctrl
.len
= ARM_BREAKPOINT_LEN_4
;
429 case HW_BREAKPOINT_LEN_8
:
430 info
->ctrl
.len
= ARM_BREAKPOINT_LEN_8
;
437 * On AArch64, we only permit breakpoints of length 4, whereas
438 * AArch32 also requires breakpoints of length 2 for Thumb.
439 * Watchpoints can be of length 1, 2, 4 or 8 bytes.
441 if (info
->ctrl
.type
== ARM_BREAKPOINT_EXECUTE
) {
442 if (is_compat_bp(bp
)) {
443 if (info
->ctrl
.len
!= ARM_BREAKPOINT_LEN_2
&&
444 info
->ctrl
.len
!= ARM_BREAKPOINT_LEN_4
)
446 } else if (info
->ctrl
.len
!= ARM_BREAKPOINT_LEN_4
) {
448 * FIXME: Some tools (I'm looking at you perf) assume
449 * that breakpoints should be sizeof(long). This
450 * is nonsense. For now, we fix up the parameter
451 * but we should probably return -EINVAL instead.
453 info
->ctrl
.len
= ARM_BREAKPOINT_LEN_4
;
458 info
->address
= bp
->attr
.bp_addr
;
462 * Note that we disallow combined EL0/EL1 breakpoints because
463 * that would complicate the stepping code.
465 if (arch_check_bp_in_kernelspace(bp
))
466 info
->ctrl
.privilege
= AARCH64_BREAKPOINT_EL1
;
468 info
->ctrl
.privilege
= AARCH64_BREAKPOINT_EL0
;
471 info
->ctrl
.enabled
= !bp
->attr
.disabled
;
477 * Validate the arch-specific HW Breakpoint register settings.
479 int arch_validate_hwbkpt_settings(struct perf_event
*bp
)
481 struct arch_hw_breakpoint
*info
= counter_arch_bp(bp
);
483 u64 alignment_mask
, offset
;
485 /* Build the arch_hw_breakpoint. */
486 ret
= arch_build_bp_info(bp
);
491 * Check address alignment.
492 * We don't do any clever alignment correction for watchpoints
493 * because using 64-bit unaligned addresses is deprecated for
496 * AArch32 tasks expect some simple alignment fixups, so emulate
499 if (is_compat_bp(bp
)) {
500 if (info
->ctrl
.len
== ARM_BREAKPOINT_LEN_8
)
501 alignment_mask
= 0x7;
503 alignment_mask
= 0x3;
504 offset
= info
->address
& alignment_mask
;
510 /* Allow single byte watchpoint. */
511 if (info
->ctrl
.len
== ARM_BREAKPOINT_LEN_1
)
514 /* Allow halfword watchpoints and breakpoints. */
515 if (info
->ctrl
.len
== ARM_BREAKPOINT_LEN_2
)
521 info
->address
&= ~alignment_mask
;
522 info
->ctrl
.len
<<= offset
;
524 if (info
->ctrl
.type
== ARM_BREAKPOINT_EXECUTE
)
525 alignment_mask
= 0x3;
527 alignment_mask
= 0x7;
528 if (info
->address
& alignment_mask
)
533 * Disallow per-task kernel breakpoints since these would
534 * complicate the stepping code.
536 if (info
->ctrl
.privilege
== AARCH64_BREAKPOINT_EL1
&& bp
->hw
.target
)
543 * Enable/disable all of the breakpoints active at the specified
544 * exception level at the register level.
545 * This is used when single-stepping after a breakpoint exception.
547 static void toggle_bp_registers(int reg
, enum dbg_active_el el
, int enable
)
549 int i
, max_slots
, privilege
;
551 struct perf_event
**slots
;
554 case AARCH64_DBG_REG_BCR
:
555 slots
= this_cpu_ptr(bp_on_reg
);
556 max_slots
= core_num_brps
;
558 case AARCH64_DBG_REG_WCR
:
559 slots
= this_cpu_ptr(wp_on_reg
);
560 max_slots
= core_num_wrps
;
566 for (i
= 0; i
< max_slots
; ++i
) {
570 privilege
= counter_arch_bp(slots
[i
])->ctrl
.privilege
;
571 if (debug_exception_level(privilege
) != el
)
574 ctrl
= read_wb_reg(reg
, i
);
579 write_wb_reg(reg
, i
, ctrl
);
582 NOKPROBE_SYMBOL(toggle_bp_registers
);
585 * Debug exception handlers.
587 static int breakpoint_handler(unsigned long unused
, unsigned int esr
,
588 struct pt_regs
*regs
)
590 int i
, step
= 0, *kernel_step
;
593 struct perf_event
*bp
, **slots
;
594 struct debug_info
*debug_info
;
595 struct arch_hw_breakpoint_ctrl ctrl
;
597 slots
= this_cpu_ptr(bp_on_reg
);
598 addr
= instruction_pointer(regs
);
599 debug_info
= ¤t
->thread
.debug
;
601 for (i
= 0; i
< core_num_brps
; ++i
) {
609 /* Check if the breakpoint value matches. */
610 val
= read_wb_reg(AARCH64_DBG_REG_BVR
, i
);
611 if (val
!= (addr
& ~0x3))
614 /* Possible match, check the byte address select to confirm. */
615 ctrl_reg
= read_wb_reg(AARCH64_DBG_REG_BCR
, i
);
616 decode_ctrl_reg(ctrl_reg
, &ctrl
);
617 if (!((1 << (addr
& 0x3)) & ctrl
.len
))
620 counter_arch_bp(bp
)->trigger
= addr
;
621 perf_bp_event(bp
, regs
);
623 /* Do we need to handle the stepping? */
624 if (is_default_overflow_handler(bp
))
633 if (user_mode(regs
)) {
634 debug_info
->bps_disabled
= 1;
635 toggle_bp_registers(AARCH64_DBG_REG_BCR
, DBG_ACTIVE_EL0
, 0);
637 /* If we're already stepping a watchpoint, just return. */
638 if (debug_info
->wps_disabled
)
641 if (test_thread_flag(TIF_SINGLESTEP
))
642 debug_info
->suspended_step
= 1;
644 user_enable_single_step(current
);
646 toggle_bp_registers(AARCH64_DBG_REG_BCR
, DBG_ACTIVE_EL1
, 0);
647 kernel_step
= this_cpu_ptr(&stepping_kernel_bp
);
649 if (*kernel_step
!= ARM_KERNEL_STEP_NONE
)
652 if (kernel_active_single_step()) {
653 *kernel_step
= ARM_KERNEL_STEP_SUSPEND
;
655 *kernel_step
= ARM_KERNEL_STEP_ACTIVE
;
656 kernel_enable_single_step(regs
);
662 NOKPROBE_SYMBOL(breakpoint_handler
);
664 static int watchpoint_handler(unsigned long addr
, unsigned int esr
,
665 struct pt_regs
*regs
)
667 int i
, step
= 0, *kernel_step
, access
;
669 u64 val
, alignment_mask
;
670 struct perf_event
*wp
, **slots
;
671 struct debug_info
*debug_info
;
672 struct arch_hw_breakpoint
*info
;
673 struct arch_hw_breakpoint_ctrl ctrl
;
675 slots
= this_cpu_ptr(wp_on_reg
);
676 debug_info
= ¤t
->thread
.debug
;
678 for (i
= 0; i
< core_num_wrps
; ++i
) {
686 info
= counter_arch_bp(wp
);
687 /* AArch32 watchpoints are either 4 or 8 bytes aligned. */
688 if (is_compat_task()) {
689 if (info
->ctrl
.len
== ARM_BREAKPOINT_LEN_8
)
690 alignment_mask
= 0x7;
692 alignment_mask
= 0x3;
694 alignment_mask
= 0x7;
697 /* Check if the watchpoint value matches. */
698 val
= read_wb_reg(AARCH64_DBG_REG_WVR
, i
);
699 if (val
!= (addr
& ~alignment_mask
))
702 /* Possible match, check the byte address select to confirm. */
703 ctrl_reg
= read_wb_reg(AARCH64_DBG_REG_WCR
, i
);
704 decode_ctrl_reg(ctrl_reg
, &ctrl
);
705 if (!((1 << (addr
& alignment_mask
)) & ctrl
.len
))
709 * Check that the access type matches.
710 * 0 => load, otherwise => store
712 access
= (esr
& AARCH64_ESR_ACCESS_MASK
) ? HW_BREAKPOINT_W
:
714 if (!(access
& hw_breakpoint_type(wp
)))
717 info
->trigger
= addr
;
718 perf_bp_event(wp
, regs
);
720 /* Do we need to handle the stepping? */
721 if (is_default_overflow_handler(wp
))
732 * We always disable EL0 watchpoints because the kernel can
733 * cause these to fire via an unprivileged access.
735 toggle_bp_registers(AARCH64_DBG_REG_WCR
, DBG_ACTIVE_EL0
, 0);
737 if (user_mode(regs
)) {
738 debug_info
->wps_disabled
= 1;
740 /* If we're already stepping a breakpoint, just return. */
741 if (debug_info
->bps_disabled
)
744 if (test_thread_flag(TIF_SINGLESTEP
))
745 debug_info
->suspended_step
= 1;
747 user_enable_single_step(current
);
749 toggle_bp_registers(AARCH64_DBG_REG_WCR
, DBG_ACTIVE_EL1
, 0);
750 kernel_step
= this_cpu_ptr(&stepping_kernel_bp
);
752 if (*kernel_step
!= ARM_KERNEL_STEP_NONE
)
755 if (kernel_active_single_step()) {
756 *kernel_step
= ARM_KERNEL_STEP_SUSPEND
;
758 *kernel_step
= ARM_KERNEL_STEP_ACTIVE
;
759 kernel_enable_single_step(regs
);
765 NOKPROBE_SYMBOL(watchpoint_handler
);
768 * Handle single-step exception.
770 int reinstall_suspended_bps(struct pt_regs
*regs
)
772 struct debug_info
*debug_info
= ¤t
->thread
.debug
;
773 int handled_exception
= 0, *kernel_step
;
775 kernel_step
= this_cpu_ptr(&stepping_kernel_bp
);
778 * Called from single-step exception handler.
779 * Return 0 if execution can resume, 1 if a SIGTRAP should be
782 if (user_mode(regs
)) {
783 if (debug_info
->bps_disabled
) {
784 debug_info
->bps_disabled
= 0;
785 toggle_bp_registers(AARCH64_DBG_REG_BCR
, DBG_ACTIVE_EL0
, 1);
786 handled_exception
= 1;
789 if (debug_info
->wps_disabled
) {
790 debug_info
->wps_disabled
= 0;
791 toggle_bp_registers(AARCH64_DBG_REG_WCR
, DBG_ACTIVE_EL0
, 1);
792 handled_exception
= 1;
795 if (handled_exception
) {
796 if (debug_info
->suspended_step
) {
797 debug_info
->suspended_step
= 0;
798 /* Allow exception handling to fall-through. */
799 handled_exception
= 0;
801 user_disable_single_step(current
);
804 } else if (*kernel_step
!= ARM_KERNEL_STEP_NONE
) {
805 toggle_bp_registers(AARCH64_DBG_REG_BCR
, DBG_ACTIVE_EL1
, 1);
806 toggle_bp_registers(AARCH64_DBG_REG_WCR
, DBG_ACTIVE_EL1
, 1);
808 if (!debug_info
->wps_disabled
)
809 toggle_bp_registers(AARCH64_DBG_REG_WCR
, DBG_ACTIVE_EL0
, 1);
811 if (*kernel_step
!= ARM_KERNEL_STEP_SUSPEND
) {
812 kernel_disable_single_step();
813 handled_exception
= 1;
815 handled_exception
= 0;
818 *kernel_step
= ARM_KERNEL_STEP_NONE
;
821 return !handled_exception
;
823 NOKPROBE_SYMBOL(reinstall_suspended_bps
);
826 * Context-switcher for restoring suspended breakpoints.
828 void hw_breakpoint_thread_switch(struct task_struct
*next
)
832 * disabled: 0 0 => The usual case, NOTIFY_DONE
833 * 0 1 => Disable the registers
834 * 1 0 => Enable the registers
835 * 1 1 => NOTIFY_DONE. per-task bps will
836 * get taken care of by perf.
839 struct debug_info
*current_debug_info
, *next_debug_info
;
841 current_debug_info
= ¤t
->thread
.debug
;
842 next_debug_info
= &next
->thread
.debug
;
844 /* Update breakpoints. */
845 if (current_debug_info
->bps_disabled
!= next_debug_info
->bps_disabled
)
846 toggle_bp_registers(AARCH64_DBG_REG_BCR
,
848 !next_debug_info
->bps_disabled
);
850 /* Update watchpoints. */
851 if (current_debug_info
->wps_disabled
!= next_debug_info
->wps_disabled
)
852 toggle_bp_registers(AARCH64_DBG_REG_WCR
,
854 !next_debug_info
->wps_disabled
);
858 * CPU initialisation.
860 static int hw_breakpoint_reset(unsigned int cpu
)
863 struct perf_event
**slots
;
865 * When a CPU goes through cold-boot, it does not have any installed
866 * slot, so it is safe to share the same function for restoring and
867 * resetting breakpoints; when a CPU is hotplugged in, it goes
868 * through the slots, which are all empty, hence it just resets control
869 * and value for debug registers.
870 * When this function is triggered on warm-boot through a CPU PM
871 * notifier some slots might be initialized; if so they are
872 * reprogrammed according to the debug slots content.
874 for (slots
= this_cpu_ptr(bp_on_reg
), i
= 0; i
< core_num_brps
; ++i
) {
876 hw_breakpoint_control(slots
[i
], HW_BREAKPOINT_RESTORE
);
878 write_wb_reg(AARCH64_DBG_REG_BCR
, i
, 0UL);
879 write_wb_reg(AARCH64_DBG_REG_BVR
, i
, 0UL);
883 for (slots
= this_cpu_ptr(wp_on_reg
), i
= 0; i
< core_num_wrps
; ++i
) {
885 hw_breakpoint_control(slots
[i
], HW_BREAKPOINT_RESTORE
);
887 write_wb_reg(AARCH64_DBG_REG_WCR
, i
, 0UL);
888 write_wb_reg(AARCH64_DBG_REG_WVR
, i
, 0UL);
896 extern void cpu_suspend_set_dbg_restorer(int (*hw_bp_restore
)(unsigned int));
898 static inline void cpu_suspend_set_dbg_restorer(int (*hw_bp_restore
)(unsigned int))
904 * One-time initialisation.
906 static int __init
arch_hw_breakpoint_init(void)
910 core_num_brps
= get_num_brps();
911 core_num_wrps
= get_num_wrps();
913 pr_info("found %d breakpoint and %d watchpoint registers.\n",
914 core_num_brps
, core_num_wrps
);
916 /* Register debug fault handlers. */
917 hook_debug_fault_code(DBG_ESR_EVT_HWBP
, breakpoint_handler
, SIGTRAP
,
918 TRAP_HWBKPT
, "hw-breakpoint handler");
919 hook_debug_fault_code(DBG_ESR_EVT_HWWP
, watchpoint_handler
, SIGTRAP
,
920 TRAP_HWBKPT
, "hw-watchpoint handler");
923 * Reset the breakpoint resources. We assume that a halting
924 * debugger will leave the world in a nice state for us.
926 ret
= cpuhp_setup_state(CPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING
,
927 "CPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING",
928 hw_breakpoint_reset
, NULL
);
930 pr_err("failed to register CPU hotplug notifier: %d\n", ret
);
932 /* Register cpu_suspend hw breakpoint restore hook */
933 cpu_suspend_set_dbg_restorer(hw_breakpoint_reset
);
937 arch_initcall(arch_hw_breakpoint_init
);
939 void hw_breakpoint_pmu_read(struct perf_event
*bp
)
944 * Dummy function to register with die_notifier.
946 int hw_breakpoint_exceptions_notify(struct notifier_block
*unused
,
947 unsigned long val
, void *data
)