2 * Copyright (C) 2013 Huawei Ltd.
3 * Author: Jiang Liu <liuj97@gmail.com>
5 * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/bitops.h>
20 #include <linux/compiler.h>
21 #include <linux/kernel.h>
22 #include <linux/smp.h>
23 #include <linux/stop_machine.h>
24 #include <linux/uaccess.h>
26 #include <asm/cacheflush.h>
27 #include <asm/debug-monitors.h>
30 #define AARCH64_INSN_SF_BIT BIT(31)
31 #define AARCH64_INSN_N_BIT BIT(22)
33 static int aarch64_insn_encoding_class
[] = {
34 AARCH64_INSN_CLS_UNKNOWN
,
35 AARCH64_INSN_CLS_UNKNOWN
,
36 AARCH64_INSN_CLS_UNKNOWN
,
37 AARCH64_INSN_CLS_UNKNOWN
,
38 AARCH64_INSN_CLS_LDST
,
39 AARCH64_INSN_CLS_DP_REG
,
40 AARCH64_INSN_CLS_LDST
,
41 AARCH64_INSN_CLS_DP_FPSIMD
,
42 AARCH64_INSN_CLS_DP_IMM
,
43 AARCH64_INSN_CLS_DP_IMM
,
44 AARCH64_INSN_CLS_BR_SYS
,
45 AARCH64_INSN_CLS_BR_SYS
,
46 AARCH64_INSN_CLS_LDST
,
47 AARCH64_INSN_CLS_DP_REG
,
48 AARCH64_INSN_CLS_LDST
,
49 AARCH64_INSN_CLS_DP_FPSIMD
,
52 enum aarch64_insn_encoding_class __kprobes
aarch64_get_insn_class(u32 insn
)
54 return aarch64_insn_encoding_class
[(insn
>> 25) & 0xf];
57 /* NOP is an alias of HINT */
58 bool __kprobes
aarch64_insn_is_nop(u32 insn
)
60 if (!aarch64_insn_is_hint(insn
))
63 switch (insn
& 0xFE0) {
64 case AARCH64_INSN_HINT_YIELD
:
65 case AARCH64_INSN_HINT_WFE
:
66 case AARCH64_INSN_HINT_WFI
:
67 case AARCH64_INSN_HINT_SEV
:
68 case AARCH64_INSN_HINT_SEVL
:
76 * In ARMv8-A, A64 instructions have a fixed length of 32 bits and are always
79 int __kprobes
aarch64_insn_read(void *addr
, u32
*insnp
)
84 ret
= probe_kernel_read(&val
, addr
, AARCH64_INSN_SIZE
);
86 *insnp
= le32_to_cpu(val
);
91 int __kprobes
aarch64_insn_write(void *addr
, u32 insn
)
93 insn
= cpu_to_le32(insn
);
94 return probe_kernel_write(addr
, &insn
, AARCH64_INSN_SIZE
);
97 static bool __kprobes
__aarch64_insn_hotpatch_safe(u32 insn
)
99 if (aarch64_get_insn_class(insn
) != AARCH64_INSN_CLS_BR_SYS
)
102 return aarch64_insn_is_b(insn
) ||
103 aarch64_insn_is_bl(insn
) ||
104 aarch64_insn_is_svc(insn
) ||
105 aarch64_insn_is_hvc(insn
) ||
106 aarch64_insn_is_smc(insn
) ||
107 aarch64_insn_is_brk(insn
) ||
108 aarch64_insn_is_nop(insn
);
112 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
113 * Section B2.6.5 "Concurrent modification and execution of instructions":
114 * Concurrent modification and execution of instructions can lead to the
115 * resulting instruction performing any behavior that can be achieved by
116 * executing any sequence of instructions that can be executed from the
117 * same Exception level, except where the instruction before modification
118 * and the instruction after modification is a B, BL, NOP, BKPT, SVC, HVC,
119 * or SMC instruction.
121 bool __kprobes
aarch64_insn_hotpatch_safe(u32 old_insn
, u32 new_insn
)
123 return __aarch64_insn_hotpatch_safe(old_insn
) &&
124 __aarch64_insn_hotpatch_safe(new_insn
);
127 int __kprobes
aarch64_insn_patch_text_nosync(void *addr
, u32 insn
)
132 /* A64 instructions must be word aligned */
133 if ((uintptr_t)tp
& 0x3)
136 ret
= aarch64_insn_write(tp
, insn
);
138 flush_icache_range((uintptr_t)tp
,
139 (uintptr_t)tp
+ AARCH64_INSN_SIZE
);
144 struct aarch64_insn_patch
{
151 static int __kprobes
aarch64_insn_patch_text_cb(void *arg
)
154 struct aarch64_insn_patch
*pp
= arg
;
156 /* The first CPU becomes master */
157 if (atomic_inc_return(&pp
->cpu_count
) == 1) {
158 for (i
= 0; ret
== 0 && i
< pp
->insn_cnt
; i
++)
159 ret
= aarch64_insn_patch_text_nosync(pp
->text_addrs
[i
],
162 * aarch64_insn_patch_text_nosync() calls flush_icache_range(),
163 * which ends with "dsb; isb" pair guaranteeing global
166 /* Notify other processors with an additional increment. */
167 atomic_inc(&pp
->cpu_count
);
169 while (atomic_read(&pp
->cpu_count
) <= num_online_cpus())
177 int __kprobes
aarch64_insn_patch_text_sync(void *addrs
[], u32 insns
[], int cnt
)
179 struct aarch64_insn_patch patch
= {
183 .cpu_count
= ATOMIC_INIT(0),
189 return stop_machine(aarch64_insn_patch_text_cb
, &patch
,
193 int __kprobes
aarch64_insn_patch_text(void *addrs
[], u32 insns
[], int cnt
)
198 /* Unsafe to patch multiple instructions without synchronizaiton */
200 ret
= aarch64_insn_read(addrs
[0], &insn
);
204 if (aarch64_insn_hotpatch_safe(insn
, insns
[0])) {
206 * ARMv8 architecture doesn't guarantee all CPUs see
207 * the new instruction after returning from function
208 * aarch64_insn_patch_text_nosync(). So send IPIs to
209 * all other CPUs to achieve instruction
212 ret
= aarch64_insn_patch_text_nosync(addrs
[0], insns
[0]);
213 kick_all_cpus_sync();
218 return aarch64_insn_patch_text_sync(addrs
, insns
, cnt
);
221 u32 __kprobes
aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type
,
224 u32 immlo
, immhi
, lomask
, himask
, mask
;
228 case AARCH64_INSN_IMM_ADR
:
231 immlo
= imm
& lomask
;
233 immhi
= imm
& himask
;
234 imm
= (immlo
<< 24) | (immhi
);
235 mask
= (lomask
<< 24) | (himask
);
238 case AARCH64_INSN_IMM_26
:
242 case AARCH64_INSN_IMM_19
:
246 case AARCH64_INSN_IMM_16
:
250 case AARCH64_INSN_IMM_14
:
254 case AARCH64_INSN_IMM_12
:
258 case AARCH64_INSN_IMM_9
:
262 case AARCH64_INSN_IMM_7
:
266 case AARCH64_INSN_IMM_6
:
267 case AARCH64_INSN_IMM_S
:
271 case AARCH64_INSN_IMM_R
:
276 pr_err("aarch64_insn_encode_immediate: unknown immediate encoding %d\n",
281 /* Update the immediate field. */
282 insn
&= ~(mask
<< shift
);
283 insn
|= (imm
& mask
) << shift
;
288 static u32
aarch64_insn_encode_register(enum aarch64_insn_register_type type
,
290 enum aarch64_insn_register reg
)
294 if (reg
< AARCH64_INSN_REG_0
|| reg
> AARCH64_INSN_REG_SP
) {
295 pr_err("%s: unknown register encoding %d\n", __func__
, reg
);
300 case AARCH64_INSN_REGTYPE_RT
:
301 case AARCH64_INSN_REGTYPE_RD
:
304 case AARCH64_INSN_REGTYPE_RN
:
307 case AARCH64_INSN_REGTYPE_RT2
:
308 case AARCH64_INSN_REGTYPE_RA
:
311 case AARCH64_INSN_REGTYPE_RM
:
315 pr_err("%s: unknown register type encoding %d\n", __func__
,
320 insn
&= ~(GENMASK(4, 0) << shift
);
321 insn
|= reg
<< shift
;
326 static u32
aarch64_insn_encode_ldst_size(enum aarch64_insn_size_type type
,
332 case AARCH64_INSN_SIZE_8
:
335 case AARCH64_INSN_SIZE_16
:
338 case AARCH64_INSN_SIZE_32
:
341 case AARCH64_INSN_SIZE_64
:
345 pr_err("%s: unknown size encoding %d\n", __func__
, type
);
349 insn
&= ~GENMASK(31, 30);
355 static inline long branch_imm_common(unsigned long pc
, unsigned long addr
,
361 * PC: A 64-bit Program Counter holding the address of the current
362 * instruction. A64 instructions must be word-aligned.
364 BUG_ON((pc
& 0x3) || (addr
& 0x3));
366 offset
= ((long)addr
- (long)pc
);
367 BUG_ON(offset
< -range
|| offset
>= range
);
372 u32 __kprobes
aarch64_insn_gen_branch_imm(unsigned long pc
, unsigned long addr
,
373 enum aarch64_insn_branch_type type
)
379 * B/BL support [-128M, 128M) offset
380 * ARM64 virtual address arrangement guarantees all kernel and module
381 * texts are within +/-128M.
383 offset
= branch_imm_common(pc
, addr
, SZ_128M
);
386 case AARCH64_INSN_BRANCH_LINK
:
387 insn
= aarch64_insn_get_bl_value();
389 case AARCH64_INSN_BRANCH_NOLINK
:
390 insn
= aarch64_insn_get_b_value();
394 return AARCH64_BREAK_FAULT
;
397 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_26
, insn
,
401 u32
aarch64_insn_gen_comp_branch_imm(unsigned long pc
, unsigned long addr
,
402 enum aarch64_insn_register reg
,
403 enum aarch64_insn_variant variant
,
404 enum aarch64_insn_branch_type type
)
409 offset
= branch_imm_common(pc
, addr
, SZ_1M
);
412 case AARCH64_INSN_BRANCH_COMP_ZERO
:
413 insn
= aarch64_insn_get_cbz_value();
415 case AARCH64_INSN_BRANCH_COMP_NONZERO
:
416 insn
= aarch64_insn_get_cbnz_value();
420 return AARCH64_BREAK_FAULT
;
424 case AARCH64_INSN_VARIANT_32BIT
:
426 case AARCH64_INSN_VARIANT_64BIT
:
427 insn
|= AARCH64_INSN_SF_BIT
;
431 return AARCH64_BREAK_FAULT
;
434 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT
, insn
, reg
);
436 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19
, insn
,
440 u32
aarch64_insn_gen_cond_branch_imm(unsigned long pc
, unsigned long addr
,
441 enum aarch64_insn_condition cond
)
446 offset
= branch_imm_common(pc
, addr
, SZ_1M
);
448 insn
= aarch64_insn_get_bcond_value();
450 BUG_ON(cond
< AARCH64_INSN_COND_EQ
|| cond
> AARCH64_INSN_COND_AL
);
453 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_19
, insn
,
457 u32 __kprobes
aarch64_insn_gen_hint(enum aarch64_insn_hint_op op
)
459 return aarch64_insn_get_hint_value() | op
;
462 u32 __kprobes
aarch64_insn_gen_nop(void)
464 return aarch64_insn_gen_hint(AARCH64_INSN_HINT_NOP
);
467 u32
aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg
,
468 enum aarch64_insn_branch_type type
)
473 case AARCH64_INSN_BRANCH_NOLINK
:
474 insn
= aarch64_insn_get_br_value();
476 case AARCH64_INSN_BRANCH_LINK
:
477 insn
= aarch64_insn_get_blr_value();
479 case AARCH64_INSN_BRANCH_RETURN
:
480 insn
= aarch64_insn_get_ret_value();
484 return AARCH64_BREAK_FAULT
;
487 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN
, insn
, reg
);
490 u32
aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg
,
491 enum aarch64_insn_register base
,
492 enum aarch64_insn_register offset
,
493 enum aarch64_insn_size_type size
,
494 enum aarch64_insn_ldst_type type
)
499 case AARCH64_INSN_LDST_LOAD_REG_OFFSET
:
500 insn
= aarch64_insn_get_ldr_reg_value();
502 case AARCH64_INSN_LDST_STORE_REG_OFFSET
:
503 insn
= aarch64_insn_get_str_reg_value();
507 return AARCH64_BREAK_FAULT
;
510 insn
= aarch64_insn_encode_ldst_size(size
, insn
);
512 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT
, insn
, reg
);
514 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN
, insn
,
517 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM
, insn
,
521 u32
aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1
,
522 enum aarch64_insn_register reg2
,
523 enum aarch64_insn_register base
,
525 enum aarch64_insn_variant variant
,
526 enum aarch64_insn_ldst_type type
)
532 case AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX
:
533 insn
= aarch64_insn_get_ldp_pre_value();
535 case AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX
:
536 insn
= aarch64_insn_get_stp_pre_value();
538 case AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX
:
539 insn
= aarch64_insn_get_ldp_post_value();
541 case AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX
:
542 insn
= aarch64_insn_get_stp_post_value();
546 return AARCH64_BREAK_FAULT
;
550 case AARCH64_INSN_VARIANT_32BIT
:
551 /* offset must be multiples of 4 in the range [-256, 252] */
552 BUG_ON(offset
& 0x3);
553 BUG_ON(offset
< -256 || offset
> 252);
556 case AARCH64_INSN_VARIANT_64BIT
:
557 /* offset must be multiples of 8 in the range [-512, 504] */
558 BUG_ON(offset
& 0x7);
559 BUG_ON(offset
< -512 || offset
> 504);
561 insn
|= AARCH64_INSN_SF_BIT
;
565 return AARCH64_BREAK_FAULT
;
568 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT
, insn
,
571 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT2
, insn
,
574 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN
, insn
,
577 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_7
, insn
,
581 u32
aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst
,
582 enum aarch64_insn_register src
,
583 int imm
, enum aarch64_insn_variant variant
,
584 enum aarch64_insn_adsb_type type
)
589 case AARCH64_INSN_ADSB_ADD
:
590 insn
= aarch64_insn_get_add_imm_value();
592 case AARCH64_INSN_ADSB_SUB
:
593 insn
= aarch64_insn_get_sub_imm_value();
595 case AARCH64_INSN_ADSB_ADD_SETFLAGS
:
596 insn
= aarch64_insn_get_adds_imm_value();
598 case AARCH64_INSN_ADSB_SUB_SETFLAGS
:
599 insn
= aarch64_insn_get_subs_imm_value();
603 return AARCH64_BREAK_FAULT
;
607 case AARCH64_INSN_VARIANT_32BIT
:
609 case AARCH64_INSN_VARIANT_64BIT
:
610 insn
|= AARCH64_INSN_SF_BIT
;
614 return AARCH64_BREAK_FAULT
;
617 BUG_ON(imm
& ~(SZ_4K
- 1));
619 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD
, insn
, dst
);
621 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN
, insn
, src
);
623 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12
, insn
, imm
);
626 u32
aarch64_insn_gen_bitfield(enum aarch64_insn_register dst
,
627 enum aarch64_insn_register src
,
629 enum aarch64_insn_variant variant
,
630 enum aarch64_insn_bitfield_type type
)
636 case AARCH64_INSN_BITFIELD_MOVE
:
637 insn
= aarch64_insn_get_bfm_value();
639 case AARCH64_INSN_BITFIELD_MOVE_UNSIGNED
:
640 insn
= aarch64_insn_get_ubfm_value();
642 case AARCH64_INSN_BITFIELD_MOVE_SIGNED
:
643 insn
= aarch64_insn_get_sbfm_value();
647 return AARCH64_BREAK_FAULT
;
651 case AARCH64_INSN_VARIANT_32BIT
:
652 mask
= GENMASK(4, 0);
654 case AARCH64_INSN_VARIANT_64BIT
:
655 insn
|= AARCH64_INSN_SF_BIT
| AARCH64_INSN_N_BIT
;
656 mask
= GENMASK(5, 0);
660 return AARCH64_BREAK_FAULT
;
663 BUG_ON(immr
& ~mask
);
664 BUG_ON(imms
& ~mask
);
666 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD
, insn
, dst
);
668 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN
, insn
, src
);
670 insn
= aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R
, insn
, immr
);
672 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S
, insn
, imms
);
675 u32
aarch64_insn_gen_movewide(enum aarch64_insn_register dst
,
677 enum aarch64_insn_variant variant
,
678 enum aarch64_insn_movewide_type type
)
683 case AARCH64_INSN_MOVEWIDE_ZERO
:
684 insn
= aarch64_insn_get_movz_value();
686 case AARCH64_INSN_MOVEWIDE_KEEP
:
687 insn
= aarch64_insn_get_movk_value();
689 case AARCH64_INSN_MOVEWIDE_INVERSE
:
690 insn
= aarch64_insn_get_movn_value();
694 return AARCH64_BREAK_FAULT
;
697 BUG_ON(imm
& ~(SZ_64K
- 1));
700 case AARCH64_INSN_VARIANT_32BIT
:
701 BUG_ON(shift
!= 0 && shift
!= 16);
703 case AARCH64_INSN_VARIANT_64BIT
:
704 insn
|= AARCH64_INSN_SF_BIT
;
705 BUG_ON(shift
!= 0 && shift
!= 16 && shift
!= 32 &&
710 return AARCH64_BREAK_FAULT
;
713 insn
|= (shift
>> 4) << 21;
715 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD
, insn
, dst
);
717 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16
, insn
, imm
);
720 u32
aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst
,
721 enum aarch64_insn_register src
,
722 enum aarch64_insn_register reg
,
724 enum aarch64_insn_variant variant
,
725 enum aarch64_insn_adsb_type type
)
730 case AARCH64_INSN_ADSB_ADD
:
731 insn
= aarch64_insn_get_add_value();
733 case AARCH64_INSN_ADSB_SUB
:
734 insn
= aarch64_insn_get_sub_value();
736 case AARCH64_INSN_ADSB_ADD_SETFLAGS
:
737 insn
= aarch64_insn_get_adds_value();
739 case AARCH64_INSN_ADSB_SUB_SETFLAGS
:
740 insn
= aarch64_insn_get_subs_value();
744 return AARCH64_BREAK_FAULT
;
748 case AARCH64_INSN_VARIANT_32BIT
:
749 BUG_ON(shift
& ~(SZ_32
- 1));
751 case AARCH64_INSN_VARIANT_64BIT
:
752 insn
|= AARCH64_INSN_SF_BIT
;
753 BUG_ON(shift
& ~(SZ_64
- 1));
757 return AARCH64_BREAK_FAULT
;
761 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD
, insn
, dst
);
763 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN
, insn
, src
);
765 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM
, insn
, reg
);
767 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6
, insn
, shift
);
770 u32
aarch64_insn_gen_data1(enum aarch64_insn_register dst
,
771 enum aarch64_insn_register src
,
772 enum aarch64_insn_variant variant
,
773 enum aarch64_insn_data1_type type
)
778 case AARCH64_INSN_DATA1_REVERSE_16
:
779 insn
= aarch64_insn_get_rev16_value();
781 case AARCH64_INSN_DATA1_REVERSE_32
:
782 insn
= aarch64_insn_get_rev32_value();
784 case AARCH64_INSN_DATA1_REVERSE_64
:
785 BUG_ON(variant
!= AARCH64_INSN_VARIANT_64BIT
);
786 insn
= aarch64_insn_get_rev64_value();
790 return AARCH64_BREAK_FAULT
;
794 case AARCH64_INSN_VARIANT_32BIT
:
796 case AARCH64_INSN_VARIANT_64BIT
:
797 insn
|= AARCH64_INSN_SF_BIT
;
801 return AARCH64_BREAK_FAULT
;
804 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD
, insn
, dst
);
806 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN
, insn
, src
);
809 u32
aarch64_insn_gen_data2(enum aarch64_insn_register dst
,
810 enum aarch64_insn_register src
,
811 enum aarch64_insn_register reg
,
812 enum aarch64_insn_variant variant
,
813 enum aarch64_insn_data2_type type
)
818 case AARCH64_INSN_DATA2_UDIV
:
819 insn
= aarch64_insn_get_udiv_value();
821 case AARCH64_INSN_DATA2_SDIV
:
822 insn
= aarch64_insn_get_sdiv_value();
824 case AARCH64_INSN_DATA2_LSLV
:
825 insn
= aarch64_insn_get_lslv_value();
827 case AARCH64_INSN_DATA2_LSRV
:
828 insn
= aarch64_insn_get_lsrv_value();
830 case AARCH64_INSN_DATA2_ASRV
:
831 insn
= aarch64_insn_get_asrv_value();
833 case AARCH64_INSN_DATA2_RORV
:
834 insn
= aarch64_insn_get_rorv_value();
838 return AARCH64_BREAK_FAULT
;
842 case AARCH64_INSN_VARIANT_32BIT
:
844 case AARCH64_INSN_VARIANT_64BIT
:
845 insn
|= AARCH64_INSN_SF_BIT
;
849 return AARCH64_BREAK_FAULT
;
852 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD
, insn
, dst
);
854 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN
, insn
, src
);
856 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM
, insn
, reg
);
859 u32
aarch64_insn_gen_data3(enum aarch64_insn_register dst
,
860 enum aarch64_insn_register src
,
861 enum aarch64_insn_register reg1
,
862 enum aarch64_insn_register reg2
,
863 enum aarch64_insn_variant variant
,
864 enum aarch64_insn_data3_type type
)
869 case AARCH64_INSN_DATA3_MADD
:
870 insn
= aarch64_insn_get_madd_value();
872 case AARCH64_INSN_DATA3_MSUB
:
873 insn
= aarch64_insn_get_msub_value();
877 return AARCH64_BREAK_FAULT
;
881 case AARCH64_INSN_VARIANT_32BIT
:
883 case AARCH64_INSN_VARIANT_64BIT
:
884 insn
|= AARCH64_INSN_SF_BIT
;
888 return AARCH64_BREAK_FAULT
;
891 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD
, insn
, dst
);
893 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RA
, insn
, src
);
895 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN
, insn
,
898 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM
, insn
,
902 u32
aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst
,
903 enum aarch64_insn_register src
,
904 enum aarch64_insn_register reg
,
906 enum aarch64_insn_variant variant
,
907 enum aarch64_insn_logic_type type
)
912 case AARCH64_INSN_LOGIC_AND
:
913 insn
= aarch64_insn_get_and_value();
915 case AARCH64_INSN_LOGIC_BIC
:
916 insn
= aarch64_insn_get_bic_value();
918 case AARCH64_INSN_LOGIC_ORR
:
919 insn
= aarch64_insn_get_orr_value();
921 case AARCH64_INSN_LOGIC_ORN
:
922 insn
= aarch64_insn_get_orn_value();
924 case AARCH64_INSN_LOGIC_EOR
:
925 insn
= aarch64_insn_get_eor_value();
927 case AARCH64_INSN_LOGIC_EON
:
928 insn
= aarch64_insn_get_eon_value();
930 case AARCH64_INSN_LOGIC_AND_SETFLAGS
:
931 insn
= aarch64_insn_get_ands_value();
933 case AARCH64_INSN_LOGIC_BIC_SETFLAGS
:
934 insn
= aarch64_insn_get_bics_value();
938 return AARCH64_BREAK_FAULT
;
942 case AARCH64_INSN_VARIANT_32BIT
:
943 BUG_ON(shift
& ~(SZ_32
- 1));
945 case AARCH64_INSN_VARIANT_64BIT
:
946 insn
|= AARCH64_INSN_SF_BIT
;
947 BUG_ON(shift
& ~(SZ_64
- 1));
951 return AARCH64_BREAK_FAULT
;
955 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD
, insn
, dst
);
957 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN
, insn
, src
);
959 insn
= aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM
, insn
, reg
);
961 return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_6
, insn
, shift
);