arch/arm64/kernel/setup.c

   1 /*
   2  * Based on arch/arm/kernel/setup.c
   3  *
   4  * Copyright (C) 1995-2001 Russell King
   5  * Copyright (C) 2012 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/export.h>
  21 #include <linux/kernel.h>
  22 #include <linux/stddef.h>
  23 #include <linux/ioport.h>
  24 #include <linux/delay.h>
  25 #include <linux/utsname.h>
  26 #include <linux/initrd.h>
  27 #include <linux/console.h>
  28 #include <linux/cache.h>
  29 #include <linux/bootmem.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/screen_info.h>
  32 #include <linux/init.h>
  33 #include <linux/kexec.h>
  34 #include <linux/crash_dump.h>
  35 #include <linux/root_dev.h>
  36 #include <linux/clk-provider.h>
  37 #include <linux/cpu.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/smp.h>
  40 #include <linux/fs.h>
  41 #include <linux/proc_fs.h>
  42 #include <linux/memblock.h>
  43 #include <linux/of_fdt.h>
  44 #include <linux/of_platform.h>
  45 #include <linux/efi.h>
  46
  47 #include <asm/fixmap.h>
  48 #include <asm/cpu.h>
  49 #include <asm/cputype.h>
  50 #include <asm/elf.h>
  51 #include <asm/cputable.h>
  52 #include <asm/cpu_ops.h>
  53 #include <asm/sections.h>
  54 #include <asm/setup.h>
  55 #include <asm/smp_plat.h>
  56 #include <asm/cacheflush.h>
  57 #include <asm/tlbflush.h>
  58 #include <asm/traps.h>
  59 #include <asm/memblock.h>
  60 #include <asm/psci.h>
  61 #include <asm/efi.h>
  62
  63 unsigned int processor_id;
  64 EXPORT_SYMBOL(processor_id);
  65
  66 unsigned long elf_hwcap __read_mostly;
  67 EXPORT_SYMBOL_GPL(elf_hwcap);
  68
  69 #ifdef CONFIG_COMPAT
  70 #define COMPAT_ELF_HWCAP_DEFAULT        \
  71                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  72                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  73                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  74                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  75                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV)
  76 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  77 unsigned int compat_elf_hwcap2 __read_mostly;
  78 #endif
  79
  80 static const char *cpu_name;
  81 static const char *machine_name;
  82 phys_addr_t __fdt_pointer __initdata;
  83
  84 /*
  85  * Standard memory resources
  86  */
  87 static struct resource mem_res[] = {
  88         {
  89                 .name = "Kernel code",
  90                 .start = 0,
  91                 .end = 0,
  92                 .flags = IORESOURCE_MEM
  93         },
  94         {
  95                 .name = "Kernel data",
  96                 .start = 0,
  97                 .end = 0,
  98                 .flags = IORESOURCE_MEM
  99         }
 100 };
 101
 102 #define kernel_code mem_res[0]
 103 #define kernel_data mem_res[1]
 104
 105 void __init early_print(const char *str, ...)
 106 {
 107         char buf[256];
 108         va_list ap;
 109
 110         va_start(ap, str);
 111         vsnprintf(buf, sizeof(buf), str, ap);
 112         va_end(ap);
 113
 114         printk("%s", buf);
 115 }
 116
 117 void __init smp_setup_processor_id(void)
 118 {
 119         /*
 120          * clear __my_cpu_offset on boot CPU to avoid hang caused by
 121          * using percpu variable early, for example, lockdep will
 122          * access percpu variable inside lock_release
 123          */
 124         set_my_cpu_offset(0);
 125 }
 126
 127 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
 128 {
 129         return phys_id == cpu_logical_map(cpu);
 130 }
 131
 132 struct mpidr_hash mpidr_hash;
 133 #ifdef CONFIG_SMP
 134 /**
 135  * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
 136  *                        level in order to build a linear index from an
 137  *                        MPIDR value. Resulting algorithm is a collision
 138  *                        free hash carried out through shifting and ORing
 139  */
 140 static void __init smp_build_mpidr_hash(void)
 141 {
 142         u32 i, affinity, fs[4], bits[4], ls;
 143         u64 mask = 0;
 144         /*
 145          * Pre-scan the list of MPIDRS and filter out bits that do
 146          * not contribute to affinity levels, ie they never toggle.
 147          */
 148         for_each_possible_cpu(i)
 149                 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
 150         pr_debug("mask of set bits %#llx\n", mask);
 151         /*
 152          * Find and stash the last and first bit set at all affinity levels to
 153          * check how many bits are required to represent them.
 154          */
 155         for (i = 0; i < 4; i++) {
 156                 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
 157                 /*
 158                  * Find the MSB bit and LSB bits position
 159                  * to determine how many bits are required
 160                  * to express the affinity level.
 161                  */
 162                 ls = fls(affinity);
 163                 fs[i] = affinity ? ffs(affinity) - 1 : 0;
 164                 bits[i] = ls - fs[i];
 165         }
 166         /*
 167          * An index can be created from the MPIDR_EL1 by isolating the
 168          * significant bits at each affinity level and by shifting
 169          * them in order to compress the 32 bits values space to a
 170          * compressed set of values. This is equivalent to hashing
 171          * the MPIDR_EL1 through shifting and ORing. It is a collision free
 172          * hash though not minimal since some levels might contain a number
 173          * of CPUs that is not an exact power of 2 and their bit
 174          * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
 175          */
 176         mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
 177         mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
 178         mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
 179                                                 (bits[1] + bits[0]);
 180         mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
 181                                   fs[3] - (bits[2] + bits[1] + bits[0]);
 182         mpidr_hash.mask = mask;
 183         mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
 184         pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
 185                 mpidr_hash.shift_aff[0],
 186                 mpidr_hash.shift_aff[1],
 187                 mpidr_hash.shift_aff[2],
 188                 mpidr_hash.shift_aff[3],
 189                 mpidr_hash.mask,
 190                 mpidr_hash.bits);
 191         /*
 192          * 4x is an arbitrary value used to warn on a hash table much bigger
 193          * than expected on most systems.
 194          */
 195         if (mpidr_hash_size() > 4 * num_possible_cpus())
 196                 pr_warn("Large number of MPIDR hash buckets detected\n");
 197         __flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash));
 198 }
 199 #endif
 200
 201 static void __init setup_processor(void)
 202 {
 203         struct cpu_info *cpu_info;
 204         u64 features, block;
 205         u32 cwg;
 206         int cls;
 207
 208         cpu_info = lookup_processor_type(read_cpuid_id());
 209         if (!cpu_info) {
 210                 printk("CPU configuration botched (ID %08x), unable to continue.\n",
 211                        read_cpuid_id());
 212                 while (1);
 213         }
 214
 215         cpu_name = cpu_info->cpu_name;
 216
 217         printk("CPU: %s [%08x] revision %d\n",
 218                cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
 219
 220         sprintf(init_utsname()->machine, ELF_PLATFORM);
 221         elf_hwcap = 0;
 222
 223         cpuinfo_store_boot_cpu();
 224
 225         /*
 226          * Check for sane CTR_EL0.CWG value.
 227          */
 228         cwg = cache_type_cwg();
 229         cls = cache_line_size();
 230         if (!cwg)
 231                 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
 232                         cls);
 233         if (L1_CACHE_BYTES < cls)
 234                 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
 235                         L1_CACHE_BYTES, cls);
 236
 237         /*
 238          * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
 239          * The blocks we test below represent incremental functionality
 240          * for non-negative values. Negative values are reserved.
 241          */
 242         features = read_cpuid(ID_AA64ISAR0_EL1);
 243         block = (features >> 4) & 0xf;
 244         if (!(block & 0x8)) {
 245                 switch (block) {
 246                 default:
 247                 case 2:
 248                         elf_hwcap |= HWCAP_PMULL;
 249                 case 1:
 250                         elf_hwcap |= HWCAP_AES;
 251                 case 0:
 252                         break;
 253                 }
 254         }
 255
 256         block = (features >> 8) & 0xf;
 257         if (block && !(block & 0x8))
 258                 elf_hwcap |= HWCAP_SHA1;
 259
 260         block = (features >> 12) & 0xf;
 261         if (block && !(block & 0x8))
 262                 elf_hwcap |= HWCAP_SHA2;
 263
 264         block = (features >> 16) & 0xf;
 265         if (block && !(block & 0x8))
 266                 elf_hwcap |= HWCAP_CRC32;
 267
 268 #ifdef CONFIG_COMPAT
 269         /*
 270          * ID_ISAR5_EL1 carries similar information as above, but pertaining to
 271          * the Aarch32 32-bit execution state.
 272          */
 273         features = read_cpuid(ID_ISAR5_EL1);
 274         block = (features >> 4) & 0xf;
 275         if (!(block & 0x8)) {
 276                 switch (block) {
 277                 default:
 278                 case 2:
 279                         compat_elf_hwcap2 |= COMPAT_HWCAP2_PMULL;
 280                 case 1:
 281                         compat_elf_hwcap2 |= COMPAT_HWCAP2_AES;
 282                 case 0:
 283                         break;
 284                 }
 285         }
 286
 287         block = (features >> 8) & 0xf;
 288         if (block && !(block & 0x8))
 289                 compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA1;
 290
 291         block = (features >> 12) & 0xf;
 292         if (block && !(block & 0x8))
 293                 compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA2;
 294
 295         block = (features >> 16) & 0xf;
 296         if (block && !(block & 0x8))
 297                 compat_elf_hwcap2 |= COMPAT_HWCAP2_CRC32;
 298 #endif
 299 }
 300
 301 static void __init setup_machine_fdt(phys_addr_t dt_phys)
 302 {
 303         if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) {
 304                 early_print("\n"
 305                         "Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n"
 306                         "The dtb must be 8-byte aligned and passed in the first 512MB of memory\n"
 307                         "\nPlease check your bootloader.\n",
 308                         dt_phys, phys_to_virt(dt_phys));
 309
 310                 while (true)
 311                         cpu_relax();
 312         }
 313
 314         machine_name = of_flat_dt_get_machine_name();
 315         dump_stack_set_arch_desc("%s (DT)", machine_name);
 316 }
 317
 318 /*
 319  * Limit the memory size that was specified via FDT.
 320  */
 321 static int __init early_mem(char *p)
 322 {
 323         phys_addr_t limit;
 324
 325         if (!p)
 326                 return 1;
 327
 328         limit = memparse(p, &p) & PAGE_MASK;
 329         pr_notice("Memory limited to %lldMB\n", limit >> 20);
 330
 331         memblock_enforce_memory_limit(limit);
 332
 333         return 0;
 334 }
 335 early_param("mem", early_mem);
 336
 337 static void __init request_standard_resources(void)
 338 {
 339         struct memblock_region *region;
 340         struct resource *res;
 341
 342         kernel_code.start   = virt_to_phys(_text);
 343         kernel_code.end     = virt_to_phys(_etext - 1);
 344         kernel_data.start   = virt_to_phys(_sdata);
 345         kernel_data.end     = virt_to_phys(_end - 1);
 346
 347         for_each_memblock(memory, region) {
 348                 res = alloc_bootmem_low(sizeof(*res));
 349                 res->name  = "System RAM";
 350                 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
 351                 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
 352                 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
 353
 354                 request_resource(&iomem_resource, res);
 355
 356                 if (kernel_code.start >= res->start &&
 357                     kernel_code.end <= res->end)
 358                         request_resource(res, &kernel_code);
 359                 if (kernel_data.start >= res->start &&
 360                     kernel_data.end <= res->end)
 361                         request_resource(res, &kernel_data);
 362         }
 363 }
 364
 365 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
 366
 367 void __init setup_arch(char **cmdline_p)
 368 {
 369         setup_processor();
 370
 371         setup_machine_fdt(__fdt_pointer);
 372
 373         init_mm.start_code = (unsigned long) _text;
 374         init_mm.end_code   = (unsigned long) _etext;
 375         init_mm.end_data   = (unsigned long) _edata;
 376         init_mm.brk        = (unsigned long) _end;
 377
 378         *cmdline_p = boot_command_line;
 379
 380         early_ioremap_init();
 381
 382         parse_early_param();
 383
 384         /*
 385          *  Unmask asynchronous aborts after bringing up possible earlycon.
 386          * (Report possible System Errors once we can report this occurred)
 387          */
 388         local_async_enable();
 389
 390         efi_init();
 391         arm64_memblock_init();
 392
 393         paging_init();
 394         request_standard_resources();
 395
 396         efi_idmap_init();
 397
 398         unflatten_device_tree();
 399
 400         psci_init();
 401
 402         cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
 403         cpu_read_bootcpu_ops();
 404 #ifdef CONFIG_SMP
 405         smp_init_cpus();
 406         smp_build_mpidr_hash();
 407 #endif
 408
 409 #ifdef CONFIG_VT
 410 #if defined(CONFIG_VGA_CONSOLE)
 411         conswitchp = &vga_con;
 412 #elif defined(CONFIG_DUMMY_CONSOLE)
 413         conswitchp = &dummy_con;
 414 #endif
 415 #endif
 416 }
 417
 418 static int __init arm64_device_init(void)
 419 {
 420         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 421         return 0;
 422 }
 423 arch_initcall_sync(arm64_device_init);
 424
 425 static int __init topology_init(void)
 426 {
 427         int i;
 428
 429         for_each_possible_cpu(i) {
 430                 struct cpu *cpu = &per_cpu(cpu_data.cpu, i);
 431                 cpu->hotpluggable = 1;
 432                 register_cpu(cpu, i);
 433         }
 434
 435         return 0;
 436 }
 437 subsys_initcall(topology_init);
 438
 439 static const char *hwcap_str[] = {
 440         "fp",
 441         "asimd",
 442         "evtstrm",
 443         "aes",
 444         "pmull",
 445         "sha1",
 446         "sha2",
 447         "crc32",
 448         NULL
 449 };
 450
 451 static int c_show(struct seq_file *m, void *v)
 452 {
 453         int i;
 454
 455         seq_printf(m, "Processor\t: %s rev %d (%s)\n",
 456                    cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);
 457
 458         for_each_online_cpu(i) {
 459                 /*
 460                  * glibc reads /proc/cpuinfo to determine the number of
 461                  * online processors, looking for lines beginning with
 462                  * "processor".  Give glibc what it expects.
 463                  */
 464 #ifdef CONFIG_SMP
 465                 seq_printf(m, "processor\t: %d\n", i);
 466 #endif
 467         }
 468
 469         /* dump out the processor features */
 470         seq_puts(m, "Features\t: ");
 471
 472         for (i = 0; hwcap_str[i]; i++)
 473                 if (elf_hwcap & (1 << i))
 474                         seq_printf(m, "%s ", hwcap_str[i]);
 475
 476         seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
 477         seq_printf(m, "CPU architecture: AArch64\n");
 478         seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15);
 479         seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff);
 480         seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
 481
 482         seq_puts(m, "\n");
 483
 484         seq_printf(m, "Hardware\t: %s\n", machine_name);
 485
 486         return 0;
 487 }
 488
 489 static void *c_start(struct seq_file *m, loff_t *pos)
 490 {
 491         return *pos < 1 ? (void *)1 : NULL;
 492 }
 493
 494 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 495 {
 496         ++*pos;
 497         return NULL;
 498 }
 499
 500 static void c_stop(struct seq_file *m, void *v)
 501 {
 502 }
 503
 504 const struct seq_operations cpuinfo_op = {
 505         .start  = c_start,
 506         .next   = c_next,
 507         .stop   = c_stop,
 508         .show   = c_show
 509 };