2 * Copyright (C) 2015 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/types.h>
19 #include <linux/jump_label.h>
20 #include <uapi/linux/psci.h>
22 #include <asm/kvm_asm.h>
23 #include <asm/kvm_emulate.h>
24 #include <asm/kvm_hyp.h>
25 #include <asm/fpsimd.h>
26 #include <asm/debug-monitors.h>
28 static bool __hyp_text
__fpsimd_enabled_nvhe(void)
30 return !(read_sysreg(cptr_el2
) & CPTR_EL2_TFP
);
33 static bool __hyp_text
__fpsimd_enabled_vhe(void)
35 return !!(read_sysreg(cpacr_el1
) & CPACR_EL1_FPEN
);
38 static hyp_alternate_select(__fpsimd_is_enabled
,
39 __fpsimd_enabled_nvhe
, __fpsimd_enabled_vhe
,
40 ARM64_HAS_VIRT_HOST_EXTN
);
42 bool __hyp_text
__fpsimd_enabled(void)
44 return __fpsimd_is_enabled()();
47 static void __hyp_text
__activate_traps_vhe(void)
51 val
= read_sysreg(cpacr_el1
);
53 val
&= ~(CPACR_EL1_FPEN
| CPACR_EL1_ZEN
);
54 write_sysreg(val
, cpacr_el1
);
56 write_sysreg(kvm_get_hyp_vector(), vbar_el1
);
59 static void __hyp_text
__activate_traps_nvhe(void)
63 val
= CPTR_EL2_DEFAULT
;
64 val
|= CPTR_EL2_TTA
| CPTR_EL2_TFP
| CPTR_EL2_TZ
;
65 write_sysreg(val
, cptr_el2
);
68 static hyp_alternate_select(__activate_traps_arch
,
69 __activate_traps_nvhe
, __activate_traps_vhe
,
70 ARM64_HAS_VIRT_HOST_EXTN
);
72 static void __hyp_text
__activate_traps(struct kvm_vcpu
*vcpu
)
77 * We are about to set CPTR_EL2.TFP to trap all floating point
78 * register accesses to EL2, however, the ARM ARM clearly states that
79 * traps are only taken to EL2 if the operation would not otherwise
80 * trap to EL1. Therefore, always make sure that for 32-bit guests,
81 * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
82 * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
83 * it will cause an exception.
85 val
= vcpu
->arch
.hcr_el2
;
87 if (!(val
& HCR_RW
) && system_supports_fpsimd()) {
88 write_sysreg(1 << 30, fpexc32_el2
);
92 if (val
& HCR_RW
) /* for AArch64 only: */
93 val
|= HCR_TID3
; /* TID3: trap feature register accesses */
95 write_sysreg(val
, hcr_el2
);
97 if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN
) && (val
& HCR_VSE
))
98 write_sysreg_s(vcpu
->arch
.vsesr_el2
, SYS_VSESR_EL2
);
100 /* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */
101 write_sysreg(1 << 15, hstr_el2
);
103 * Make sure we trap PMU access from EL0 to EL2. Also sanitize
104 * PMSELR_EL0 to make sure it never contains the cycle
105 * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
106 * EL1 instead of being trapped to EL2.
108 write_sysreg(0, pmselr_el0
);
109 write_sysreg(ARMV8_PMU_USERENR_MASK
, pmuserenr_el0
);
110 write_sysreg(vcpu
->arch
.mdcr_el2
, mdcr_el2
);
111 __activate_traps_arch()();
114 static void __hyp_text
__deactivate_traps_vhe(void)
116 extern char vectors
[]; /* kernel exception vectors */
117 u64 mdcr_el2
= read_sysreg(mdcr_el2
);
119 mdcr_el2
&= MDCR_EL2_HPMN_MASK
|
120 MDCR_EL2_E2PB_MASK
<< MDCR_EL2_E2PB_SHIFT
|
123 write_sysreg(mdcr_el2
, mdcr_el2
);
124 write_sysreg(HCR_HOST_VHE_FLAGS
, hcr_el2
);
125 write_sysreg(CPACR_EL1_DEFAULT
, cpacr_el1
);
126 write_sysreg(vectors
, vbar_el1
);
129 static void __hyp_text
__deactivate_traps_nvhe(void)
131 u64 mdcr_el2
= read_sysreg(mdcr_el2
);
133 mdcr_el2
&= MDCR_EL2_HPMN_MASK
;
134 mdcr_el2
|= MDCR_EL2_E2PB_MASK
<< MDCR_EL2_E2PB_SHIFT
;
136 write_sysreg(mdcr_el2
, mdcr_el2
);
137 write_sysreg(HCR_RW
, hcr_el2
);
138 write_sysreg(CPTR_EL2_DEFAULT
, cptr_el2
);
141 static hyp_alternate_select(__deactivate_traps_arch
,
142 __deactivate_traps_nvhe
, __deactivate_traps_vhe
,
143 ARM64_HAS_VIRT_HOST_EXTN
);
145 static void __hyp_text
__deactivate_traps(struct kvm_vcpu
*vcpu
)
148 * If we pended a virtual abort, preserve it until it gets
149 * cleared. See D1.14.3 (Virtual Interrupts) for details, but
150 * the crucial bit is "On taking a vSError interrupt,
151 * HCR_EL2.VSE is cleared to 0."
153 if (vcpu
->arch
.hcr_el2
& HCR_VSE
)
154 vcpu
->arch
.hcr_el2
= read_sysreg(hcr_el2
);
156 __deactivate_traps_arch()();
157 write_sysreg(0, hstr_el2
);
158 write_sysreg(0, pmuserenr_el0
);
161 static void __hyp_text
__activate_vm(struct kvm_vcpu
*vcpu
)
163 struct kvm
*kvm
= kern_hyp_va(vcpu
->kvm
);
164 write_sysreg(kvm
->arch
.vttbr
, vttbr_el2
);
167 static void __hyp_text
__deactivate_vm(struct kvm_vcpu
*vcpu
)
169 write_sysreg(0, vttbr_el2
);
172 static void __hyp_text
__vgic_save_state(struct kvm_vcpu
*vcpu
)
174 if (static_branch_unlikely(&kvm_vgic_global_state
.gicv3_cpuif
))
175 __vgic_v3_save_state(vcpu
);
177 __vgic_v2_save_state(vcpu
);
179 write_sysreg(read_sysreg(hcr_el2
) & ~HCR_INT_OVERRIDE
, hcr_el2
);
182 static void __hyp_text
__vgic_restore_state(struct kvm_vcpu
*vcpu
)
186 val
= read_sysreg(hcr_el2
);
187 val
|= HCR_INT_OVERRIDE
;
188 val
|= vcpu
->arch
.irq_lines
;
189 write_sysreg(val
, hcr_el2
);
191 if (static_branch_unlikely(&kvm_vgic_global_state
.gicv3_cpuif
))
192 __vgic_v3_restore_state(vcpu
);
194 __vgic_v2_restore_state(vcpu
);
197 static bool __hyp_text
__true_value(void)
202 static bool __hyp_text
__false_value(void)
207 static hyp_alternate_select(__check_arm_834220
,
208 __false_value
, __true_value
,
209 ARM64_WORKAROUND_834220
);
211 static bool __hyp_text
__translate_far_to_hpfar(u64 far
, u64
*hpfar
)
216 * Resolve the IPA the hard way using the guest VA.
218 * Stage-1 translation already validated the memory access
219 * rights. As such, we can use the EL1 translation regime, and
220 * don't have to distinguish between EL0 and EL1 access.
222 * We do need to save/restore PAR_EL1 though, as we haven't
223 * saved the guest context yet, and we may return early...
225 par
= read_sysreg(par_el1
);
226 asm volatile("at s1e1r, %0" : : "r" (far
));
229 tmp
= read_sysreg(par_el1
);
230 write_sysreg(par
, par_el1
);
232 if (unlikely(tmp
& 1))
233 return false; /* Translation failed, back to guest */
235 /* Convert PAR to HPFAR format */
236 *hpfar
= ((tmp
>> 12) & ((1UL << 36) - 1)) << 4;
240 static bool __hyp_text
__populate_fault_info(struct kvm_vcpu
*vcpu
)
246 esr
= vcpu
->arch
.fault
.esr_el2
;
247 ec
= ESR_ELx_EC(esr
);
249 if (ec
!= ESR_ELx_EC_DABT_LOW
&& ec
!= ESR_ELx_EC_IABT_LOW
)
252 far
= read_sysreg_el2(far
);
255 * The HPFAR can be invalid if the stage 2 fault did not
256 * happen during a stage 1 page table walk (the ESR_EL2.S1PTW
257 * bit is clear) and one of the two following cases are true:
258 * 1. The fault was due to a permission fault
259 * 2. The processor carries errata 834220
261 * Therefore, for all non S1PTW faults where we either have a
262 * permission fault or the errata workaround is enabled, we
263 * resolve the IPA using the AT instruction.
265 if (!(esr
& ESR_ELx_S1PTW
) &&
266 (__check_arm_834220()() || (esr
& ESR_ELx_FSC_TYPE
) == FSC_PERM
)) {
267 if (!__translate_far_to_hpfar(far
, &hpfar
))
270 hpfar
= read_sysreg(hpfar_el2
);
273 vcpu
->arch
.fault
.far_el2
= far
;
274 vcpu
->arch
.fault
.hpfar_el2
= hpfar
;
278 /* Skip an instruction which has been emulated. Returns true if
279 * execution can continue or false if we need to exit hyp mode because
280 * single-step was in effect.
282 static bool __hyp_text
__skip_instr(struct kvm_vcpu
*vcpu
)
284 *vcpu_pc(vcpu
) = read_sysreg_el2(elr
);
286 if (vcpu_mode_is_32bit(vcpu
)) {
287 vcpu
->arch
.ctxt
.gp_regs
.regs
.pstate
= read_sysreg_el2(spsr
);
288 kvm_skip_instr32(vcpu
, kvm_vcpu_trap_il_is32bit(vcpu
));
289 write_sysreg_el2(vcpu
->arch
.ctxt
.gp_regs
.regs
.pstate
, spsr
);
294 write_sysreg_el2(*vcpu_pc(vcpu
), elr
);
296 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
) {
297 vcpu
->arch
.fault
.esr_el2
=
298 (ESR_ELx_EC_SOFTSTP_LOW
<< ESR_ELx_EC_SHIFT
) | 0x22;
305 int __hyp_text
__kvm_vcpu_run(struct kvm_vcpu
*vcpu
)
307 struct kvm_cpu_context
*host_ctxt
;
308 struct kvm_cpu_context
*guest_ctxt
;
312 vcpu
= kern_hyp_va(vcpu
);
314 host_ctxt
= kern_hyp_va(vcpu
->arch
.host_cpu_context
);
315 host_ctxt
->__hyp_running_vcpu
= vcpu
;
316 guest_ctxt
= &vcpu
->arch
.ctxt
;
318 __sysreg_save_host_state(host_ctxt
);
319 __debug_cond_save_host_state(vcpu
);
321 __activate_traps(vcpu
);
324 __vgic_restore_state(vcpu
);
325 __timer_enable_traps(vcpu
);
328 * We must restore the 32-bit state before the sysregs, thanks
329 * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
331 __sysreg32_restore_state(vcpu
);
332 __sysreg_restore_guest_state(guest_ctxt
);
333 __debug_restore_state(vcpu
, kern_hyp_va(vcpu
->arch
.debug_ptr
), guest_ctxt
);
335 /* Jump in the fire! */
337 exit_code
= __guest_enter(vcpu
, host_ctxt
);
338 /* And we're baaack! */
340 if (ARM_EXCEPTION_CODE(exit_code
) != ARM_EXCEPTION_IRQ
)
341 vcpu
->arch
.fault
.esr_el2
= read_sysreg_el2(esr
);
343 * We're using the raw exception code in order to only process
344 * the trap if no SError is pending. We will come back to the
345 * same PC once the SError has been injected, and replay the
346 * trapping instruction.
348 if (exit_code
== ARM_EXCEPTION_TRAP
&& !__populate_fault_info(vcpu
))
351 if (exit_code
== ARM_EXCEPTION_TRAP
&&
352 (kvm_vcpu_trap_get_class(vcpu
) == ESR_ELx_EC_HVC64
||
353 kvm_vcpu_trap_get_class(vcpu
) == ESR_ELx_EC_HVC32
) &&
354 vcpu_get_reg(vcpu
, 0) == PSCI_0_2_FN_PSCI_VERSION
) {
355 u64 val
= PSCI_RET_NOT_SUPPORTED
;
356 if (test_bit(KVM_ARM_VCPU_PSCI_0_2
, vcpu
->arch
.features
))
359 vcpu_set_reg(vcpu
, 0, val
);
363 if (static_branch_unlikely(&vgic_v2_cpuif_trap
) &&
364 exit_code
== ARM_EXCEPTION_TRAP
) {
367 valid
= kvm_vcpu_trap_get_class(vcpu
) == ESR_ELx_EC_DABT_LOW
&&
368 kvm_vcpu_trap_get_fault_type(vcpu
) == FSC_FAULT
&&
369 kvm_vcpu_dabt_isvalid(vcpu
) &&
370 !kvm_vcpu_dabt_isextabt(vcpu
) &&
371 !kvm_vcpu_dabt_iss1tw(vcpu
);
374 int ret
= __vgic_v2_perform_cpuif_access(vcpu
);
377 if (__skip_instr(vcpu
))
380 exit_code
= ARM_EXCEPTION_TRAP
;
384 /* Promote an illegal access to an
385 * SError. If we would be returning
386 * due to single-step clear the SS
387 * bit so handle_exit knows what to
388 * do after dealing with the error.
390 if (!__skip_instr(vcpu
))
391 *vcpu_cpsr(vcpu
) &= ~DBG_SPSR_SS
;
392 exit_code
= ARM_EXCEPTION_EL1_SERROR
;
395 /* 0 falls through to be handler out of EL2 */
399 if (static_branch_unlikely(&vgic_v3_cpuif_trap
) &&
400 exit_code
== ARM_EXCEPTION_TRAP
&&
401 (kvm_vcpu_trap_get_class(vcpu
) == ESR_ELx_EC_SYS64
||
402 kvm_vcpu_trap_get_class(vcpu
) == ESR_ELx_EC_CP15_32
)) {
403 int ret
= __vgic_v3_perform_cpuif_access(vcpu
);
406 if (__skip_instr(vcpu
))
409 exit_code
= ARM_EXCEPTION_TRAP
;
412 /* 0 falls through to be handled out of EL2 */
415 if (cpus_have_const_cap(ARM64_HARDEN_BP_POST_GUEST_EXIT
)) {
416 u32 midr
= read_cpuid_id();
418 /* Apply BTAC predictors mitigation to all Falkor chips */
419 if ((midr
& MIDR_CPU_MODEL_MASK
) == MIDR_QCOM_FALKOR_V1
)
420 __qcom_hyp_sanitize_btac_predictors();
423 fp_enabled
= __fpsimd_enabled();
425 __sysreg_save_guest_state(guest_ctxt
);
426 __sysreg32_save_state(vcpu
);
427 __timer_disable_traps(vcpu
);
428 __vgic_save_state(vcpu
);
430 __deactivate_traps(vcpu
);
431 __deactivate_vm(vcpu
);
433 __sysreg_restore_host_state(host_ctxt
);
436 __fpsimd_save_state(&guest_ctxt
->gp_regs
.fp_regs
);
437 __fpsimd_restore_state(&host_ctxt
->gp_regs
.fp_regs
);
440 __debug_save_state(vcpu
, kern_hyp_va(vcpu
->arch
.debug_ptr
), guest_ctxt
);
442 * This must come after restoring the host sysregs, since a non-VHE
443 * system may enable SPE here and make use of the TTBRs.
445 __debug_cond_restore_host_state(vcpu
);
450 static const char __hyp_panic_string
[] = "HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n";
452 static void __hyp_text
__hyp_call_panic_nvhe(u64 spsr
, u64 elr
, u64 par
,
453 struct kvm_vcpu
*vcpu
)
455 unsigned long str_va
;
458 * Force the panic string to be loaded from the literal pool,
459 * making sure it is a kernel address and not a PC-relative
462 asm volatile("ldr %0, =__hyp_panic_string" : "=r" (str_va
));
464 __hyp_do_panic(str_va
,
466 read_sysreg(esr_el2
), read_sysreg_el2(far
),
467 read_sysreg(hpfar_el2
), par
, vcpu
);
470 static void __hyp_text
__hyp_call_panic_vhe(u64 spsr
, u64 elr
, u64 par
,
471 struct kvm_vcpu
*vcpu
)
473 panic(__hyp_panic_string
,
475 read_sysreg_el2(esr
), read_sysreg_el2(far
),
476 read_sysreg(hpfar_el2
), par
, vcpu
);
479 static hyp_alternate_select(__hyp_call_panic
,
480 __hyp_call_panic_nvhe
, __hyp_call_panic_vhe
,
481 ARM64_HAS_VIRT_HOST_EXTN
);
483 void __hyp_text __noreturn
hyp_panic(struct kvm_cpu_context
*__host_ctxt
)
485 struct kvm_vcpu
*vcpu
= NULL
;
487 u64 spsr
= read_sysreg_el2(spsr
);
488 u64 elr
= read_sysreg_el2(elr
);
489 u64 par
= read_sysreg(par_el1
);
491 if (read_sysreg(vttbr_el2
)) {
492 struct kvm_cpu_context
*host_ctxt
;
494 host_ctxt
= kern_hyp_va(__host_ctxt
);
495 vcpu
= host_ctxt
->__hyp_running_vcpu
;
496 __timer_disable_traps(vcpu
);
497 __deactivate_traps(vcpu
);
498 __deactivate_vm(vcpu
);
499 __sysreg_restore_host_state(host_ctxt
);
502 /* Call panic for real */
503 __hyp_call_panic()(spsr
, elr
, par
, vcpu
);