2 * Copyright (C) 2015 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/types.h>
19 #include <linux/jump_label.h>
20 #include <uapi/linux/psci.h>
22 #include <kvm/arm_psci.h>
24 #include <asm/kvm_asm.h>
25 #include <asm/kvm_emulate.h>
26 #include <asm/kvm_hyp.h>
27 #include <asm/fpsimd.h>
29 static bool __hyp_text
__fpsimd_enabled_nvhe(void)
31 return !(read_sysreg(cptr_el2
) & CPTR_EL2_TFP
);
34 static bool __hyp_text
__fpsimd_enabled_vhe(void)
36 return !!(read_sysreg(cpacr_el1
) & CPACR_EL1_FPEN
);
39 static hyp_alternate_select(__fpsimd_is_enabled
,
40 __fpsimd_enabled_nvhe
, __fpsimd_enabled_vhe
,
41 ARM64_HAS_VIRT_HOST_EXTN
);
43 bool __hyp_text
__fpsimd_enabled(void)
45 return __fpsimd_is_enabled()();
48 static void __hyp_text
__activate_traps_vhe(void)
52 val
= read_sysreg(cpacr_el1
);
54 val
&= ~CPACR_EL1_FPEN
;
55 write_sysreg(val
, cpacr_el1
);
57 write_sysreg(kvm_get_hyp_vector(), vbar_el1
);
60 static void __hyp_text
__activate_traps_nvhe(void)
64 val
= CPTR_EL2_DEFAULT
;
65 val
|= CPTR_EL2_TTA
| CPTR_EL2_TFP
;
66 write_sysreg(val
, cptr_el2
);
69 static hyp_alternate_select(__activate_traps_arch
,
70 __activate_traps_nvhe
, __activate_traps_vhe
,
71 ARM64_HAS_VIRT_HOST_EXTN
);
73 static void __hyp_text
__activate_traps(struct kvm_vcpu
*vcpu
)
78 * We are about to set CPTR_EL2.TFP to trap all floating point
79 * register accesses to EL2, however, the ARM ARM clearly states that
80 * traps are only taken to EL2 if the operation would not otherwise
81 * trap to EL1. Therefore, always make sure that for 32-bit guests,
82 * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
83 * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
84 * it will cause an exception.
86 val
= vcpu
->arch
.hcr_el2
;
87 if (!(val
& HCR_RW
) && system_supports_fpsimd()) {
88 write_sysreg(1 << 30, fpexc32_el2
);
91 write_sysreg(val
, hcr_el2
);
92 /* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */
93 write_sysreg(1 << 15, hstr_el2
);
95 * Make sure we trap PMU access from EL0 to EL2. Also sanitize
96 * PMSELR_EL0 to make sure it never contains the cycle
97 * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
98 * EL1 instead of being trapped to EL2.
100 write_sysreg(0, pmselr_el0
);
101 write_sysreg(ARMV8_PMU_USERENR_MASK
, pmuserenr_el0
);
102 write_sysreg(vcpu
->arch
.mdcr_el2
, mdcr_el2
);
103 __activate_traps_arch()();
106 static void __hyp_text
__deactivate_traps_vhe(void)
108 extern char vectors
[]; /* kernel exception vectors */
109 u64 mdcr_el2
= read_sysreg(mdcr_el2
);
111 mdcr_el2
&= MDCR_EL2_HPMN_MASK
|
112 MDCR_EL2_E2PB_MASK
<< MDCR_EL2_E2PB_SHIFT
|
115 write_sysreg(mdcr_el2
, mdcr_el2
);
116 write_sysreg(HCR_HOST_VHE_FLAGS
, hcr_el2
);
117 write_sysreg(CPACR_EL1_FPEN
, cpacr_el1
);
118 write_sysreg(vectors
, vbar_el1
);
121 static void __hyp_text
__deactivate_traps_nvhe(void)
123 u64 mdcr_el2
= read_sysreg(mdcr_el2
);
125 mdcr_el2
&= MDCR_EL2_HPMN_MASK
;
126 mdcr_el2
|= MDCR_EL2_E2PB_MASK
<< MDCR_EL2_E2PB_SHIFT
;
128 write_sysreg(mdcr_el2
, mdcr_el2
);
129 write_sysreg(HCR_RW
, hcr_el2
);
130 write_sysreg(CPTR_EL2_DEFAULT
, cptr_el2
);
133 static hyp_alternate_select(__deactivate_traps_arch
,
134 __deactivate_traps_nvhe
, __deactivate_traps_vhe
,
135 ARM64_HAS_VIRT_HOST_EXTN
);
137 static void __hyp_text
__deactivate_traps(struct kvm_vcpu
*vcpu
)
140 * If we pended a virtual abort, preserve it until it gets
141 * cleared. See D1.14.3 (Virtual Interrupts) for details, but
142 * the crucial bit is "On taking a vSError interrupt,
143 * HCR_EL2.VSE is cleared to 0."
145 if (vcpu
->arch
.hcr_el2
& HCR_VSE
)
146 vcpu
->arch
.hcr_el2
= read_sysreg(hcr_el2
);
148 __deactivate_traps_arch()();
149 write_sysreg(0, hstr_el2
);
150 write_sysreg(0, pmuserenr_el0
);
153 static void __hyp_text
__activate_vm(struct kvm_vcpu
*vcpu
)
155 struct kvm
*kvm
= kern_hyp_va(vcpu
->kvm
);
156 write_sysreg(kvm
->arch
.vttbr
, vttbr_el2
);
159 static void __hyp_text
__deactivate_vm(struct kvm_vcpu
*vcpu
)
161 write_sysreg(0, vttbr_el2
);
164 static void __hyp_text
__vgic_save_state(struct kvm_vcpu
*vcpu
)
166 if (static_branch_unlikely(&kvm_vgic_global_state
.gicv3_cpuif
))
167 __vgic_v3_save_state(vcpu
);
169 __vgic_v2_save_state(vcpu
);
171 write_sysreg(read_sysreg(hcr_el2
) & ~HCR_INT_OVERRIDE
, hcr_el2
);
174 static void __hyp_text
__vgic_restore_state(struct kvm_vcpu
*vcpu
)
178 val
= read_sysreg(hcr_el2
);
179 val
|= HCR_INT_OVERRIDE
;
180 val
|= vcpu
->arch
.irq_lines
;
181 write_sysreg(val
, hcr_el2
);
183 if (static_branch_unlikely(&kvm_vgic_global_state
.gicv3_cpuif
))
184 __vgic_v3_restore_state(vcpu
);
186 __vgic_v2_restore_state(vcpu
);
189 static bool __hyp_text
__true_value(void)
194 static bool __hyp_text
__false_value(void)
199 static hyp_alternate_select(__check_arm_834220
,
200 __false_value
, __true_value
,
201 ARM64_WORKAROUND_834220
);
203 static bool __hyp_text
__translate_far_to_hpfar(u64 far
, u64
*hpfar
)
208 * Resolve the IPA the hard way using the guest VA.
210 * Stage-1 translation already validated the memory access
211 * rights. As such, we can use the EL1 translation regime, and
212 * don't have to distinguish between EL0 and EL1 access.
214 * We do need to save/restore PAR_EL1 though, as we haven't
215 * saved the guest context yet, and we may return early...
217 par
= read_sysreg(par_el1
);
218 asm volatile("at s1e1r, %0" : : "r" (far
));
221 tmp
= read_sysreg(par_el1
);
222 write_sysreg(par
, par_el1
);
224 if (unlikely(tmp
& 1))
225 return false; /* Translation failed, back to guest */
227 /* Convert PAR to HPFAR format */
228 *hpfar
= ((tmp
>> 12) & ((1UL << 36) - 1)) << 4;
232 static bool __hyp_text
__populate_fault_info(struct kvm_vcpu
*vcpu
)
234 u64 esr
= read_sysreg_el2(esr
);
235 u8 ec
= ESR_ELx_EC(esr
);
238 vcpu
->arch
.fault
.esr_el2
= esr
;
240 if (ec
!= ESR_ELx_EC_DABT_LOW
&& ec
!= ESR_ELx_EC_IABT_LOW
)
243 far
= read_sysreg_el2(far
);
246 * The HPFAR can be invalid if the stage 2 fault did not
247 * happen during a stage 1 page table walk (the ESR_EL2.S1PTW
248 * bit is clear) and one of the two following cases are true:
249 * 1. The fault was due to a permission fault
250 * 2. The processor carries errata 834220
252 * Therefore, for all non S1PTW faults where we either have a
253 * permission fault or the errata workaround is enabled, we
254 * resolve the IPA using the AT instruction.
256 if (!(esr
& ESR_ELx_S1PTW
) &&
257 (__check_arm_834220()() || (esr
& ESR_ELx_FSC_TYPE
) == FSC_PERM
)) {
258 if (!__translate_far_to_hpfar(far
, &hpfar
))
261 hpfar
= read_sysreg(hpfar_el2
);
264 vcpu
->arch
.fault
.far_el2
= far
;
265 vcpu
->arch
.fault
.hpfar_el2
= hpfar
;
269 static void __hyp_text
__skip_instr(struct kvm_vcpu
*vcpu
)
271 *vcpu_pc(vcpu
) = read_sysreg_el2(elr
);
273 if (vcpu_mode_is_32bit(vcpu
)) {
274 vcpu
->arch
.ctxt
.gp_regs
.regs
.pstate
= read_sysreg_el2(spsr
);
275 kvm_skip_instr32(vcpu
, kvm_vcpu_trap_il_is32bit(vcpu
));
276 write_sysreg_el2(vcpu
->arch
.ctxt
.gp_regs
.regs
.pstate
, spsr
);
281 write_sysreg_el2(*vcpu_pc(vcpu
), elr
);
284 int __hyp_text
__kvm_vcpu_run(struct kvm_vcpu
*vcpu
)
286 struct kvm_cpu_context
*host_ctxt
;
287 struct kvm_cpu_context
*guest_ctxt
;
291 vcpu
= kern_hyp_va(vcpu
);
292 write_sysreg(vcpu
, tpidr_el2
);
294 host_ctxt
= kern_hyp_va(vcpu
->arch
.host_cpu_context
);
295 guest_ctxt
= &vcpu
->arch
.ctxt
;
297 __sysreg_save_host_state(host_ctxt
);
298 __debug_cond_save_host_state(vcpu
);
300 __activate_traps(vcpu
);
303 __vgic_restore_state(vcpu
);
304 __timer_restore_state(vcpu
);
307 * We must restore the 32-bit state before the sysregs, thanks
308 * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
310 __sysreg32_restore_state(vcpu
);
311 __sysreg_restore_guest_state(guest_ctxt
);
312 __debug_restore_state(vcpu
, kern_hyp_va(vcpu
->arch
.debug_ptr
), guest_ctxt
);
314 /* Jump in the fire! */
316 exit_code
= __guest_enter(vcpu
, host_ctxt
);
317 /* And we're baaack! */
320 * We're using the raw exception code in order to only process
321 * the trap if no SError is pending. We will come back to the
322 * same PC once the SError has been injected, and replay the
323 * trapping instruction.
325 if (exit_code
== ARM_EXCEPTION_TRAP
&& !__populate_fault_info(vcpu
))
328 if (exit_code
== ARM_EXCEPTION_TRAP
&&
329 (kvm_vcpu_trap_get_class(vcpu
) == ESR_ELx_EC_HVC64
||
330 kvm_vcpu_trap_get_class(vcpu
) == ESR_ELx_EC_HVC32
)) {
331 u32 val
= vcpu_get_reg(vcpu
, 0);
333 if (val
== PSCI_0_2_FN_PSCI_VERSION
) {
334 val
= kvm_psci_version(vcpu
, kern_hyp_va(vcpu
->kvm
));
335 if (unlikely(val
== KVM_ARM_PSCI_0_1
))
336 val
= PSCI_RET_NOT_SUPPORTED
;
337 vcpu_set_reg(vcpu
, 0, val
);
342 if (static_branch_unlikely(&vgic_v2_cpuif_trap
) &&
343 exit_code
== ARM_EXCEPTION_TRAP
) {
346 valid
= kvm_vcpu_trap_get_class(vcpu
) == ESR_ELx_EC_DABT_LOW
&&
347 kvm_vcpu_trap_get_fault_type(vcpu
) == FSC_FAULT
&&
348 kvm_vcpu_dabt_isvalid(vcpu
) &&
349 !kvm_vcpu_dabt_isextabt(vcpu
) &&
350 !kvm_vcpu_dabt_iss1tw(vcpu
);
353 int ret
= __vgic_v2_perform_cpuif_access(vcpu
);
361 /* Promote an illegal access to an SError */
363 exit_code
= ARM_EXCEPTION_EL1_SERROR
;
366 /* 0 falls through to be handler out of EL2 */
370 if (static_branch_unlikely(&vgic_v3_cpuif_trap
) &&
371 exit_code
== ARM_EXCEPTION_TRAP
&&
372 (kvm_vcpu_trap_get_class(vcpu
) == ESR_ELx_EC_SYS64
||
373 kvm_vcpu_trap_get_class(vcpu
) == ESR_ELx_EC_CP15_32
)) {
374 int ret
= __vgic_v3_perform_cpuif_access(vcpu
);
381 /* 0 falls through to be handled out of EL2 */
384 if (cpus_have_const_cap(ARM64_HARDEN_BP_POST_GUEST_EXIT
)) {
385 u32 midr
= read_cpuid_id();
387 /* Apply BTAC predictors mitigation to all Falkor chips */
388 if ((midr
& MIDR_CPU_MODEL_MASK
) == MIDR_QCOM_FALKOR_V1
)
389 __qcom_hyp_sanitize_btac_predictors();
392 fp_enabled
= __fpsimd_enabled();
394 __sysreg_save_guest_state(guest_ctxt
);
395 __sysreg32_save_state(vcpu
);
396 __timer_save_state(vcpu
);
397 __vgic_save_state(vcpu
);
399 __deactivate_traps(vcpu
);
400 __deactivate_vm(vcpu
);
402 __sysreg_restore_host_state(host_ctxt
);
405 __fpsimd_save_state(&guest_ctxt
->gp_regs
.fp_regs
);
406 __fpsimd_restore_state(&host_ctxt
->gp_regs
.fp_regs
);
409 __debug_save_state(vcpu
, kern_hyp_va(vcpu
->arch
.debug_ptr
), guest_ctxt
);
411 * This must come after restoring the host sysregs, since a non-VHE
412 * system may enable SPE here and make use of the TTBRs.
414 __debug_cond_restore_host_state(vcpu
);
419 static const char __hyp_panic_string
[] = "HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n";
421 static void __hyp_text
__hyp_call_panic_nvhe(u64 spsr
, u64 elr
, u64 par
)
423 unsigned long str_va
;
426 * Force the panic string to be loaded from the literal pool,
427 * making sure it is a kernel address and not a PC-relative
430 asm volatile("ldr %0, =__hyp_panic_string" : "=r" (str_va
));
432 __hyp_do_panic(str_va
,
434 read_sysreg(esr_el2
), read_sysreg_el2(far
),
435 read_sysreg(hpfar_el2
), par
,
436 (void *)read_sysreg(tpidr_el2
));
439 static void __hyp_text
__hyp_call_panic_vhe(u64 spsr
, u64 elr
, u64 par
)
441 panic(__hyp_panic_string
,
443 read_sysreg_el2(esr
), read_sysreg_el2(far
),
444 read_sysreg(hpfar_el2
), par
,
445 (void *)read_sysreg(tpidr_el2
));
448 static hyp_alternate_select(__hyp_call_panic
,
449 __hyp_call_panic_nvhe
, __hyp_call_panic_vhe
,
450 ARM64_HAS_VIRT_HOST_EXTN
);
452 void __hyp_text __noreturn
__hyp_panic(void)
454 u64 spsr
= read_sysreg_el2(spsr
);
455 u64 elr
= read_sysreg_el2(elr
);
456 u64 par
= read_sysreg(par_el1
);
458 if (read_sysreg(vttbr_el2
)) {
459 struct kvm_vcpu
*vcpu
;
460 struct kvm_cpu_context
*host_ctxt
;
462 vcpu
= (struct kvm_vcpu
*)read_sysreg(tpidr_el2
);
463 host_ctxt
= kern_hyp_va(vcpu
->arch
.host_cpu_context
);
464 __timer_save_state(vcpu
);
465 __deactivate_traps(vcpu
);
466 __deactivate_vm(vcpu
);
467 __sysreg_restore_host_state(host_ctxt
);
470 /* Call panic for real */
471 __hyp_call_panic()(spsr
, elr
, par
);