2 * Copyright (C) 2015 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/types.h>
19 #include <linux/jump_label.h>
20 #include <uapi/linux/psci.h>
22 #include <asm/kvm_asm.h>
23 #include <asm/kvm_emulate.h>
24 #include <asm/kvm_hyp.h>
25 #include <asm/fpsimd.h>
27 static bool __hyp_text
__fpsimd_enabled_nvhe(void)
29 return !(read_sysreg(cptr_el2
) & CPTR_EL2_TFP
);
32 static bool __hyp_text
__fpsimd_enabled_vhe(void)
34 return !!(read_sysreg(cpacr_el1
) & CPACR_EL1_FPEN
);
37 static hyp_alternate_select(__fpsimd_is_enabled
,
38 __fpsimd_enabled_nvhe
, __fpsimd_enabled_vhe
,
39 ARM64_HAS_VIRT_HOST_EXTN
);
41 bool __hyp_text
__fpsimd_enabled(void)
43 return __fpsimd_is_enabled()();
46 static void __hyp_text
__activate_traps_vhe(void)
50 val
= read_sysreg(cpacr_el1
);
52 val
&= ~CPACR_EL1_FPEN
;
53 write_sysreg(val
, cpacr_el1
);
55 write_sysreg(kvm_get_hyp_vector(), vbar_el1
);
58 static void __hyp_text
__activate_traps_nvhe(void)
62 val
= CPTR_EL2_DEFAULT
;
63 val
|= CPTR_EL2_TTA
| CPTR_EL2_TFP
;
64 write_sysreg(val
, cptr_el2
);
67 static hyp_alternate_select(__activate_traps_arch
,
68 __activate_traps_nvhe
, __activate_traps_vhe
,
69 ARM64_HAS_VIRT_HOST_EXTN
);
71 static void __hyp_text
__activate_traps(struct kvm_vcpu
*vcpu
)
76 * We are about to set CPTR_EL2.TFP to trap all floating point
77 * register accesses to EL2, however, the ARM ARM clearly states that
78 * traps are only taken to EL2 if the operation would not otherwise
79 * trap to EL1. Therefore, always make sure that for 32-bit guests,
80 * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
81 * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
82 * it will cause an exception.
84 val
= vcpu
->arch
.hcr_el2
;
85 if (!(val
& HCR_RW
) && system_supports_fpsimd()) {
86 write_sysreg(1 << 30, fpexc32_el2
);
89 write_sysreg(val
, hcr_el2
);
90 /* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */
91 write_sysreg(1 << 15, hstr_el2
);
93 * Make sure we trap PMU access from EL0 to EL2. Also sanitize
94 * PMSELR_EL0 to make sure it never contains the cycle
95 * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
96 * EL1 instead of being trapped to EL2.
98 write_sysreg(0, pmselr_el0
);
99 write_sysreg(ARMV8_PMU_USERENR_MASK
, pmuserenr_el0
);
100 write_sysreg(vcpu
->arch
.mdcr_el2
, mdcr_el2
);
101 __activate_traps_arch()();
104 static void __hyp_text
__deactivate_traps_vhe(void)
106 extern char vectors
[]; /* kernel exception vectors */
107 u64 mdcr_el2
= read_sysreg(mdcr_el2
);
109 mdcr_el2
&= MDCR_EL2_HPMN_MASK
|
110 MDCR_EL2_E2PB_MASK
<< MDCR_EL2_E2PB_SHIFT
|
113 write_sysreg(mdcr_el2
, mdcr_el2
);
114 write_sysreg(HCR_HOST_VHE_FLAGS
, hcr_el2
);
115 write_sysreg(CPACR_EL1_FPEN
, cpacr_el1
);
116 write_sysreg(vectors
, vbar_el1
);
119 static void __hyp_text
__deactivate_traps_nvhe(void)
121 u64 mdcr_el2
= read_sysreg(mdcr_el2
);
123 mdcr_el2
&= MDCR_EL2_HPMN_MASK
;
124 mdcr_el2
|= MDCR_EL2_E2PB_MASK
<< MDCR_EL2_E2PB_SHIFT
;
126 write_sysreg(mdcr_el2
, mdcr_el2
);
127 write_sysreg(HCR_RW
, hcr_el2
);
128 write_sysreg(CPTR_EL2_DEFAULT
, cptr_el2
);
131 static hyp_alternate_select(__deactivate_traps_arch
,
132 __deactivate_traps_nvhe
, __deactivate_traps_vhe
,
133 ARM64_HAS_VIRT_HOST_EXTN
);
135 static void __hyp_text
__deactivate_traps(struct kvm_vcpu
*vcpu
)
138 * If we pended a virtual abort, preserve it until it gets
139 * cleared. See D1.14.3 (Virtual Interrupts) for details, but
140 * the crucial bit is "On taking a vSError interrupt,
141 * HCR_EL2.VSE is cleared to 0."
143 if (vcpu
->arch
.hcr_el2
& HCR_VSE
)
144 vcpu
->arch
.hcr_el2
= read_sysreg(hcr_el2
);
146 __deactivate_traps_arch()();
147 write_sysreg(0, hstr_el2
);
148 write_sysreg(0, pmuserenr_el0
);
151 static void __hyp_text
__activate_vm(struct kvm_vcpu
*vcpu
)
153 struct kvm
*kvm
= kern_hyp_va(vcpu
->kvm
);
154 write_sysreg(kvm
->arch
.vttbr
, vttbr_el2
);
157 static void __hyp_text
__deactivate_vm(struct kvm_vcpu
*vcpu
)
159 write_sysreg(0, vttbr_el2
);
162 static void __hyp_text
__vgic_save_state(struct kvm_vcpu
*vcpu
)
164 if (static_branch_unlikely(&kvm_vgic_global_state
.gicv3_cpuif
))
165 __vgic_v3_save_state(vcpu
);
167 __vgic_v2_save_state(vcpu
);
169 write_sysreg(read_sysreg(hcr_el2
) & ~HCR_INT_OVERRIDE
, hcr_el2
);
172 static void __hyp_text
__vgic_restore_state(struct kvm_vcpu
*vcpu
)
176 val
= read_sysreg(hcr_el2
);
177 val
|= HCR_INT_OVERRIDE
;
178 val
|= vcpu
->arch
.irq_lines
;
179 write_sysreg(val
, hcr_el2
);
181 if (static_branch_unlikely(&kvm_vgic_global_state
.gicv3_cpuif
))
182 __vgic_v3_restore_state(vcpu
);
184 __vgic_v2_restore_state(vcpu
);
187 static bool __hyp_text
__true_value(void)
192 static bool __hyp_text
__false_value(void)
197 static hyp_alternate_select(__check_arm_834220
,
198 __false_value
, __true_value
,
199 ARM64_WORKAROUND_834220
);
201 static bool __hyp_text
__translate_far_to_hpfar(u64 far
, u64
*hpfar
)
206 * Resolve the IPA the hard way using the guest VA.
208 * Stage-1 translation already validated the memory access
209 * rights. As such, we can use the EL1 translation regime, and
210 * don't have to distinguish between EL0 and EL1 access.
212 * We do need to save/restore PAR_EL1 though, as we haven't
213 * saved the guest context yet, and we may return early...
215 par
= read_sysreg(par_el1
);
216 asm volatile("at s1e1r, %0" : : "r" (far
));
219 tmp
= read_sysreg(par_el1
);
220 write_sysreg(par
, par_el1
);
222 if (unlikely(tmp
& 1))
223 return false; /* Translation failed, back to guest */
225 /* Convert PAR to HPFAR format */
226 *hpfar
= ((tmp
>> 12) & ((1UL << 36) - 1)) << 4;
230 static bool __hyp_text
__populate_fault_info(struct kvm_vcpu
*vcpu
)
232 u64 esr
= read_sysreg_el2(esr
);
233 u8 ec
= ESR_ELx_EC(esr
);
236 vcpu
->arch
.fault
.esr_el2
= esr
;
238 if (ec
!= ESR_ELx_EC_DABT_LOW
&& ec
!= ESR_ELx_EC_IABT_LOW
)
241 far
= read_sysreg_el2(far
);
244 * The HPFAR can be invalid if the stage 2 fault did not
245 * happen during a stage 1 page table walk (the ESR_EL2.S1PTW
246 * bit is clear) and one of the two following cases are true:
247 * 1. The fault was due to a permission fault
248 * 2. The processor carries errata 834220
250 * Therefore, for all non S1PTW faults where we either have a
251 * permission fault or the errata workaround is enabled, we
252 * resolve the IPA using the AT instruction.
254 if (!(esr
& ESR_ELx_S1PTW
) &&
255 (__check_arm_834220()() || (esr
& ESR_ELx_FSC_TYPE
) == FSC_PERM
)) {
256 if (!__translate_far_to_hpfar(far
, &hpfar
))
259 hpfar
= read_sysreg(hpfar_el2
);
262 vcpu
->arch
.fault
.far_el2
= far
;
263 vcpu
->arch
.fault
.hpfar_el2
= hpfar
;
267 static void __hyp_text
__skip_instr(struct kvm_vcpu
*vcpu
)
269 *vcpu_pc(vcpu
) = read_sysreg_el2(elr
);
271 if (vcpu_mode_is_32bit(vcpu
)) {
272 vcpu
->arch
.ctxt
.gp_regs
.regs
.pstate
= read_sysreg_el2(spsr
);
273 kvm_skip_instr32(vcpu
, kvm_vcpu_trap_il_is32bit(vcpu
));
274 write_sysreg_el2(vcpu
->arch
.ctxt
.gp_regs
.regs
.pstate
, spsr
);
279 write_sysreg_el2(*vcpu_pc(vcpu
), elr
);
282 int __hyp_text
__kvm_vcpu_run(struct kvm_vcpu
*vcpu
)
284 struct kvm_cpu_context
*host_ctxt
;
285 struct kvm_cpu_context
*guest_ctxt
;
289 vcpu
= kern_hyp_va(vcpu
);
290 write_sysreg(vcpu
, tpidr_el2
);
292 host_ctxt
= kern_hyp_va(vcpu
->arch
.host_cpu_context
);
293 guest_ctxt
= &vcpu
->arch
.ctxt
;
295 __sysreg_save_host_state(host_ctxt
);
296 __debug_cond_save_host_state(vcpu
);
298 __activate_traps(vcpu
);
301 __vgic_restore_state(vcpu
);
302 __timer_restore_state(vcpu
);
305 * We must restore the 32-bit state before the sysregs, thanks
306 * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
308 __sysreg32_restore_state(vcpu
);
309 __sysreg_restore_guest_state(guest_ctxt
);
310 __debug_restore_state(vcpu
, kern_hyp_va(vcpu
->arch
.debug_ptr
), guest_ctxt
);
312 /* Jump in the fire! */
314 exit_code
= __guest_enter(vcpu
, host_ctxt
);
315 /* And we're baaack! */
318 * We're using the raw exception code in order to only process
319 * the trap if no SError is pending. We will come back to the
320 * same PC once the SError has been injected, and replay the
321 * trapping instruction.
323 if (exit_code
== ARM_EXCEPTION_TRAP
&& !__populate_fault_info(vcpu
))
326 if (exit_code
== ARM_EXCEPTION_TRAP
&&
327 (kvm_vcpu_trap_get_class(vcpu
) == ESR_ELx_EC_HVC64
||
328 kvm_vcpu_trap_get_class(vcpu
) == ESR_ELx_EC_HVC32
) &&
329 vcpu_get_reg(vcpu
, 0) == PSCI_0_2_FN_PSCI_VERSION
) {
330 u64 val
= PSCI_RET_NOT_SUPPORTED
;
331 if (test_bit(KVM_ARM_VCPU_PSCI_0_2
, vcpu
->arch
.features
))
334 vcpu_set_reg(vcpu
, 0, val
);
338 if (static_branch_unlikely(&vgic_v2_cpuif_trap
) &&
339 exit_code
== ARM_EXCEPTION_TRAP
) {
342 valid
= kvm_vcpu_trap_get_class(vcpu
) == ESR_ELx_EC_DABT_LOW
&&
343 kvm_vcpu_trap_get_fault_type(vcpu
) == FSC_FAULT
&&
344 kvm_vcpu_dabt_isvalid(vcpu
) &&
345 !kvm_vcpu_dabt_isextabt(vcpu
) &&
346 !kvm_vcpu_dabt_iss1tw(vcpu
);
349 int ret
= __vgic_v2_perform_cpuif_access(vcpu
);
357 /* Promote an illegal access to an SError */
359 exit_code
= ARM_EXCEPTION_EL1_SERROR
;
362 /* 0 falls through to be handler out of EL2 */
366 if (static_branch_unlikely(&vgic_v3_cpuif_trap
) &&
367 exit_code
== ARM_EXCEPTION_TRAP
&&
368 (kvm_vcpu_trap_get_class(vcpu
) == ESR_ELx_EC_SYS64
||
369 kvm_vcpu_trap_get_class(vcpu
) == ESR_ELx_EC_CP15_32
)) {
370 int ret
= __vgic_v3_perform_cpuif_access(vcpu
);
377 /* 0 falls through to be handled out of EL2 */
380 if (cpus_have_const_cap(ARM64_HARDEN_BP_POST_GUEST_EXIT
)) {
381 u32 midr
= read_cpuid_id();
383 /* Apply BTAC predictors mitigation to all Falkor chips */
384 if ((midr
& MIDR_CPU_MODEL_MASK
) == MIDR_QCOM_FALKOR_V1
)
385 __qcom_hyp_sanitize_btac_predictors();
388 fp_enabled
= __fpsimd_enabled();
390 __sysreg_save_guest_state(guest_ctxt
);
391 __sysreg32_save_state(vcpu
);
392 __timer_save_state(vcpu
);
393 __vgic_save_state(vcpu
);
395 __deactivate_traps(vcpu
);
396 __deactivate_vm(vcpu
);
398 __sysreg_restore_host_state(host_ctxt
);
401 __fpsimd_save_state(&guest_ctxt
->gp_regs
.fp_regs
);
402 __fpsimd_restore_state(&host_ctxt
->gp_regs
.fp_regs
);
405 __debug_save_state(vcpu
, kern_hyp_va(vcpu
->arch
.debug_ptr
), guest_ctxt
);
407 * This must come after restoring the host sysregs, since a non-VHE
408 * system may enable SPE here and make use of the TTBRs.
410 __debug_cond_restore_host_state(vcpu
);
415 static const char __hyp_panic_string
[] = "HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n";
417 static void __hyp_text
__hyp_call_panic_nvhe(u64 spsr
, u64 elr
, u64 par
)
419 unsigned long str_va
;
422 * Force the panic string to be loaded from the literal pool,
423 * making sure it is a kernel address and not a PC-relative
426 asm volatile("ldr %0, =__hyp_panic_string" : "=r" (str_va
));
428 __hyp_do_panic(str_va
,
430 read_sysreg(esr_el2
), read_sysreg_el2(far
),
431 read_sysreg(hpfar_el2
), par
,
432 (void *)read_sysreg(tpidr_el2
));
435 static void __hyp_text
__hyp_call_panic_vhe(u64 spsr
, u64 elr
, u64 par
)
437 panic(__hyp_panic_string
,
439 read_sysreg_el2(esr
), read_sysreg_el2(far
),
440 read_sysreg(hpfar_el2
), par
,
441 (void *)read_sysreg(tpidr_el2
));
444 static hyp_alternate_select(__hyp_call_panic
,
445 __hyp_call_panic_nvhe
, __hyp_call_panic_vhe
,
446 ARM64_HAS_VIRT_HOST_EXTN
);
448 void __hyp_text __noreturn
__hyp_panic(void)
450 u64 spsr
= read_sysreg_el2(spsr
);
451 u64 elr
= read_sysreg_el2(elr
);
452 u64 par
= read_sysreg(par_el1
);
454 if (read_sysreg(vttbr_el2
)) {
455 struct kvm_vcpu
*vcpu
;
456 struct kvm_cpu_context
*host_ctxt
;
458 vcpu
= (struct kvm_vcpu
*)read_sysreg(tpidr_el2
);
459 host_ctxt
= kern_hyp_va(vcpu
->arch
.host_cpu_context
);
460 __timer_save_state(vcpu
);
461 __deactivate_traps(vcpu
);
462 __deactivate_vm(vcpu
);
463 __sysreg_restore_host_state(host_ctxt
);
466 /* Call panic for real */
467 __hyp_call_panic()(spsr
, elr
, par
);