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KVM: arm64: Use common sysreg definitions
[mirror_ubuntu-bionic-kernel.git] / arch / arm64 / kvm / sys_regs.c
1 /*
2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * Derived from arch/arm/kvm/coproc.c:
6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
7 * Authors: Rusty Russell <rusty@rustcorp.com.au>
8 * Christoffer Dall <c.dall@virtualopensystems.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License, version 2, as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include <linux/bsearch.h>
24 #include <linux/kvm_host.h>
25 #include <linux/mm.h>
26 #include <linux/uaccess.h>
27
28 #include <asm/cacheflush.h>
29 #include <asm/cputype.h>
30 #include <asm/debug-monitors.h>
31 #include <asm/esr.h>
32 #include <asm/kvm_arm.h>
33 #include <asm/kvm_asm.h>
34 #include <asm/kvm_coproc.h>
35 #include <asm/kvm_emulate.h>
36 #include <asm/kvm_host.h>
37 #include <asm/kvm_mmu.h>
38 #include <asm/perf_event.h>
39 #include <asm/sysreg.h>
40
41 #include <trace/events/kvm.h>
42
43 #include "sys_regs.h"
44
45 #include "trace.h"
46
47 /*
48 * All of this file is extremly similar to the ARM coproc.c, but the
49 * types are different. My gut feeling is that it should be pretty
50 * easy to merge, but that would be an ABI breakage -- again. VFP
51 * would also need to be abstracted.
52 *
53 * For AArch32, we only take care of what is being trapped. Anything
54 * that has to do with init and userspace access has to go via the
55 * 64bit interface.
56 */
57
58 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
59 static u32 cache_levels;
60
61 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
62 #define CSSELR_MAX 12
63
64 /* Which cache CCSIDR represents depends on CSSELR value. */
65 static u32 get_ccsidr(u32 csselr)
66 {
67 u32 ccsidr;
68
69 /* Make sure noone else changes CSSELR during this! */
70 local_irq_disable();
71 write_sysreg(csselr, csselr_el1);
72 isb();
73 ccsidr = read_sysreg(ccsidr_el1);
74 local_irq_enable();
75
76 return ccsidr;
77 }
78
79 /*
80 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
81 */
82 static bool access_dcsw(struct kvm_vcpu *vcpu,
83 struct sys_reg_params *p,
84 const struct sys_reg_desc *r)
85 {
86 if (!p->is_write)
87 return read_from_write_only(vcpu, p);
88
89 kvm_set_way_flush(vcpu);
90 return true;
91 }
92
93 /*
94 * Generic accessor for VM registers. Only called as long as HCR_TVM
95 * is set. If the guest enables the MMU, we stop trapping the VM
96 * sys_regs and leave it in complete control of the caches.
97 */
98 static bool access_vm_reg(struct kvm_vcpu *vcpu,
99 struct sys_reg_params *p,
100 const struct sys_reg_desc *r)
101 {
102 bool was_enabled = vcpu_has_cache_enabled(vcpu);
103
104 BUG_ON(!p->is_write);
105
106 if (!p->is_aarch32) {
107 vcpu_sys_reg(vcpu, r->reg) = p->regval;
108 } else {
109 if (!p->is_32bit)
110 vcpu_cp15_64_high(vcpu, r->reg) = upper_32_bits(p->regval);
111 vcpu_cp15_64_low(vcpu, r->reg) = lower_32_bits(p->regval);
112 }
113
114 kvm_toggle_cache(vcpu, was_enabled);
115 return true;
116 }
117
118 /*
119 * Trap handler for the GICv3 SGI generation system register.
120 * Forward the request to the VGIC emulation.
121 * The cp15_64 code makes sure this automatically works
122 * for both AArch64 and AArch32 accesses.
123 */
124 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
125 struct sys_reg_params *p,
126 const struct sys_reg_desc *r)
127 {
128 if (!p->is_write)
129 return read_from_write_only(vcpu, p);
130
131 vgic_v3_dispatch_sgi(vcpu, p->regval);
132
133 return true;
134 }
135
136 static bool access_gic_sre(struct kvm_vcpu *vcpu,
137 struct sys_reg_params *p,
138 const struct sys_reg_desc *r)
139 {
140 if (p->is_write)
141 return ignore_write(vcpu, p);
142
143 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
144 return true;
145 }
146
147 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
148 struct sys_reg_params *p,
149 const struct sys_reg_desc *r)
150 {
151 if (p->is_write)
152 return ignore_write(vcpu, p);
153 else
154 return read_zero(vcpu, p);
155 }
156
157 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
158 struct sys_reg_params *p,
159 const struct sys_reg_desc *r)
160 {
161 if (p->is_write) {
162 return ignore_write(vcpu, p);
163 } else {
164 p->regval = (1 << 3);
165 return true;
166 }
167 }
168
169 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
170 struct sys_reg_params *p,
171 const struct sys_reg_desc *r)
172 {
173 if (p->is_write) {
174 return ignore_write(vcpu, p);
175 } else {
176 p->regval = read_sysreg(dbgauthstatus_el1);
177 return true;
178 }
179 }
180
181 /*
182 * We want to avoid world-switching all the DBG registers all the
183 * time:
184 *
185 * - If we've touched any debug register, it is likely that we're
186 * going to touch more of them. It then makes sense to disable the
187 * traps and start doing the save/restore dance
188 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
189 * then mandatory to save/restore the registers, as the guest
190 * depends on them.
191 *
192 * For this, we use a DIRTY bit, indicating the guest has modified the
193 * debug registers, used as follow:
194 *
195 * On guest entry:
196 * - If the dirty bit is set (because we're coming back from trapping),
197 * disable the traps, save host registers, restore guest registers.
198 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
199 * set the dirty bit, disable the traps, save host registers,
200 * restore guest registers.
201 * - Otherwise, enable the traps
202 *
203 * On guest exit:
204 * - If the dirty bit is set, save guest registers, restore host
205 * registers and clear the dirty bit. This ensure that the host can
206 * now use the debug registers.
207 */
208 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
209 struct sys_reg_params *p,
210 const struct sys_reg_desc *r)
211 {
212 if (p->is_write) {
213 vcpu_sys_reg(vcpu, r->reg) = p->regval;
214 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
215 } else {
216 p->regval = vcpu_sys_reg(vcpu, r->reg);
217 }
218
219 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
220
221 return true;
222 }
223
224 /*
225 * reg_to_dbg/dbg_to_reg
226 *
227 * A 32 bit write to a debug register leave top bits alone
228 * A 32 bit read from a debug register only returns the bottom bits
229 *
230 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
231 * hyp.S code switches between host and guest values in future.
232 */
233 static void reg_to_dbg(struct kvm_vcpu *vcpu,
234 struct sys_reg_params *p,
235 u64 *dbg_reg)
236 {
237 u64 val = p->regval;
238
239 if (p->is_32bit) {
240 val &= 0xffffffffUL;
241 val |= ((*dbg_reg >> 32) << 32);
242 }
243
244 *dbg_reg = val;
245 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
246 }
247
248 static void dbg_to_reg(struct kvm_vcpu *vcpu,
249 struct sys_reg_params *p,
250 u64 *dbg_reg)
251 {
252 p->regval = *dbg_reg;
253 if (p->is_32bit)
254 p->regval &= 0xffffffffUL;
255 }
256
257 static bool trap_bvr(struct kvm_vcpu *vcpu,
258 struct sys_reg_params *p,
259 const struct sys_reg_desc *rd)
260 {
261 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
262
263 if (p->is_write)
264 reg_to_dbg(vcpu, p, dbg_reg);
265 else
266 dbg_to_reg(vcpu, p, dbg_reg);
267
268 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
269
270 return true;
271 }
272
273 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
274 const struct kvm_one_reg *reg, void __user *uaddr)
275 {
276 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
277
278 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
279 return -EFAULT;
280 return 0;
281 }
282
283 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
284 const struct kvm_one_reg *reg, void __user *uaddr)
285 {
286 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
287
288 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
289 return -EFAULT;
290 return 0;
291 }
292
293 static void reset_bvr(struct kvm_vcpu *vcpu,
294 const struct sys_reg_desc *rd)
295 {
296 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val;
297 }
298
299 static bool trap_bcr(struct kvm_vcpu *vcpu,
300 struct sys_reg_params *p,
301 const struct sys_reg_desc *rd)
302 {
303 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
304
305 if (p->is_write)
306 reg_to_dbg(vcpu, p, dbg_reg);
307 else
308 dbg_to_reg(vcpu, p, dbg_reg);
309
310 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
311
312 return true;
313 }
314
315 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
316 const struct kvm_one_reg *reg, void __user *uaddr)
317 {
318 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
319
320 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
321 return -EFAULT;
322
323 return 0;
324 }
325
326 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
327 const struct kvm_one_reg *reg, void __user *uaddr)
328 {
329 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
330
331 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
332 return -EFAULT;
333 return 0;
334 }
335
336 static void reset_bcr(struct kvm_vcpu *vcpu,
337 const struct sys_reg_desc *rd)
338 {
339 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val;
340 }
341
342 static bool trap_wvr(struct kvm_vcpu *vcpu,
343 struct sys_reg_params *p,
344 const struct sys_reg_desc *rd)
345 {
346 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
347
348 if (p->is_write)
349 reg_to_dbg(vcpu, p, dbg_reg);
350 else
351 dbg_to_reg(vcpu, p, dbg_reg);
352
353 trace_trap_reg(__func__, rd->reg, p->is_write,
354 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]);
355
356 return true;
357 }
358
359 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
360 const struct kvm_one_reg *reg, void __user *uaddr)
361 {
362 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
363
364 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
365 return -EFAULT;
366 return 0;
367 }
368
369 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
370 const struct kvm_one_reg *reg, void __user *uaddr)
371 {
372 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
373
374 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
375 return -EFAULT;
376 return 0;
377 }
378
379 static void reset_wvr(struct kvm_vcpu *vcpu,
380 const struct sys_reg_desc *rd)
381 {
382 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val;
383 }
384
385 static bool trap_wcr(struct kvm_vcpu *vcpu,
386 struct sys_reg_params *p,
387 const struct sys_reg_desc *rd)
388 {
389 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
390
391 if (p->is_write)
392 reg_to_dbg(vcpu, p, dbg_reg);
393 else
394 dbg_to_reg(vcpu, p, dbg_reg);
395
396 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
397
398 return true;
399 }
400
401 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
402 const struct kvm_one_reg *reg, void __user *uaddr)
403 {
404 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
405
406 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
407 return -EFAULT;
408 return 0;
409 }
410
411 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
412 const struct kvm_one_reg *reg, void __user *uaddr)
413 {
414 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
415
416 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
417 return -EFAULT;
418 return 0;
419 }
420
421 static void reset_wcr(struct kvm_vcpu *vcpu,
422 const struct sys_reg_desc *rd)
423 {
424 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val;
425 }
426
427 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
428 {
429 vcpu_sys_reg(vcpu, AMAIR_EL1) = read_sysreg(amair_el1);
430 }
431
432 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
433 {
434 u64 mpidr;
435
436 /*
437 * Map the vcpu_id into the first three affinity level fields of
438 * the MPIDR. We limit the number of VCPUs in level 0 due to a
439 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
440 * of the GICv3 to be able to address each CPU directly when
441 * sending IPIs.
442 */
443 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
444 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
445 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
446 vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
447 }
448
449 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
450 {
451 u64 pmcr, val;
452
453 pmcr = read_sysreg(pmcr_el0);
454 /*
455 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
456 * except PMCR.E resetting to zero.
457 */
458 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
459 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
460 vcpu_sys_reg(vcpu, PMCR_EL0) = val;
461 }
462
463 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
464 {
465 u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
466
467 return !((reg & ARMV8_PMU_USERENR_EN) || vcpu_mode_priv(vcpu));
468 }
469
470 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
471 {
472 u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
473
474 return !((reg & (ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN))
475 || vcpu_mode_priv(vcpu));
476 }
477
478 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
479 {
480 u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
481
482 return !((reg & (ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN))
483 || vcpu_mode_priv(vcpu));
484 }
485
486 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
487 {
488 u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
489
490 return !((reg & (ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN))
491 || vcpu_mode_priv(vcpu));
492 }
493
494 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
495 const struct sys_reg_desc *r)
496 {
497 u64 val;
498
499 if (!kvm_arm_pmu_v3_ready(vcpu))
500 return trap_raz_wi(vcpu, p, r);
501
502 if (pmu_access_el0_disabled(vcpu))
503 return false;
504
505 if (p->is_write) {
506 /* Only update writeable bits of PMCR */
507 val = vcpu_sys_reg(vcpu, PMCR_EL0);
508 val &= ~ARMV8_PMU_PMCR_MASK;
509 val |= p->regval & ARMV8_PMU_PMCR_MASK;
510 vcpu_sys_reg(vcpu, PMCR_EL0) = val;
511 kvm_pmu_handle_pmcr(vcpu, val);
512 } else {
513 /* PMCR.P & PMCR.C are RAZ */
514 val = vcpu_sys_reg(vcpu, PMCR_EL0)
515 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
516 p->regval = val;
517 }
518
519 return true;
520 }
521
522 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
523 const struct sys_reg_desc *r)
524 {
525 if (!kvm_arm_pmu_v3_ready(vcpu))
526 return trap_raz_wi(vcpu, p, r);
527
528 if (pmu_access_event_counter_el0_disabled(vcpu))
529 return false;
530
531 if (p->is_write)
532 vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
533 else
534 /* return PMSELR.SEL field */
535 p->regval = vcpu_sys_reg(vcpu, PMSELR_EL0)
536 & ARMV8_PMU_COUNTER_MASK;
537
538 return true;
539 }
540
541 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
542 const struct sys_reg_desc *r)
543 {
544 u64 pmceid;
545
546 if (!kvm_arm_pmu_v3_ready(vcpu))
547 return trap_raz_wi(vcpu, p, r);
548
549 BUG_ON(p->is_write);
550
551 if (pmu_access_el0_disabled(vcpu))
552 return false;
553
554 if (!(p->Op2 & 1))
555 pmceid = read_sysreg(pmceid0_el0);
556 else
557 pmceid = read_sysreg(pmceid1_el0);
558
559 p->regval = pmceid;
560
561 return true;
562 }
563
564 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
565 {
566 u64 pmcr, val;
567
568 pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
569 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
570 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX)
571 return false;
572
573 return true;
574 }
575
576 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
577 struct sys_reg_params *p,
578 const struct sys_reg_desc *r)
579 {
580 u64 idx;
581
582 if (!kvm_arm_pmu_v3_ready(vcpu))
583 return trap_raz_wi(vcpu, p, r);
584
585 if (r->CRn == 9 && r->CRm == 13) {
586 if (r->Op2 == 2) {
587 /* PMXEVCNTR_EL0 */
588 if (pmu_access_event_counter_el0_disabled(vcpu))
589 return false;
590
591 idx = vcpu_sys_reg(vcpu, PMSELR_EL0)
592 & ARMV8_PMU_COUNTER_MASK;
593 } else if (r->Op2 == 0) {
594 /* PMCCNTR_EL0 */
595 if (pmu_access_cycle_counter_el0_disabled(vcpu))
596 return false;
597
598 idx = ARMV8_PMU_CYCLE_IDX;
599 } else {
600 return false;
601 }
602 } else if (r->CRn == 0 && r->CRm == 9) {
603 /* PMCCNTR */
604 if (pmu_access_event_counter_el0_disabled(vcpu))
605 return false;
606
607 idx = ARMV8_PMU_CYCLE_IDX;
608 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
609 /* PMEVCNTRn_EL0 */
610 if (pmu_access_event_counter_el0_disabled(vcpu))
611 return false;
612
613 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
614 } else {
615 return false;
616 }
617
618 if (!pmu_counter_idx_valid(vcpu, idx))
619 return false;
620
621 if (p->is_write) {
622 if (pmu_access_el0_disabled(vcpu))
623 return false;
624
625 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
626 } else {
627 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
628 }
629
630 return true;
631 }
632
633 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
634 const struct sys_reg_desc *r)
635 {
636 u64 idx, reg;
637
638 if (!kvm_arm_pmu_v3_ready(vcpu))
639 return trap_raz_wi(vcpu, p, r);
640
641 if (pmu_access_el0_disabled(vcpu))
642 return false;
643
644 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
645 /* PMXEVTYPER_EL0 */
646 idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
647 reg = PMEVTYPER0_EL0 + idx;
648 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
649 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
650 if (idx == ARMV8_PMU_CYCLE_IDX)
651 reg = PMCCFILTR_EL0;
652 else
653 /* PMEVTYPERn_EL0 */
654 reg = PMEVTYPER0_EL0 + idx;
655 } else {
656 BUG();
657 }
658
659 if (!pmu_counter_idx_valid(vcpu, idx))
660 return false;
661
662 if (p->is_write) {
663 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
664 vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
665 } else {
666 p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
667 }
668
669 return true;
670 }
671
672 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
673 const struct sys_reg_desc *r)
674 {
675 u64 val, mask;
676
677 if (!kvm_arm_pmu_v3_ready(vcpu))
678 return trap_raz_wi(vcpu, p, r);
679
680 if (pmu_access_el0_disabled(vcpu))
681 return false;
682
683 mask = kvm_pmu_valid_counter_mask(vcpu);
684 if (p->is_write) {
685 val = p->regval & mask;
686 if (r->Op2 & 0x1) {
687 /* accessing PMCNTENSET_EL0 */
688 vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
689 kvm_pmu_enable_counter(vcpu, val);
690 } else {
691 /* accessing PMCNTENCLR_EL0 */
692 vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
693 kvm_pmu_disable_counter(vcpu, val);
694 }
695 } else {
696 p->regval = vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
697 }
698
699 return true;
700 }
701
702 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
703 const struct sys_reg_desc *r)
704 {
705 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
706
707 if (!kvm_arm_pmu_v3_ready(vcpu))
708 return trap_raz_wi(vcpu, p, r);
709
710 if (!vcpu_mode_priv(vcpu))
711 return false;
712
713 if (p->is_write) {
714 u64 val = p->regval & mask;
715
716 if (r->Op2 & 0x1)
717 /* accessing PMINTENSET_EL1 */
718 vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
719 else
720 /* accessing PMINTENCLR_EL1 */
721 vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
722 } else {
723 p->regval = vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
724 }
725
726 return true;
727 }
728
729 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
730 const struct sys_reg_desc *r)
731 {
732 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
733
734 if (!kvm_arm_pmu_v3_ready(vcpu))
735 return trap_raz_wi(vcpu, p, r);
736
737 if (pmu_access_el0_disabled(vcpu))
738 return false;
739
740 if (p->is_write) {
741 if (r->CRm & 0x2)
742 /* accessing PMOVSSET_EL0 */
743 kvm_pmu_overflow_set(vcpu, p->regval & mask);
744 else
745 /* accessing PMOVSCLR_EL0 */
746 vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
747 } else {
748 p->regval = vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
749 }
750
751 return true;
752 }
753
754 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
755 const struct sys_reg_desc *r)
756 {
757 u64 mask;
758
759 if (!kvm_arm_pmu_v3_ready(vcpu))
760 return trap_raz_wi(vcpu, p, r);
761
762 if (pmu_write_swinc_el0_disabled(vcpu))
763 return false;
764
765 if (p->is_write) {
766 mask = kvm_pmu_valid_counter_mask(vcpu);
767 kvm_pmu_software_increment(vcpu, p->regval & mask);
768 return true;
769 }
770
771 return false;
772 }
773
774 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
775 const struct sys_reg_desc *r)
776 {
777 if (!kvm_arm_pmu_v3_ready(vcpu))
778 return trap_raz_wi(vcpu, p, r);
779
780 if (p->is_write) {
781 if (!vcpu_mode_priv(vcpu))
782 return false;
783
784 vcpu_sys_reg(vcpu, PMUSERENR_EL0) = p->regval
785 & ARMV8_PMU_USERENR_MASK;
786 } else {
787 p->regval = vcpu_sys_reg(vcpu, PMUSERENR_EL0)
788 & ARMV8_PMU_USERENR_MASK;
789 }
790
791 return true;
792 }
793
794 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
795 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \
796 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
797 trap_bvr, reset_bvr, n, 0, get_bvr, set_bvr }, \
798 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
799 trap_bcr, reset_bcr, n, 0, get_bcr, set_bcr }, \
800 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
801 trap_wvr, reset_wvr, n, 0, get_wvr, set_wvr }, \
802 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
803 trap_wcr, reset_wcr, n, 0, get_wcr, set_wcr }
804
805 /* Macro to expand the PMEVCNTRn_EL0 register */
806 #define PMU_PMEVCNTR_EL0(n) \
807 { SYS_DESC(SYS_PMEVCNTRn_EL0(n)), \
808 access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
809
810 /* Macro to expand the PMEVTYPERn_EL0 register */
811 #define PMU_PMEVTYPER_EL0(n) \
812 { SYS_DESC(SYS_PMEVTYPERn_EL0(n)), \
813 access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
814
815 static bool access_cntp_tval(struct kvm_vcpu *vcpu,
816 struct sys_reg_params *p,
817 const struct sys_reg_desc *r)
818 {
819 struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
820 u64 now = kvm_phys_timer_read();
821
822 if (p->is_write)
823 ptimer->cnt_cval = p->regval + now;
824 else
825 p->regval = ptimer->cnt_cval - now;
826
827 return true;
828 }
829
830 static bool access_cntp_ctl(struct kvm_vcpu *vcpu,
831 struct sys_reg_params *p,
832 const struct sys_reg_desc *r)
833 {
834 struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
835
836 if (p->is_write) {
837 /* ISTATUS bit is read-only */
838 ptimer->cnt_ctl = p->regval & ~ARCH_TIMER_CTRL_IT_STAT;
839 } else {
840 u64 now = kvm_phys_timer_read();
841
842 p->regval = ptimer->cnt_ctl;
843 /*
844 * Set ISTATUS bit if it's expired.
845 * Note that according to ARMv8 ARM Issue A.k, ISTATUS bit is
846 * UNKNOWN when ENABLE bit is 0, so we chose to set ISTATUS bit
847 * regardless of ENABLE bit for our implementation convenience.
848 */
849 if (ptimer->cnt_cval <= now)
850 p->regval |= ARCH_TIMER_CTRL_IT_STAT;
851 }
852
853 return true;
854 }
855
856 static bool access_cntp_cval(struct kvm_vcpu *vcpu,
857 struct sys_reg_params *p,
858 const struct sys_reg_desc *r)
859 {
860 struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
861
862 if (p->is_write)
863 ptimer->cnt_cval = p->regval;
864 else
865 p->regval = ptimer->cnt_cval;
866
867 return true;
868 }
869
870 /*
871 * Architected system registers.
872 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
873 *
874 * Debug handling: We do trap most, if not all debug related system
875 * registers. The implementation is good enough to ensure that a guest
876 * can use these with minimal performance degradation. The drawback is
877 * that we don't implement any of the external debug, none of the
878 * OSlock protocol. This should be revisited if we ever encounter a
879 * more demanding guest...
880 */
881 static const struct sys_reg_desc sys_reg_descs[] = {
882 /* DC ISW */
883 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
884 access_dcsw },
885 /* DC CSW */
886 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
887 access_dcsw },
888 /* DC CISW */
889 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
890 access_dcsw },
891
892 DBG_BCR_BVR_WCR_WVR_EL1(0),
893 DBG_BCR_BVR_WCR_WVR_EL1(1),
894 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
895 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
896 DBG_BCR_BVR_WCR_WVR_EL1(2),
897 DBG_BCR_BVR_WCR_WVR_EL1(3),
898 DBG_BCR_BVR_WCR_WVR_EL1(4),
899 DBG_BCR_BVR_WCR_WVR_EL1(5),
900 DBG_BCR_BVR_WCR_WVR_EL1(6),
901 DBG_BCR_BVR_WCR_WVR_EL1(7),
902 DBG_BCR_BVR_WCR_WVR_EL1(8),
903 DBG_BCR_BVR_WCR_WVR_EL1(9),
904 DBG_BCR_BVR_WCR_WVR_EL1(10),
905 DBG_BCR_BVR_WCR_WVR_EL1(11),
906 DBG_BCR_BVR_WCR_WVR_EL1(12),
907 DBG_BCR_BVR_WCR_WVR_EL1(13),
908 DBG_BCR_BVR_WCR_WVR_EL1(14),
909 DBG_BCR_BVR_WCR_WVR_EL1(15),
910
911 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
912 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi },
913 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 },
914 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
915 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
916 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
917 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
918 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
919
920 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
921 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
922 // DBGDTR[TR]X_EL0 share the same encoding
923 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
924
925 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
926
927 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
928 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
929 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
930 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
931 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
932 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
933
934 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
935 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
936 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
937 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
938 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
939
940 { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
941 { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, NULL, PMINTENSET_EL1 },
942
943 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
944 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
945
946 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
947
948 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
949 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
950
951 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
952 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
953
954 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
955
956 { SYS_DESC(SYS_CSSELR_EL1), NULL, reset_unknown, CSSELR_EL1 },
957
958 { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, },
959 { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
960 { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, NULL, PMCNTENSET_EL0 },
961 { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, NULL, PMOVSSET_EL0 },
962 { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 },
963 { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 },
964 { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid },
965 { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid },
966 { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
967 { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper },
968 { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr },
969 /*
970 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
971 * in 32bit mode. Here we choose to reset it as zero for consistency.
972 */
973 { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
974 { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },
975
976 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
977 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
978
979 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_cntp_tval },
980 { SYS_DESC(SYS_CNTP_CTL_EL0), access_cntp_ctl },
981 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_cntp_cval },
982
983 /* PMEVCNTRn_EL0 */
984 PMU_PMEVCNTR_EL0(0),
985 PMU_PMEVCNTR_EL0(1),
986 PMU_PMEVCNTR_EL0(2),
987 PMU_PMEVCNTR_EL0(3),
988 PMU_PMEVCNTR_EL0(4),
989 PMU_PMEVCNTR_EL0(5),
990 PMU_PMEVCNTR_EL0(6),
991 PMU_PMEVCNTR_EL0(7),
992 PMU_PMEVCNTR_EL0(8),
993 PMU_PMEVCNTR_EL0(9),
994 PMU_PMEVCNTR_EL0(10),
995 PMU_PMEVCNTR_EL0(11),
996 PMU_PMEVCNTR_EL0(12),
997 PMU_PMEVCNTR_EL0(13),
998 PMU_PMEVCNTR_EL0(14),
999 PMU_PMEVCNTR_EL0(15),
1000 PMU_PMEVCNTR_EL0(16),
1001 PMU_PMEVCNTR_EL0(17),
1002 PMU_PMEVCNTR_EL0(18),
1003 PMU_PMEVCNTR_EL0(19),
1004 PMU_PMEVCNTR_EL0(20),
1005 PMU_PMEVCNTR_EL0(21),
1006 PMU_PMEVCNTR_EL0(22),
1007 PMU_PMEVCNTR_EL0(23),
1008 PMU_PMEVCNTR_EL0(24),
1009 PMU_PMEVCNTR_EL0(25),
1010 PMU_PMEVCNTR_EL0(26),
1011 PMU_PMEVCNTR_EL0(27),
1012 PMU_PMEVCNTR_EL0(28),
1013 PMU_PMEVCNTR_EL0(29),
1014 PMU_PMEVCNTR_EL0(30),
1015 /* PMEVTYPERn_EL0 */
1016 PMU_PMEVTYPER_EL0(0),
1017 PMU_PMEVTYPER_EL0(1),
1018 PMU_PMEVTYPER_EL0(2),
1019 PMU_PMEVTYPER_EL0(3),
1020 PMU_PMEVTYPER_EL0(4),
1021 PMU_PMEVTYPER_EL0(5),
1022 PMU_PMEVTYPER_EL0(6),
1023 PMU_PMEVTYPER_EL0(7),
1024 PMU_PMEVTYPER_EL0(8),
1025 PMU_PMEVTYPER_EL0(9),
1026 PMU_PMEVTYPER_EL0(10),
1027 PMU_PMEVTYPER_EL0(11),
1028 PMU_PMEVTYPER_EL0(12),
1029 PMU_PMEVTYPER_EL0(13),
1030 PMU_PMEVTYPER_EL0(14),
1031 PMU_PMEVTYPER_EL0(15),
1032 PMU_PMEVTYPER_EL0(16),
1033 PMU_PMEVTYPER_EL0(17),
1034 PMU_PMEVTYPER_EL0(18),
1035 PMU_PMEVTYPER_EL0(19),
1036 PMU_PMEVTYPER_EL0(20),
1037 PMU_PMEVTYPER_EL0(21),
1038 PMU_PMEVTYPER_EL0(22),
1039 PMU_PMEVTYPER_EL0(23),
1040 PMU_PMEVTYPER_EL0(24),
1041 PMU_PMEVTYPER_EL0(25),
1042 PMU_PMEVTYPER_EL0(26),
1043 PMU_PMEVTYPER_EL0(27),
1044 PMU_PMEVTYPER_EL0(28),
1045 PMU_PMEVTYPER_EL0(29),
1046 PMU_PMEVTYPER_EL0(30),
1047 /*
1048 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
1049 * in 32bit mode. Here we choose to reset it as zero for consistency.
1050 */
1051 { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
1052
1053 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
1054 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
1055 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x70 },
1056 };
1057
1058 static bool trap_dbgidr(struct kvm_vcpu *vcpu,
1059 struct sys_reg_params *p,
1060 const struct sys_reg_desc *r)
1061 {
1062 if (p->is_write) {
1063 return ignore_write(vcpu, p);
1064 } else {
1065 u64 dfr = read_system_reg(SYS_ID_AA64DFR0_EL1);
1066 u64 pfr = read_system_reg(SYS_ID_AA64PFR0_EL1);
1067 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
1068
1069 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1070 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1071 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1072 | (6 << 16) | (el3 << 14) | (el3 << 12));
1073 return true;
1074 }
1075 }
1076
1077 static bool trap_debug32(struct kvm_vcpu *vcpu,
1078 struct sys_reg_params *p,
1079 const struct sys_reg_desc *r)
1080 {
1081 if (p->is_write) {
1082 vcpu_cp14(vcpu, r->reg) = p->regval;
1083 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1084 } else {
1085 p->regval = vcpu_cp14(vcpu, r->reg);
1086 }
1087
1088 return true;
1089 }
1090
1091 /* AArch32 debug register mappings
1092 *
1093 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1094 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1095 *
1096 * All control registers and watchpoint value registers are mapped to
1097 * the lower 32 bits of their AArch64 equivalents. We share the trap
1098 * handlers with the above AArch64 code which checks what mode the
1099 * system is in.
1100 */
1101
1102 static bool trap_xvr(struct kvm_vcpu *vcpu,
1103 struct sys_reg_params *p,
1104 const struct sys_reg_desc *rd)
1105 {
1106 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1107
1108 if (p->is_write) {
1109 u64 val = *dbg_reg;
1110
1111 val &= 0xffffffffUL;
1112 val |= p->regval << 32;
1113 *dbg_reg = val;
1114
1115 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1116 } else {
1117 p->regval = *dbg_reg >> 32;
1118 }
1119
1120 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1121
1122 return true;
1123 }
1124
1125 #define DBG_BCR_BVR_WCR_WVR(n) \
1126 /* DBGBVRn */ \
1127 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1128 /* DBGBCRn */ \
1129 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1130 /* DBGWVRn */ \
1131 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1132 /* DBGWCRn */ \
1133 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1134
1135 #define DBGBXVR(n) \
1136 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
1137
1138 /*
1139 * Trapped cp14 registers. We generally ignore most of the external
1140 * debug, on the principle that they don't really make sense to a
1141 * guest. Revisit this one day, would this principle change.
1142 */
1143 static const struct sys_reg_desc cp14_regs[] = {
1144 /* DBGIDR */
1145 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1146 /* DBGDTRRXext */
1147 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1148
1149 DBG_BCR_BVR_WCR_WVR(0),
1150 /* DBGDSCRint */
1151 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1152 DBG_BCR_BVR_WCR_WVR(1),
1153 /* DBGDCCINT */
1154 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
1155 /* DBGDSCRext */
1156 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
1157 DBG_BCR_BVR_WCR_WVR(2),
1158 /* DBGDTR[RT]Xint */
1159 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1160 /* DBGDTR[RT]Xext */
1161 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1162 DBG_BCR_BVR_WCR_WVR(3),
1163 DBG_BCR_BVR_WCR_WVR(4),
1164 DBG_BCR_BVR_WCR_WVR(5),
1165 /* DBGWFAR */
1166 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1167 /* DBGOSECCR */
1168 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1169 DBG_BCR_BVR_WCR_WVR(6),
1170 /* DBGVCR */
1171 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
1172 DBG_BCR_BVR_WCR_WVR(7),
1173 DBG_BCR_BVR_WCR_WVR(8),
1174 DBG_BCR_BVR_WCR_WVR(9),
1175 DBG_BCR_BVR_WCR_WVR(10),
1176 DBG_BCR_BVR_WCR_WVR(11),
1177 DBG_BCR_BVR_WCR_WVR(12),
1178 DBG_BCR_BVR_WCR_WVR(13),
1179 DBG_BCR_BVR_WCR_WVR(14),
1180 DBG_BCR_BVR_WCR_WVR(15),
1181
1182 /* DBGDRAR (32bit) */
1183 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1184
1185 DBGBXVR(0),
1186 /* DBGOSLAR */
1187 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1188 DBGBXVR(1),
1189 /* DBGOSLSR */
1190 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1191 DBGBXVR(2),
1192 DBGBXVR(3),
1193 /* DBGOSDLR */
1194 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1195 DBGBXVR(4),
1196 /* DBGPRCR */
1197 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1198 DBGBXVR(5),
1199 DBGBXVR(6),
1200 DBGBXVR(7),
1201 DBGBXVR(8),
1202 DBGBXVR(9),
1203 DBGBXVR(10),
1204 DBGBXVR(11),
1205 DBGBXVR(12),
1206 DBGBXVR(13),
1207 DBGBXVR(14),
1208 DBGBXVR(15),
1209
1210 /* DBGDSAR (32bit) */
1211 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1212
1213 /* DBGDEVID2 */
1214 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1215 /* DBGDEVID1 */
1216 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1217 /* DBGDEVID */
1218 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1219 /* DBGCLAIMSET */
1220 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1221 /* DBGCLAIMCLR */
1222 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1223 /* DBGAUTHSTATUS */
1224 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1225 };
1226
1227 /* Trapped cp14 64bit registers */
1228 static const struct sys_reg_desc cp14_64_regs[] = {
1229 /* DBGDRAR (64bit) */
1230 { Op1( 0), CRm( 1), .access = trap_raz_wi },
1231
1232 /* DBGDSAR (64bit) */
1233 { Op1( 0), CRm( 2), .access = trap_raz_wi },
1234 };
1235
1236 /* Macro to expand the PMEVCNTRn register */
1237 #define PMU_PMEVCNTR(n) \
1238 /* PMEVCNTRn */ \
1239 { Op1(0), CRn(0b1110), \
1240 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1241 access_pmu_evcntr }
1242
1243 /* Macro to expand the PMEVTYPERn register */
1244 #define PMU_PMEVTYPER(n) \
1245 /* PMEVTYPERn */ \
1246 { Op1(0), CRn(0b1110), \
1247 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1248 access_pmu_evtyper }
1249
1250 /*
1251 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1252 * depending on the way they are accessed (as a 32bit or a 64bit
1253 * register).
1254 */
1255 static const struct sys_reg_desc cp15_regs[] = {
1256 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
1257
1258 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
1259 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1260 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1261 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
1262 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1263 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1264 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1265 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
1266 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
1267 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
1268 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
1269
1270 /*
1271 * DC{C,I,CI}SW operations:
1272 */
1273 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1274 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1275 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
1276
1277 /* PMU */
1278 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
1279 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1280 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
1281 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
1282 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
1283 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
1284 { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1285 { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
1286 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
1287 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
1288 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
1289 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
1290 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1291 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
1292 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
1293
1294 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
1295 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
1296 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
1297 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
1298
1299 /* ICC_SRE */
1300 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
1301
1302 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
1303
1304 /* PMEVCNTRn */
1305 PMU_PMEVCNTR(0),
1306 PMU_PMEVCNTR(1),
1307 PMU_PMEVCNTR(2),
1308 PMU_PMEVCNTR(3),
1309 PMU_PMEVCNTR(4),
1310 PMU_PMEVCNTR(5),
1311 PMU_PMEVCNTR(6),
1312 PMU_PMEVCNTR(7),
1313 PMU_PMEVCNTR(8),
1314 PMU_PMEVCNTR(9),
1315 PMU_PMEVCNTR(10),
1316 PMU_PMEVCNTR(11),
1317 PMU_PMEVCNTR(12),
1318 PMU_PMEVCNTR(13),
1319 PMU_PMEVCNTR(14),
1320 PMU_PMEVCNTR(15),
1321 PMU_PMEVCNTR(16),
1322 PMU_PMEVCNTR(17),
1323 PMU_PMEVCNTR(18),
1324 PMU_PMEVCNTR(19),
1325 PMU_PMEVCNTR(20),
1326 PMU_PMEVCNTR(21),
1327 PMU_PMEVCNTR(22),
1328 PMU_PMEVCNTR(23),
1329 PMU_PMEVCNTR(24),
1330 PMU_PMEVCNTR(25),
1331 PMU_PMEVCNTR(26),
1332 PMU_PMEVCNTR(27),
1333 PMU_PMEVCNTR(28),
1334 PMU_PMEVCNTR(29),
1335 PMU_PMEVCNTR(30),
1336 /* PMEVTYPERn */
1337 PMU_PMEVTYPER(0),
1338 PMU_PMEVTYPER(1),
1339 PMU_PMEVTYPER(2),
1340 PMU_PMEVTYPER(3),
1341 PMU_PMEVTYPER(4),
1342 PMU_PMEVTYPER(5),
1343 PMU_PMEVTYPER(6),
1344 PMU_PMEVTYPER(7),
1345 PMU_PMEVTYPER(8),
1346 PMU_PMEVTYPER(9),
1347 PMU_PMEVTYPER(10),
1348 PMU_PMEVTYPER(11),
1349 PMU_PMEVTYPER(12),
1350 PMU_PMEVTYPER(13),
1351 PMU_PMEVTYPER(14),
1352 PMU_PMEVTYPER(15),
1353 PMU_PMEVTYPER(16),
1354 PMU_PMEVTYPER(17),
1355 PMU_PMEVTYPER(18),
1356 PMU_PMEVTYPER(19),
1357 PMU_PMEVTYPER(20),
1358 PMU_PMEVTYPER(21),
1359 PMU_PMEVTYPER(22),
1360 PMU_PMEVTYPER(23),
1361 PMU_PMEVTYPER(24),
1362 PMU_PMEVTYPER(25),
1363 PMU_PMEVTYPER(26),
1364 PMU_PMEVTYPER(27),
1365 PMU_PMEVTYPER(28),
1366 PMU_PMEVTYPER(29),
1367 PMU_PMEVTYPER(30),
1368 /* PMCCFILTR */
1369 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
1370 };
1371
1372 static const struct sys_reg_desc cp15_64_regs[] = {
1373 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1374 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
1375 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
1376 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
1377 };
1378
1379 /* Target specific emulation tables */
1380 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
1381
1382 void kvm_register_target_sys_reg_table(unsigned int target,
1383 struct kvm_sys_reg_target_table *table)
1384 {
1385 target_tables[target] = table;
1386 }
1387
1388 /* Get specific register table for this target. */
1389 static const struct sys_reg_desc *get_target_table(unsigned target,
1390 bool mode_is_64,
1391 size_t *num)
1392 {
1393 struct kvm_sys_reg_target_table *table;
1394
1395 table = target_tables[target];
1396 if (mode_is_64) {
1397 *num = table->table64.num;
1398 return table->table64.table;
1399 } else {
1400 *num = table->table32.num;
1401 return table->table32.table;
1402 }
1403 }
1404
1405 #define reg_to_match_value(x) \
1406 ({ \
1407 unsigned long val; \
1408 val = (x)->Op0 << 14; \
1409 val |= (x)->Op1 << 11; \
1410 val |= (x)->CRn << 7; \
1411 val |= (x)->CRm << 3; \
1412 val |= (x)->Op2; \
1413 val; \
1414 })
1415
1416 static int match_sys_reg(const void *key, const void *elt)
1417 {
1418 const unsigned long pval = (unsigned long)key;
1419 const struct sys_reg_desc *r = elt;
1420
1421 return pval - reg_to_match_value(r);
1422 }
1423
1424 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
1425 const struct sys_reg_desc table[],
1426 unsigned int num)
1427 {
1428 unsigned long pval = reg_to_match_value(params);
1429
1430 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
1431 }
1432
1433 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
1434 {
1435 kvm_inject_undefined(vcpu);
1436 return 1;
1437 }
1438
1439 /*
1440 * emulate_cp -- tries to match a sys_reg access in a handling table, and
1441 * call the corresponding trap handler.
1442 *
1443 * @params: pointer to the descriptor of the access
1444 * @table: array of trap descriptors
1445 * @num: size of the trap descriptor array
1446 *
1447 * Return 0 if the access has been handled, and -1 if not.
1448 */
1449 static int emulate_cp(struct kvm_vcpu *vcpu,
1450 struct sys_reg_params *params,
1451 const struct sys_reg_desc *table,
1452 size_t num)
1453 {
1454 const struct sys_reg_desc *r;
1455
1456 if (!table)
1457 return -1; /* Not handled */
1458
1459 r = find_reg(params, table, num);
1460
1461 if (r) {
1462 /*
1463 * Not having an accessor means that we have
1464 * configured a trap that we don't know how to
1465 * handle. This certainly qualifies as a gross bug
1466 * that should be fixed right away.
1467 */
1468 BUG_ON(!r->access);
1469
1470 if (likely(r->access(vcpu, params, r))) {
1471 /* Skip instruction, since it was emulated */
1472 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1473 /* Handled */
1474 return 0;
1475 }
1476 }
1477
1478 /* Not handled */
1479 return -1;
1480 }
1481
1482 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
1483 struct sys_reg_params *params)
1484 {
1485 u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
1486 int cp = -1;
1487
1488 switch(hsr_ec) {
1489 case ESR_ELx_EC_CP15_32:
1490 case ESR_ELx_EC_CP15_64:
1491 cp = 15;
1492 break;
1493 case ESR_ELx_EC_CP14_MR:
1494 case ESR_ELx_EC_CP14_64:
1495 cp = 14;
1496 break;
1497 default:
1498 WARN_ON(1);
1499 }
1500
1501 kvm_err("Unsupported guest CP%d access at: %08lx\n",
1502 cp, *vcpu_pc(vcpu));
1503 print_sys_reg_instr(params);
1504 kvm_inject_undefined(vcpu);
1505 }
1506
1507 /**
1508 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
1509 * @vcpu: The VCPU pointer
1510 * @run: The kvm_run struct
1511 */
1512 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
1513 const struct sys_reg_desc *global,
1514 size_t nr_global,
1515 const struct sys_reg_desc *target_specific,
1516 size_t nr_specific)
1517 {
1518 struct sys_reg_params params;
1519 u32 hsr = kvm_vcpu_get_hsr(vcpu);
1520 int Rt = (hsr >> 5) & 0xf;
1521 int Rt2 = (hsr >> 10) & 0xf;
1522
1523 params.is_aarch32 = true;
1524 params.is_32bit = false;
1525 params.CRm = (hsr >> 1) & 0xf;
1526 params.is_write = ((hsr & 1) == 0);
1527
1528 params.Op0 = 0;
1529 params.Op1 = (hsr >> 16) & 0xf;
1530 params.Op2 = 0;
1531 params.CRn = 0;
1532
1533 /*
1534 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
1535 * backends between AArch32 and AArch64, we get away with it.
1536 */
1537 if (params.is_write) {
1538 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
1539 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
1540 }
1541
1542 if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
1543 goto out;
1544 if (!emulate_cp(vcpu, &params, global, nr_global))
1545 goto out;
1546
1547 unhandled_cp_access(vcpu, &params);
1548
1549 out:
1550 /* Split up the value between registers for the read side */
1551 if (!params.is_write) {
1552 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
1553 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
1554 }
1555
1556 return 1;
1557 }
1558
1559 /**
1560 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
1561 * @vcpu: The VCPU pointer
1562 * @run: The kvm_run struct
1563 */
1564 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
1565 const struct sys_reg_desc *global,
1566 size_t nr_global,
1567 const struct sys_reg_desc *target_specific,
1568 size_t nr_specific)
1569 {
1570 struct sys_reg_params params;
1571 u32 hsr = kvm_vcpu_get_hsr(vcpu);
1572 int Rt = (hsr >> 5) & 0xf;
1573
1574 params.is_aarch32 = true;
1575 params.is_32bit = true;
1576 params.CRm = (hsr >> 1) & 0xf;
1577 params.regval = vcpu_get_reg(vcpu, Rt);
1578 params.is_write = ((hsr & 1) == 0);
1579 params.CRn = (hsr >> 10) & 0xf;
1580 params.Op0 = 0;
1581 params.Op1 = (hsr >> 14) & 0x7;
1582 params.Op2 = (hsr >> 17) & 0x7;
1583
1584 if (!emulate_cp(vcpu, &params, target_specific, nr_specific) ||
1585 !emulate_cp(vcpu, &params, global, nr_global)) {
1586 if (!params.is_write)
1587 vcpu_set_reg(vcpu, Rt, params.regval);
1588 return 1;
1589 }
1590
1591 unhandled_cp_access(vcpu, &params);
1592 return 1;
1593 }
1594
1595 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1596 {
1597 const struct sys_reg_desc *target_specific;
1598 size_t num;
1599
1600 target_specific = get_target_table(vcpu->arch.target, false, &num);
1601 return kvm_handle_cp_64(vcpu,
1602 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
1603 target_specific, num);
1604 }
1605
1606 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1607 {
1608 const struct sys_reg_desc *target_specific;
1609 size_t num;
1610
1611 target_specific = get_target_table(vcpu->arch.target, false, &num);
1612 return kvm_handle_cp_32(vcpu,
1613 cp15_regs, ARRAY_SIZE(cp15_regs),
1614 target_specific, num);
1615 }
1616
1617 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1618 {
1619 return kvm_handle_cp_64(vcpu,
1620 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
1621 NULL, 0);
1622 }
1623
1624 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1625 {
1626 return kvm_handle_cp_32(vcpu,
1627 cp14_regs, ARRAY_SIZE(cp14_regs),
1628 NULL, 0);
1629 }
1630
1631 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
1632 struct sys_reg_params *params)
1633 {
1634 size_t num;
1635 const struct sys_reg_desc *table, *r;
1636
1637 table = get_target_table(vcpu->arch.target, true, &num);
1638
1639 /* Search target-specific then generic table. */
1640 r = find_reg(params, table, num);
1641 if (!r)
1642 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1643
1644 if (likely(r)) {
1645 /*
1646 * Not having an accessor means that we have
1647 * configured a trap that we don't know how to
1648 * handle. This certainly qualifies as a gross bug
1649 * that should be fixed right away.
1650 */
1651 BUG_ON(!r->access);
1652
1653 if (likely(r->access(vcpu, params, r))) {
1654 /* Skip instruction, since it was emulated */
1655 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1656 return 1;
1657 }
1658 /* If access function fails, it should complain. */
1659 } else {
1660 kvm_err("Unsupported guest sys_reg access at: %lx\n",
1661 *vcpu_pc(vcpu));
1662 print_sys_reg_instr(params);
1663 }
1664 kvm_inject_undefined(vcpu);
1665 return 1;
1666 }
1667
1668 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
1669 const struct sys_reg_desc *table, size_t num)
1670 {
1671 unsigned long i;
1672
1673 for (i = 0; i < num; i++)
1674 if (table[i].reset)
1675 table[i].reset(vcpu, &table[i]);
1676 }
1677
1678 /**
1679 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
1680 * @vcpu: The VCPU pointer
1681 * @run: The kvm_run struct
1682 */
1683 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
1684 {
1685 struct sys_reg_params params;
1686 unsigned long esr = kvm_vcpu_get_hsr(vcpu);
1687 int Rt = (esr >> 5) & 0x1f;
1688 int ret;
1689
1690 trace_kvm_handle_sys_reg(esr);
1691
1692 params.is_aarch32 = false;
1693 params.is_32bit = false;
1694 params.Op0 = (esr >> 20) & 3;
1695 params.Op1 = (esr >> 14) & 0x7;
1696 params.CRn = (esr >> 10) & 0xf;
1697 params.CRm = (esr >> 1) & 0xf;
1698 params.Op2 = (esr >> 17) & 0x7;
1699 params.regval = vcpu_get_reg(vcpu, Rt);
1700 params.is_write = !(esr & 1);
1701
1702 ret = emulate_sys_reg(vcpu, &params);
1703
1704 if (!params.is_write)
1705 vcpu_set_reg(vcpu, Rt, params.regval);
1706 return ret;
1707 }
1708
1709 /******************************************************************************
1710 * Userspace API
1711 *****************************************************************************/
1712
1713 static bool index_to_params(u64 id, struct sys_reg_params *params)
1714 {
1715 switch (id & KVM_REG_SIZE_MASK) {
1716 case KVM_REG_SIZE_U64:
1717 /* Any unused index bits means it's not valid. */
1718 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
1719 | KVM_REG_ARM_COPROC_MASK
1720 | KVM_REG_ARM64_SYSREG_OP0_MASK
1721 | KVM_REG_ARM64_SYSREG_OP1_MASK
1722 | KVM_REG_ARM64_SYSREG_CRN_MASK
1723 | KVM_REG_ARM64_SYSREG_CRM_MASK
1724 | KVM_REG_ARM64_SYSREG_OP2_MASK))
1725 return false;
1726 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
1727 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
1728 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
1729 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
1730 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
1731 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
1732 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
1733 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
1734 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
1735 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
1736 return true;
1737 default:
1738 return false;
1739 }
1740 }
1741
1742 const struct sys_reg_desc *find_reg_by_id(u64 id,
1743 struct sys_reg_params *params,
1744 const struct sys_reg_desc table[],
1745 unsigned int num)
1746 {
1747 if (!index_to_params(id, params))
1748 return NULL;
1749
1750 return find_reg(params, table, num);
1751 }
1752
1753 /* Decode an index value, and find the sys_reg_desc entry. */
1754 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
1755 u64 id)
1756 {
1757 size_t num;
1758 const struct sys_reg_desc *table, *r;
1759 struct sys_reg_params params;
1760
1761 /* We only do sys_reg for now. */
1762 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
1763 return NULL;
1764
1765 table = get_target_table(vcpu->arch.target, true, &num);
1766 r = find_reg_by_id(id, &params, table, num);
1767 if (!r)
1768 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1769
1770 /* Not saved in the sys_reg array? */
1771 if (r && !r->reg)
1772 r = NULL;
1773
1774 return r;
1775 }
1776
1777 /*
1778 * These are the invariant sys_reg registers: we let the guest see the
1779 * host versions of these, so they're part of the guest state.
1780 *
1781 * A future CPU may provide a mechanism to present different values to
1782 * the guest, or a future kvm may trap them.
1783 */
1784
1785 #define FUNCTION_INVARIANT(reg) \
1786 static void get_##reg(struct kvm_vcpu *v, \
1787 const struct sys_reg_desc *r) \
1788 { \
1789 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
1790 }
1791
1792 FUNCTION_INVARIANT(midr_el1)
1793 FUNCTION_INVARIANT(ctr_el0)
1794 FUNCTION_INVARIANT(revidr_el1)
1795 FUNCTION_INVARIANT(id_pfr0_el1)
1796 FUNCTION_INVARIANT(id_pfr1_el1)
1797 FUNCTION_INVARIANT(id_dfr0_el1)
1798 FUNCTION_INVARIANT(id_afr0_el1)
1799 FUNCTION_INVARIANT(id_mmfr0_el1)
1800 FUNCTION_INVARIANT(id_mmfr1_el1)
1801 FUNCTION_INVARIANT(id_mmfr2_el1)
1802 FUNCTION_INVARIANT(id_mmfr3_el1)
1803 FUNCTION_INVARIANT(id_isar0_el1)
1804 FUNCTION_INVARIANT(id_isar1_el1)
1805 FUNCTION_INVARIANT(id_isar2_el1)
1806 FUNCTION_INVARIANT(id_isar3_el1)
1807 FUNCTION_INVARIANT(id_isar4_el1)
1808 FUNCTION_INVARIANT(id_isar5_el1)
1809 FUNCTION_INVARIANT(clidr_el1)
1810 FUNCTION_INVARIANT(aidr_el1)
1811
1812 /* ->val is filled in by kvm_sys_reg_table_init() */
1813 static struct sys_reg_desc invariant_sys_regs[] = {
1814 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
1815 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
1816 { SYS_DESC(SYS_ID_PFR0_EL1), NULL, get_id_pfr0_el1 },
1817 { SYS_DESC(SYS_ID_PFR1_EL1), NULL, get_id_pfr1_el1 },
1818 { SYS_DESC(SYS_ID_DFR0_EL1), NULL, get_id_dfr0_el1 },
1819 { SYS_DESC(SYS_ID_AFR0_EL1), NULL, get_id_afr0_el1 },
1820 { SYS_DESC(SYS_ID_MMFR0_EL1), NULL, get_id_mmfr0_el1 },
1821 { SYS_DESC(SYS_ID_MMFR1_EL1), NULL, get_id_mmfr1_el1 },
1822 { SYS_DESC(SYS_ID_MMFR2_EL1), NULL, get_id_mmfr2_el1 },
1823 { SYS_DESC(SYS_ID_MMFR3_EL1), NULL, get_id_mmfr3_el1 },
1824 { SYS_DESC(SYS_ID_ISAR0_EL1), NULL, get_id_isar0_el1 },
1825 { SYS_DESC(SYS_ID_ISAR1_EL1), NULL, get_id_isar1_el1 },
1826 { SYS_DESC(SYS_ID_ISAR2_EL1), NULL, get_id_isar2_el1 },
1827 { SYS_DESC(SYS_ID_ISAR3_EL1), NULL, get_id_isar3_el1 },
1828 { SYS_DESC(SYS_ID_ISAR4_EL1), NULL, get_id_isar4_el1 },
1829 { SYS_DESC(SYS_ID_ISAR5_EL1), NULL, get_id_isar5_el1 },
1830 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },
1831 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
1832 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
1833 };
1834
1835 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
1836 {
1837 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
1838 return -EFAULT;
1839 return 0;
1840 }
1841
1842 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
1843 {
1844 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
1845 return -EFAULT;
1846 return 0;
1847 }
1848
1849 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
1850 {
1851 struct sys_reg_params params;
1852 const struct sys_reg_desc *r;
1853
1854 r = find_reg_by_id(id, &params, invariant_sys_regs,
1855 ARRAY_SIZE(invariant_sys_regs));
1856 if (!r)
1857 return -ENOENT;
1858
1859 return reg_to_user(uaddr, &r->val, id);
1860 }
1861
1862 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
1863 {
1864 struct sys_reg_params params;
1865 const struct sys_reg_desc *r;
1866 int err;
1867 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
1868
1869 r = find_reg_by_id(id, &params, invariant_sys_regs,
1870 ARRAY_SIZE(invariant_sys_regs));
1871 if (!r)
1872 return -ENOENT;
1873
1874 err = reg_from_user(&val, uaddr, id);
1875 if (err)
1876 return err;
1877
1878 /* This is what we mean by invariant: you can't change it. */
1879 if (r->val != val)
1880 return -EINVAL;
1881
1882 return 0;
1883 }
1884
1885 static bool is_valid_cache(u32 val)
1886 {
1887 u32 level, ctype;
1888
1889 if (val >= CSSELR_MAX)
1890 return false;
1891
1892 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
1893 level = (val >> 1);
1894 ctype = (cache_levels >> (level * 3)) & 7;
1895
1896 switch (ctype) {
1897 case 0: /* No cache */
1898 return false;
1899 case 1: /* Instruction cache only */
1900 return (val & 1);
1901 case 2: /* Data cache only */
1902 case 4: /* Unified cache */
1903 return !(val & 1);
1904 case 3: /* Separate instruction and data caches */
1905 return true;
1906 default: /* Reserved: we can't know instruction or data. */
1907 return false;
1908 }
1909 }
1910
1911 static int demux_c15_get(u64 id, void __user *uaddr)
1912 {
1913 u32 val;
1914 u32 __user *uval = uaddr;
1915
1916 /* Fail if we have unknown bits set. */
1917 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1918 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1919 return -ENOENT;
1920
1921 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1922 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1923 if (KVM_REG_SIZE(id) != 4)
1924 return -ENOENT;
1925 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1926 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1927 if (!is_valid_cache(val))
1928 return -ENOENT;
1929
1930 return put_user(get_ccsidr(val), uval);
1931 default:
1932 return -ENOENT;
1933 }
1934 }
1935
1936 static int demux_c15_set(u64 id, void __user *uaddr)
1937 {
1938 u32 val, newval;
1939 u32 __user *uval = uaddr;
1940
1941 /* Fail if we have unknown bits set. */
1942 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1943 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1944 return -ENOENT;
1945
1946 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1947 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1948 if (KVM_REG_SIZE(id) != 4)
1949 return -ENOENT;
1950 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1951 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1952 if (!is_valid_cache(val))
1953 return -ENOENT;
1954
1955 if (get_user(newval, uval))
1956 return -EFAULT;
1957
1958 /* This is also invariant: you can't change it. */
1959 if (newval != get_ccsidr(val))
1960 return -EINVAL;
1961 return 0;
1962 default:
1963 return -ENOENT;
1964 }
1965 }
1966
1967 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1968 {
1969 const struct sys_reg_desc *r;
1970 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
1971
1972 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1973 return demux_c15_get(reg->id, uaddr);
1974
1975 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
1976 return -ENOENT;
1977
1978 r = index_to_sys_reg_desc(vcpu, reg->id);
1979 if (!r)
1980 return get_invariant_sys_reg(reg->id, uaddr);
1981
1982 if (r->get_user)
1983 return (r->get_user)(vcpu, r, reg, uaddr);
1984
1985 return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
1986 }
1987
1988 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1989 {
1990 const struct sys_reg_desc *r;
1991 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
1992
1993 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1994 return demux_c15_set(reg->id, uaddr);
1995
1996 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
1997 return -ENOENT;
1998
1999 r = index_to_sys_reg_desc(vcpu, reg->id);
2000 if (!r)
2001 return set_invariant_sys_reg(reg->id, uaddr);
2002
2003 if (r->set_user)
2004 return (r->set_user)(vcpu, r, reg, uaddr);
2005
2006 return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2007 }
2008
2009 static unsigned int num_demux_regs(void)
2010 {
2011 unsigned int i, count = 0;
2012
2013 for (i = 0; i < CSSELR_MAX; i++)
2014 if (is_valid_cache(i))
2015 count++;
2016
2017 return count;
2018 }
2019
2020 static int write_demux_regids(u64 __user *uindices)
2021 {
2022 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2023 unsigned int i;
2024
2025 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2026 for (i = 0; i < CSSELR_MAX; i++) {
2027 if (!is_valid_cache(i))
2028 continue;
2029 if (put_user(val | i, uindices))
2030 return -EFAULT;
2031 uindices++;
2032 }
2033 return 0;
2034 }
2035
2036 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2037 {
2038 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2039 KVM_REG_ARM64_SYSREG |
2040 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2041 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2042 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2043 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2044 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2045 }
2046
2047 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2048 {
2049 if (!*uind)
2050 return true;
2051
2052 if (put_user(sys_reg_to_index(reg), *uind))
2053 return false;
2054
2055 (*uind)++;
2056 return true;
2057 }
2058
2059 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
2060 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2061 {
2062 const struct sys_reg_desc *i1, *i2, *end1, *end2;
2063 unsigned int total = 0;
2064 size_t num;
2065
2066 /* We check for duplicates here, to allow arch-specific overrides. */
2067 i1 = get_target_table(vcpu->arch.target, true, &num);
2068 end1 = i1 + num;
2069 i2 = sys_reg_descs;
2070 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2071
2072 BUG_ON(i1 == end1 || i2 == end2);
2073
2074 /* Walk carefully, as both tables may refer to the same register. */
2075 while (i1 || i2) {
2076 int cmp = cmp_sys_reg(i1, i2);
2077 /* target-specific overrides generic entry. */
2078 if (cmp <= 0) {
2079 /* Ignore registers we trap but don't save. */
2080 if (i1->reg) {
2081 if (!copy_reg_to_user(i1, &uind))
2082 return -EFAULT;
2083 total++;
2084 }
2085 } else {
2086 /* Ignore registers we trap but don't save. */
2087 if (i2->reg) {
2088 if (!copy_reg_to_user(i2, &uind))
2089 return -EFAULT;
2090 total++;
2091 }
2092 }
2093
2094 if (cmp <= 0 && ++i1 == end1)
2095 i1 = NULL;
2096 if (cmp >= 0 && ++i2 == end2)
2097 i2 = NULL;
2098 }
2099 return total;
2100 }
2101
2102 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2103 {
2104 return ARRAY_SIZE(invariant_sys_regs)
2105 + num_demux_regs()
2106 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2107 }
2108
2109 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2110 {
2111 unsigned int i;
2112 int err;
2113
2114 /* Then give them all the invariant registers' indices. */
2115 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2116 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2117 return -EFAULT;
2118 uindices++;
2119 }
2120
2121 err = walk_sys_regs(vcpu, uindices);
2122 if (err < 0)
2123 return err;
2124 uindices += err;
2125
2126 return write_demux_regids(uindices);
2127 }
2128
2129 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
2130 {
2131 unsigned int i;
2132
2133 for (i = 1; i < n; i++) {
2134 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2135 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2136 return 1;
2137 }
2138 }
2139
2140 return 0;
2141 }
2142
2143 void kvm_sys_reg_table_init(void)
2144 {
2145 unsigned int i;
2146 struct sys_reg_desc clidr;
2147
2148 /* Make sure tables are unique and in order. */
2149 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
2150 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
2151 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
2152 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
2153 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
2154 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
2155
2156 /* We abuse the reset function to overwrite the table itself. */
2157 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2158 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2159
2160 /*
2161 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
2162 *
2163 * If software reads the Cache Type fields from Ctype1
2164 * upwards, once it has seen a value of 0b000, no caches
2165 * exist at further-out levels of the hierarchy. So, for
2166 * example, if Ctype3 is the first Cache Type field with a
2167 * value of 0b000, the values of Ctype4 to Ctype7 must be
2168 * ignored.
2169 */
2170 get_clidr_el1(NULL, &clidr); /* Ugly... */
2171 cache_levels = clidr.val;
2172 for (i = 0; i < 7; i++)
2173 if (((cache_levels >> (i*3)) & 7) == 0)
2174 break;
2175 /* Clear all higher bits. */
2176 cache_levels &= (1 << (i*3))-1;
2177 }
2178
2179 /**
2180 * kvm_reset_sys_regs - sets system registers to reset value
2181 * @vcpu: The VCPU pointer
2182 *
2183 * This function finds the right table above and sets the registers on the
2184 * virtual CPU struct to their architecturally defined reset values.
2185 */
2186 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2187 {
2188 size_t num;
2189 const struct sys_reg_desc *table;
2190
2191 /* Catch someone adding a register without putting in reset entry. */
2192 memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
2193
2194 /* Generic chip reset first (so target could override). */
2195 reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2196
2197 table = get_target_table(vcpu->arch.target, true, &num);
2198 reset_sys_reg_descs(vcpu, table, num);
2199
2200 for (num = 1; num < NR_SYS_REGS; num++)
2201 if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
2202 panic("Didn't reset vcpu_sys_reg(%zi)", num);
2203 }
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