2 * Favr-32 board-specific setup code.
4 * Copyright (C) 2008 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/clk.h>
11 #include <linux/etherdevice.h>
12 #include <linux/bootmem.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/types.h>
17 #include <linux/linkage.h>
18 #include <linux/gpio.h>
19 #include <linux/leds.h>
20 #include <linux/atmel-pwm-bl.h>
21 #include <linux/spi/spi.h>
22 #include <linux/spi/ads7846.h>
24 #include <video/atmel_lcdc.h>
26 #include <asm/setup.h>
28 #include <mach/at32ap700x.h>
29 #include <mach/init.h>
30 #include <mach/board.h>
31 #include <mach/portmux.h>
33 /* Oscillator frequencies. These are board-specific */
34 unsigned long at32_board_osc_rates
[3] = {
35 [0] = 32768, /* 32.768 kHz on RTC osc */
36 [1] = 20000000, /* 20 MHz on osc0 */
37 [2] = 12000000, /* 12 MHz on osc1 */
40 /* Initialized by bootloader-specific startup code. */
41 struct tag
*bootloader_tags __initdata
;
46 static struct eth_addr __initdata hw_addr
[1];
47 static struct eth_platform_data __initdata eth_data
[1] = {
49 .phy_mask
= ~(1U << 1),
53 static int ads7843_get_pendown_state(void)
55 return !gpio_get_value(GPIO_PIN_PB(3));
58 static struct ads7846_platform_data ads7843_data
= {
60 .get_pendown_state
= ads7843_get_pendown_state
,
63 * Values below are for debounce filtering, these can be experimented
71 static struct spi_board_info __initdata spi1_board_info
[] = {
73 /* ADS7843 touch controller */
74 .modalias
= "ads7846",
75 .max_speed_hz
= 2000000,
78 .platform_data
= &ads7843_data
,
82 static struct fb_videomode __initdata lb104v03_modes
[] = {
84 .name
= "640x480 @ 50",
86 .xres
= 640, .yres
= 480,
87 .pixclock
= KHZ2PICOS(25100),
89 .left_margin
= 90, .right_margin
= 70,
90 .upper_margin
= 30, .lower_margin
= 15,
91 .hsync_len
= 12, .vsync_len
= 2,
94 .vmode
= FB_VMODE_NONINTERLACED
,
98 static struct fb_monspecs __initdata favr32_default_monspecs
= {
100 .monitor
= "LB104V03",
101 .modedb
= lb104v03_modes
,
102 .modedb_len
= ARRAY_SIZE(lb104v03_modes
),
110 struct atmel_lcdfb_info __initdata favr32_lcdc_data
= {
112 .default_dmacon
= ATMEL_LCDC_DMAEN
| ATMEL_LCDC_DMA2DEN
,
113 .default_lcdcon2
= (ATMEL_LCDC_DISTYPE_TFT
114 | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE
115 | ATMEL_LCDC_MEMOR_BIG
),
116 .default_monspecs
= &favr32_default_monspecs
,
120 static struct gpio_led favr32_leds
[] = {
123 .gpio
= GPIO_PIN_PE(19),
124 .default_trigger
= "heartbeat",
129 .gpio
= GPIO_PIN_PE(20),
134 static struct gpio_led_platform_data favr32_led_data
= {
135 .num_leds
= ARRAY_SIZE(favr32_leds
),
139 static struct platform_device favr32_led_dev
= {
143 .platform_data
= &favr32_led_data
,
148 * The next two functions should go away as the boot loader is
149 * supposed to initialize the macb address registers with a valid
150 * ethernet address. But we need to keep it around for a while until
151 * we can be reasonably sure the boot loader does this.
153 * The phy_id is ignored as the driver will probe for it.
155 static int __init
parse_tag_ethernet(struct tag
*tag
)
159 i
= tag
->u
.ethernet
.mac_index
;
160 if (i
< ARRAY_SIZE(hw_addr
))
161 memcpy(hw_addr
[i
].addr
, tag
->u
.ethernet
.hw_address
,
162 sizeof(hw_addr
[i
].addr
));
166 __tagtable(ATAG_ETHERNET
, parse_tag_ethernet
);
168 static void __init
set_hw_addr(struct platform_device
*pdev
)
170 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
177 if (pdev
->id
>= ARRAY_SIZE(hw_addr
))
180 addr
= hw_addr
[pdev
->id
].addr
;
181 if (!is_valid_ether_addr(addr
))
185 * Since this is board-specific code, we'll cheat and use the
186 * physical address directly as we happen to know that it's
187 * the same as the virtual address.
189 regs
= (void __iomem __force
*)res
->start
;
190 pclk
= clk_get(&pdev
->dev
, "pclk");
195 __raw_writel((addr
[3] << 24) | (addr
[2] << 16)
196 | (addr
[1] << 8) | addr
[0], regs
+ 0x98);
197 __raw_writel((addr
[5] << 8) | addr
[4], regs
+ 0x9c);
202 void __init
favr32_setup_leds(void)
206 for (i
= 0; i
< ARRAY_SIZE(favr32_leds
); i
++)
207 at32_select_gpio(favr32_leds
[i
].gpio
, AT32_GPIOF_OUTPUT
);
209 platform_device_register(&favr32_led_dev
);
212 static struct atmel_pwm_bl_platform_data atmel_pwm_bl_pdata
= {
214 .pwm_frequency
= 200000,
215 .pwm_compare_max
= 345,
219 .gpio_on
= GPIO_PIN_PA(28),
223 static struct platform_device atmel_pwm_bl_dev
= {
224 .name
= "atmel-pwm-bl",
227 .platform_data
= &atmel_pwm_bl_pdata
,
231 static void __init
favr32_setup_atmel_pwm_bl(void)
233 platform_device_register(&atmel_pwm_bl_dev
);
234 at32_select_gpio(atmel_pwm_bl_pdata
.gpio_on
, 0);
237 void __init
setup_board(void)
239 at32_map_usart(3, 0); /* USART 3 => /dev/ttyS0 */
240 at32_setup_serial_console(0);
243 static int __init
set_abdac_rate(struct platform_device
*pdev
)
253 osc1
= clk_get(NULL
, "osc1");
255 retval
= PTR_ERR(osc1
);
259 pll1
= clk_get(NULL
, "pll1");
261 retval
= PTR_ERR(pll1
);
265 abdac
= clk_get(&pdev
->dev
, "sample_clk");
267 retval
= PTR_ERR(abdac
);
271 retval
= clk_set_parent(pll1
, osc1
);
276 * Rate is 32000 to 50000 and ABDAC oversamples 256x. Multiply, in
277 * power of 2, to a value above 80 MHz. Power of 2 so it is possible
278 * for the generic clock to divide it down again and 80 MHz is the
279 * lowest frequency for the PLL.
281 retval
= clk_round_rate(pll1
,
282 CONFIG_BOARD_FAVR32_ABDAC_RATE
* 256 * 16);
286 retval
= clk_set_rate(pll1
, retval
);
290 retval
= clk_set_parent(abdac
, pll1
);
304 static int __init
favr32_init(void)
307 * Favr-32 uses 32-bit SDRAM interface. Reserve the SDRAM-specific
308 * pins so that nobody messes with them.
310 at32_reserve_pin(GPIO_PIN_PE(0)); /* DATA[16] */
311 at32_reserve_pin(GPIO_PIN_PE(1)); /* DATA[17] */
312 at32_reserve_pin(GPIO_PIN_PE(2)); /* DATA[18] */
313 at32_reserve_pin(GPIO_PIN_PE(3)); /* DATA[19] */
314 at32_reserve_pin(GPIO_PIN_PE(4)); /* DATA[20] */
315 at32_reserve_pin(GPIO_PIN_PE(5)); /* DATA[21] */
316 at32_reserve_pin(GPIO_PIN_PE(6)); /* DATA[22] */
317 at32_reserve_pin(GPIO_PIN_PE(7)); /* DATA[23] */
318 at32_reserve_pin(GPIO_PIN_PE(8)); /* DATA[24] */
319 at32_reserve_pin(GPIO_PIN_PE(9)); /* DATA[25] */
320 at32_reserve_pin(GPIO_PIN_PE(10)); /* DATA[26] */
321 at32_reserve_pin(GPIO_PIN_PE(11)); /* DATA[27] */
322 at32_reserve_pin(GPIO_PIN_PE(12)); /* DATA[28] */
323 at32_reserve_pin(GPIO_PIN_PE(13)); /* DATA[29] */
324 at32_reserve_pin(GPIO_PIN_PE(14)); /* DATA[30] */
325 at32_reserve_pin(GPIO_PIN_PE(15)); /* DATA[31] */
326 at32_reserve_pin(GPIO_PIN_PE(26)); /* SDCS */
328 at32_select_gpio(GPIO_PIN_PB(3), 0); /* IRQ from ADS7843 */
330 at32_add_system_devices();
332 at32_add_device_usart(0);
334 set_hw_addr(at32_add_device_eth(0, ð_data
[0]));
336 spi1_board_info
[0].irq
= gpio_to_irq(GPIO_PIN_PB(3));
338 set_abdac_rate(at32_add_device_abdac(0));
340 at32_add_device_pwm(1 << atmel_pwm_bl_pdata
.pwm_channel
);
341 at32_add_device_spi(1, spi1_board_info
, ARRAY_SIZE(spi1_board_info
));
342 at32_add_device_mci(0, NULL
);
343 at32_add_device_usba(0, NULL
);
344 at32_add_device_lcdc(0, &favr32_lcdc_data
, fbmem_start
, fbmem_size
, 0);
348 favr32_setup_atmel_pwm_bl();
352 postcore_initcall(favr32_init
);