arch/avr32/kernel/time.c

   1 /*
   2  * Copyright (C) 2004-2006 Atmel Corporation
   3  *
   4  * Based on MIPS implementation arch/mips/kernel/time.c
   5  *   Copyright 2001 MontaVista Software Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clocksource.h>
  14 #include <linux/time.h>
  15 #include <linux/module.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irq.h>
  18 #include <linux/kernel_stat.h>
  19 #include <linux/errno.h>
  20 #include <linux/init.h>
  21 #include <linux/profile.h>
  22 #include <linux/sysdev.h>
  23
  24 #include <asm/div64.h>
  25 #include <asm/sysreg.h>
  26 #include <asm/io.h>
  27 #include <asm/sections.h>
  28
  29 static cycle_t read_cycle_count(void)
  30 {
  31         return (cycle_t)sysreg_read(COUNT);
  32 }
  33
  34 static struct clocksource clocksource_avr32 = {
  35         .name           = "avr32",
  36         .rating         = 350,
  37         .read           = read_cycle_count,
  38         .mask           = CLOCKSOURCE_MASK(32),
  39         .shift          = 16,
  40         .is_continuous  = 1,
  41 };
  42
  43 /*
  44  * By default we provide the null RTC ops
  45  */
  46 static unsigned long null_rtc_get_time(void)
  47 {
  48         return mktime(2004, 1, 1, 0, 0, 0);
  49 }
  50
  51 static int null_rtc_set_time(unsigned long sec)
  52 {
  53         return 0;
  54 }
  55
  56 static unsigned long (*rtc_get_time)(void) = null_rtc_get_time;
  57 static int (*rtc_set_time)(unsigned long) = null_rtc_set_time;
  58
  59 /* how many counter cycles in a jiffy? */
  60 static unsigned long cycles_per_jiffy;
  61
  62 /* cycle counter value at the previous timer interrupt */
  63 static unsigned int timerhi, timerlo;
  64
  65 /* the count value for the next timer interrupt */
  66 static unsigned int expirelo;
  67
  68 static void avr32_timer_ack(void)
  69 {
  70         unsigned int count;
  71
  72         /* Ack this timer interrupt and set the next one */
  73         expirelo += cycles_per_jiffy;
  74         if (expirelo == 0) {
  75                 printk(KERN_DEBUG "expirelo == 0\n");
  76                 sysreg_write(COMPARE, expirelo + 1);
  77         } else {
  78                 sysreg_write(COMPARE, expirelo);
  79         }
  80
  81         /* Check to see if we have missed any timer interrupts */
  82         count = sysreg_read(COUNT);
  83         if ((count - expirelo) < 0x7fffffff) {
  84                 expirelo = count + cycles_per_jiffy;
  85                 sysreg_write(COMPARE, expirelo);
  86         }
  87 }
  88
  89 static unsigned int avr32_hpt_read(void)
  90 {
  91         return sysreg_read(COUNT);
  92 }
  93
  94 /*
  95  * Taken from MIPS c0_hpt_timer_init().
  96  *
  97  * Why is it so complicated, and what is "count"?  My assumption is
  98  * that `count' specifies the "reference cycle", i.e. the cycle since
  99  * reset that should mean "zero". The reason COUNT is written twice is
 100  * probably to make sure we don't get any timer interrupts while we
 101  * are messing with the counter.
 102  */
 103 static void avr32_hpt_init(unsigned int count)
 104 {
 105         count = sysreg_read(COUNT) - count;
 106         expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
 107         sysreg_write(COUNT, expirelo - cycles_per_jiffy);
 108         sysreg_write(COMPARE, expirelo);
 109         sysreg_write(COUNT, count);
 110 }
 111
 112 /*
 113  * Scheduler clock - returns current time in nanosec units.
 114  */
 115 unsigned long long sched_clock(void)
 116 {
 117         /* There must be better ways...? */
 118         return (unsigned long long)jiffies * (1000000000 / HZ);
 119 }
 120
 121 /*
 122  * local_timer_interrupt() does profiling and process accounting on a
 123  * per-CPU basis.
 124  *
 125  * In UP mode, it is invoked from the (global) timer_interrupt.
 126  */
 127 static void local_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 128 {
 129         if (current->pid)
 130                 profile_tick(CPU_PROFILING, regs);
 131         update_process_times(user_mode(regs));
 132 }
 133
 134 static irqreturn_t
 135 timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 136 {
 137         unsigned int count;
 138
 139         /* ack timer interrupt and try to set next interrupt */
 140         count = avr32_hpt_read();
 141         avr32_timer_ack();
 142
 143         /* Update timerhi/timerlo for intra-jiffy calibration */
 144         timerhi += count < timerlo;     /* Wrap around */
 145         timerlo = count;
 146
 147         /*
 148          * Call the generic timer interrupt handler
 149          */
 150         write_seqlock(&xtime_lock);
 151         do_timer(regs);
 152         write_sequnlock(&xtime_lock);
 153
 154         /*
 155          * In UP mode, we call local_timer_interrupt() to do profiling
 156          * and process accounting.
 157          *
 158          * SMP is not supported yet.
 159          */
 160         local_timer_interrupt(irq, dev_id, regs);
 161
 162         return IRQ_HANDLED;
 163 }
 164
 165 static struct irqaction timer_irqaction = {
 166         .handler        = timer_interrupt,
 167         .flags          = IRQF_DISABLED,
 168         .name           = "timer",
 169 };
 170
 171 void __init time_init(void)
 172 {
 173         unsigned long mult, shift, count_hz;
 174         int ret;
 175
 176         xtime.tv_sec = rtc_get_time();
 177         xtime.tv_nsec = 0;
 178
 179         set_normalized_timespec(&wall_to_monotonic,
 180                                 -xtime.tv_sec, -xtime.tv_nsec);
 181
 182         printk("Before time_init: count=%08lx, compare=%08lx\n",
 183                (unsigned long)sysreg_read(COUNT),
 184                (unsigned long)sysreg_read(COMPARE));
 185
 186         count_hz = clk_get_rate(boot_cpu_data.clk);
 187         shift = clocksource_avr32.shift;
 188         mult = clocksource_hz2mult(count_hz, shift);
 189         clocksource_avr32.mult = mult;
 190
 191         printk("Cycle counter: mult=%lu, shift=%lu\n", mult, shift);
 192
 193         {
 194                 u64 tmp;
 195
 196                 tmp = TICK_NSEC;
 197                 tmp <<= shift;
 198                 tmp += mult / 2;
 199                 do_div(tmp, mult);
 200
 201                 cycles_per_jiffy = tmp;
 202         }
 203
 204         /* This sets up the high precision timer for the first interrupt. */
 205         avr32_hpt_init(avr32_hpt_read());
 206
 207         printk("After time_init: count=%08lx, compare=%08lx\n",
 208                (unsigned long)sysreg_read(COUNT),
 209                (unsigned long)sysreg_read(COMPARE));
 210
 211         ret = clocksource_register(&clocksource_avr32);
 212         if (ret)
 213                 printk(KERN_ERR
 214                        "timer: could not register clocksource: %d\n", ret);
 215
 216         ret = setup_irq(0, &timer_irqaction);
 217         if (ret)
 218                 printk("timer: could not request IRQ 0: %d\n", ret);
 219 }
 220
 221 static struct sysdev_class timer_class = {
 222         set_kset_name("timer"),
 223 };
 224
 225 static struct sys_device timer_device = {
 226         .id     = 0,
 227         .cls    = &timer_class,
 228 };
 229
 230 static int __init init_timer_sysfs(void)
 231 {
 232         int err = sysdev_class_register(&timer_class);
 233         if (!err)
 234                 err = sysdev_register(&timer_device);
 235         return err;
 236 }
 237
 238 device_initcall(init_timer_sysfs);