arch/blackfin/Kconfig

   1 config MMU
   2         def_bool n
   3
   4 config FPU
   5         def_bool n
   6
   7 config RWSEM_GENERIC_SPINLOCK
   8         def_bool y
   9
  10 config RWSEM_XCHGADD_ALGORITHM
  11         def_bool n
  12
  13 config BLACKFIN
  14         def_bool y
  15         select HAVE_ARCH_KGDB
  16         select HAVE_ARCH_TRACEHOOK
  17         select HAVE_DYNAMIC_FTRACE
  18         select HAVE_FTRACE_MCOUNT_RECORD
  19         select HAVE_FUNCTION_GRAPH_TRACER
  20         select HAVE_FUNCTION_TRACER
  21         select HAVE_IDE
  22         select HAVE_KERNEL_GZIP if RAMKERNEL
  23         select HAVE_KERNEL_BZIP2 if RAMKERNEL
  24         select HAVE_KERNEL_LZMA if RAMKERNEL
  25         select HAVE_KERNEL_LZO if RAMKERNEL
  26         select HAVE_OPROFILE
  27         select HAVE_PERF_EVENTS
  28         select ARCH_HAVE_CUSTOM_GPIO_H
  29         select GPIOLIB
  30         select HAVE_UID16
  31         select HAVE_UNDERSCORE_SYMBOL_PREFIX
  32         select VIRT_TO_BUS
  33         select ARCH_WANT_IPC_PARSE_VERSION
  34         select GENERIC_ATOMIC64
  35         select GENERIC_IRQ_PROBE
  36         select GENERIC_IRQ_SHOW
  37         select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
  38         select GENERIC_SMP_IDLE_THREAD
  39         select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
  40         select HAVE_MOD_ARCH_SPECIFIC
  41         select MODULES_USE_ELF_RELA
  42         select HAVE_DEBUG_STACKOVERFLOW
  43         select HAVE_NMI
  44
  45 config GENERIC_CSUM
  46         def_bool y
  47
  48 config GENERIC_BUG
  49         def_bool y
  50         depends on BUG
  51
  52 config ZONE_DMA
  53         def_bool y
  54
  55 config FORCE_MAX_ZONEORDER
  56         int
  57         default "14"
  58
  59 config GENERIC_CALIBRATE_DELAY
  60         def_bool y
  61
  62 config LOCKDEP_SUPPORT
  63         def_bool y
  64
  65 config STACKTRACE_SUPPORT
  66         def_bool y
  67
  68 config TRACE_IRQFLAGS_SUPPORT
  69         def_bool y
  70
  71 source "init/Kconfig"
  72
  73 source "kernel/Kconfig.preempt"
  74
  75 source "kernel/Kconfig.freezer"
  76
  77 menu "Blackfin Processor Options"
  78
  79 comment "Processor and Board Settings"
  80
  81 choice
  82         prompt "CPU"
  83         default BF533
  84
  85 config BF512
  86         bool "BF512"
  87         help
  88           BF512 Processor Support.
  89
  90 config BF514
  91         bool "BF514"
  92         help
  93           BF514 Processor Support.
  94
  95 config BF516
  96         bool "BF516"
  97         help
  98           BF516 Processor Support.
  99
 100 config BF518
 101         bool "BF518"
 102         help
 103           BF518 Processor Support.
 104
 105 config BF522
 106         bool "BF522"
 107         help
 108           BF522 Processor Support.
 109
 110 config BF523
 111         bool "BF523"
 112         help
 113           BF523 Processor Support.
 114
 115 config BF524
 116         bool "BF524"
 117         help
 118           BF524 Processor Support.
 119
 120 config BF525
 121         bool "BF525"
 122         help
 123           BF525 Processor Support.
 124
 125 config BF526
 126         bool "BF526"
 127         help
 128           BF526 Processor Support.
 129
 130 config BF527
 131         bool "BF527"
 132         help
 133           BF527 Processor Support.
 134
 135 config BF531
 136         bool "BF531"
 137         help
 138           BF531 Processor Support.
 139
 140 config BF532
 141         bool "BF532"
 142         help
 143           BF532 Processor Support.
 144
 145 config BF533
 146         bool "BF533"
 147         help
 148           BF533 Processor Support.
 149
 150 config BF534
 151         bool "BF534"
 152         help
 153           BF534 Processor Support.
 154
 155 config BF536
 156         bool "BF536"
 157         help
 158           BF536 Processor Support.
 159
 160 config BF537
 161         bool "BF537"
 162         help
 163           BF537 Processor Support.
 164
 165 config BF538
 166         bool "BF538"
 167         help
 168           BF538 Processor Support.
 169
 170 config BF539
 171         bool "BF539"
 172         help
 173           BF539 Processor Support.
 174
 175 config BF542_std
 176         bool "BF542"
 177         help
 178           BF542 Processor Support.
 179
 180 config BF542M
 181         bool "BF542m"
 182         help
 183           BF542 Processor Support.
 184
 185 config BF544_std
 186         bool "BF544"
 187         help
 188           BF544 Processor Support.
 189
 190 config BF544M
 191         bool "BF544m"
 192         help
 193           BF544 Processor Support.
 194
 195 config BF547_std
 196         bool "BF547"
 197         help
 198           BF547 Processor Support.
 199
 200 config BF547M
 201         bool "BF547m"
 202         help
 203           BF547 Processor Support.
 204
 205 config BF548_std
 206         bool "BF548"
 207         help
 208           BF548 Processor Support.
 209
 210 config BF548M
 211         bool "BF548m"
 212         help
 213           BF548 Processor Support.
 214
 215 config BF549_std
 216         bool "BF549"
 217         help
 218           BF549 Processor Support.
 219
 220 config BF549M
 221         bool "BF549m"
 222         help
 223           BF549 Processor Support.
 224
 225 config BF561
 226         bool "BF561"
 227         help
 228           BF561 Processor Support.
 229
 230 config BF609
 231         bool "BF609"
 232         select CLKDEV_LOOKUP
 233         help
 234           BF609 Processor Support.
 235
 236 endchoice
 237
 238 config SMP
 239         depends on BF561
 240         select TICKSOURCE_CORETMR
 241         bool "Symmetric multi-processing support"
 242         ---help---
 243           This enables support for systems with more than one CPU,
 244           like the dual core BF561. If you have a system with only one
 245           CPU, say N. If you have a system with more than one CPU, say Y.
 246
 247           If you don't know what to do here, say N.
 248
 249 config NR_CPUS
 250         int
 251         depends on SMP
 252         default 2 if BF561
 253
 254 config HOTPLUG_CPU
 255         bool "Support for hot-pluggable CPUs"
 256         depends on SMP
 257         default y
 258
 259 config BF_REV_MIN
 260         int
 261         default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
 262         default 2 if (BF537 || BF536 || BF534)
 263         default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
 264         default 4 if (BF538 || BF539)
 265
 266 config BF_REV_MAX
 267         int
 268         default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
 269         default 3 if (BF537 || BF536 || BF534 || BF54xM)
 270         default 5 if (BF561 || BF538 || BF539)
 271         default 6 if (BF533 || BF532 || BF531)
 272
 273 choice
 274         prompt "Silicon Rev"
 275         default BF_REV_0_0 if (BF51x || BF52x || BF60x)
 276         default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
 277         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
 278
 279 config BF_REV_0_0
 280         bool "0.0"
 281         depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
 282
 283 config BF_REV_0_1
 284         bool "0.1"
 285         depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
 286
 287 config BF_REV_0_2
 288         bool "0.2"
 289         depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
 290
 291 config BF_REV_0_3
 292         bool "0.3"
 293         depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 294
 295 config BF_REV_0_4
 296         bool "0.4"
 297         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x)
 298
 299 config BF_REV_0_5
 300         bool "0.5"
 301         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 302
 303 config BF_REV_0_6
 304         bool "0.6"
 305         depends on (BF533 || BF532 || BF531)
 306
 307 config BF_REV_ANY
 308         bool "any"
 309
 310 config BF_REV_NONE
 311         bool "none"
 312
 313 endchoice
 314
 315 config BF53x
 316         bool
 317         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 318         default y
 319
 320 config GPIO_ADI
 321         def_bool y
 322         depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561)
 323
 324 config PINCTRL
 325         def_bool y
 326         depends on BF54x || BF60x
 327
 328 config MEM_MT48LC64M4A2FB_7E
 329         bool
 330         depends on (BFIN533_STAMP)
 331         default y
 332
 333 config MEM_MT48LC16M16A2TG_75
 334         bool
 335         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 336                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
 337                 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
 338                 || BFIN527_BLUETECHNIX_CM)
 339         default y
 340
 341 config MEM_MT48LC32M8A2_75
 342         bool
 343         depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 344         default y
 345
 346 config MEM_MT48LC8M32B2B5_7
 347         bool
 348         depends on (BFIN561_BLUETECHNIX_CM)
 349         default y
 350
 351 config MEM_MT48LC32M16A2TG_75
 352         bool
 353         depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
 354         default y
 355
 356 config MEM_MT48H32M16LFCJ_75
 357         bool
 358         depends on (BFIN526_EZBRD)
 359         default y
 360
 361 config MEM_MT47H64M16
 362         bool
 363         depends on (BFIN609_EZKIT)
 364         default y
 365
 366 source "arch/blackfin/mach-bf518/Kconfig"
 367 source "arch/blackfin/mach-bf527/Kconfig"
 368 source "arch/blackfin/mach-bf533/Kconfig"
 369 source "arch/blackfin/mach-bf561/Kconfig"
 370 source "arch/blackfin/mach-bf537/Kconfig"
 371 source "arch/blackfin/mach-bf538/Kconfig"
 372 source "arch/blackfin/mach-bf548/Kconfig"
 373 source "arch/blackfin/mach-bf609/Kconfig"
 374
 375 menu "Board customizations"
 376
 377 config CMDLINE_BOOL
 378         bool "Default bootloader kernel arguments"
 379
 380 config CMDLINE
 381         string "Initial kernel command string"
 382         depends on CMDLINE_BOOL
 383         default "console=ttyBF0,57600"
 384         help
 385           If you don't have a boot loader capable of passing a command line string
 386           to the kernel, you may specify one here. As a minimum, you should specify
 387           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 388
 389 config BOOT_LOAD
 390         hex "Kernel load address for booting"
 391         default "0x1000"
 392         range 0x1000 0x20000000
 393         help
 394           This option allows you to set the load address of the kernel.
 395           This can be useful if you are on a board which has a small amount
 396           of memory or you wish to reserve some memory at the beginning of
 397           the address space.
 398
 399           Note that you need to keep this value above 4k (0x1000) as this
 400           memory region is used to capture NULL pointer references as well
 401           as some core kernel functions.
 402
 403 config PHY_RAM_BASE_ADDRESS
 404         hex "Physical RAM Base"
 405         default 0x0
 406         help
 407           set BF609 FPGA physical SRAM base address
 408
 409 config ROM_BASE
 410         hex "Kernel ROM Base"
 411         depends on ROMKERNEL
 412         default "0x20040040"
 413         range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
 414         range 0x20000000 0x30000000 if (BF54x || BF561)
 415         range 0xB0000000 0xC0000000 if (BF60x)
 416         help
 417           Make sure your ROM base does not include any file-header
 418           information that is prepended to the kernel.
 419
 420           For example, the bootable U-Boot format (created with
 421           mkimage) has a 64 byte header (0x40).  So while the image
 422           you write to flash might start at say 0x20080000, you have
 423           to add 0x40 to get the kernel's ROM base as it will come
 424           after the header.
 425
 426 comment "Clock/PLL Setup"
 427
 428 config CLKIN_HZ
 429         int "Frequency of the crystal on the board in Hz"
 430         default "10000000" if BFIN532_IP0X
 431         default "11059200" if BFIN533_STAMP
 432         default "24576000" if PNAV10
 433         default "25000000" # most people use this
 434         default "27000000" if BFIN533_EZKIT
 435         default "30000000" if BFIN561_EZKIT
 436         default "24000000" if BFIN527_AD7160EVAL
 437         help
 438           The frequency of CLKIN crystal oscillator on the board in Hz.
 439           Warning: This value should match the crystal on the board. Otherwise,
 440           peripherals won't work properly.
 441
 442 config BFIN_KERNEL_CLOCK
 443         bool "Re-program Clocks while Kernel boots?"
 444         default n
 445         help
 446           This option decides if kernel clocks are re-programed from the
 447           bootloader settings. If the clocks are not set, the SDRAM settings
 448           are also not changed, and the Bootloader does 100% of the hardware
 449           configuration.
 450
 451 config PLL_BYPASS
 452         bool "Bypass PLL"
 453         depends on BFIN_KERNEL_CLOCK && (!BF60x)
 454         default n
 455
 456 config CLKIN_HALF
 457         bool "Half Clock In"
 458         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 459         default n
 460         help
 461           If this is set the clock will be divided by 2, before it goes to the PLL.
 462
 463 config VCO_MULT
 464         int "VCO Multiplier"
 465         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 466         range 1 64
 467         default "22" if BFIN533_EZKIT
 468         default "45" if BFIN533_STAMP
 469         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 470         default "22" if BFIN533_BLUETECHNIX_CM
 471         default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 472         default "20" if (BFIN561_EZKIT || BF609)
 473         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 474         default "25" if BFIN527_AD7160EVAL
 475         help
 476           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 477           PLL Frequency = (Crystal Frequency) * (this setting)
 478
 479 choice
 480         prompt "Core Clock Divider"
 481         depends on BFIN_KERNEL_CLOCK
 482         default CCLK_DIV_1
 483         help
 484           This sets the frequency of the core. It can be 1, 2, 4 or 8
 485           Core Frequency = (PLL frequency) / (this setting)
 486
 487 config CCLK_DIV_1
 488         bool "1"
 489
 490 config CCLK_DIV_2
 491         bool "2"
 492
 493 config CCLK_DIV_4
 494         bool "4"
 495
 496 config CCLK_DIV_8
 497         bool "8"
 498 endchoice
 499
 500 config SCLK_DIV
 501         int "System Clock Divider"
 502         depends on BFIN_KERNEL_CLOCK
 503         range 1 15
 504         default 4
 505         help
 506           This sets the frequency of the system clock (including SDRAM or DDR) on
 507           !BF60x else it set the clock for system buses and provides the
 508           source from which SCLK0 and SCLK1 are derived.
 509           This can be between 1 and 15
 510           System Clock = (PLL frequency) / (this setting)
 511
 512 config SCLK0_DIV
 513         int "System Clock0 Divider"
 514         depends on BFIN_KERNEL_CLOCK && BF60x
 515         range 1 15
 516         default 1
 517         help
 518           This sets the frequency of the system clock0 for PVP and all other
 519           peripherals not clocked by SCLK1.
 520           This can be between 1 and 15
 521           System Clock0 = (System Clock) / (this setting)
 522
 523 config SCLK1_DIV
 524         int "System Clock1 Divider"
 525         depends on BFIN_KERNEL_CLOCK && BF60x
 526         range 1 15
 527         default 1
 528         help
 529           This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
 530           This can be between 1 and 15
 531           System Clock1 = (System Clock) / (this setting)
 532
 533 config DCLK_DIV
 534         int "DDR Clock Divider"
 535         depends on BFIN_KERNEL_CLOCK && BF60x
 536         range 1 15
 537         default 2
 538         help
 539           This sets the frequency of the DDR memory.
 540           This can be between 1 and 15
 541           DDR Clock = (PLL frequency) / (this setting)
 542
 543 choice
 544         prompt "DDR SDRAM Chip Type"
 545         depends on BFIN_KERNEL_CLOCK
 546         depends on BF54x
 547         default MEM_MT46V32M16_5B
 548
 549 config MEM_MT46V32M16_6T
 550         bool "MT46V32M16_6T"
 551
 552 config MEM_MT46V32M16_5B
 553         bool "MT46V32M16_5B"
 554 endchoice
 555
 556 choice
 557         prompt "DDR/SDRAM Timing"
 558         depends on BFIN_KERNEL_CLOCK && !BF60x
 559         default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 560         help
 561           This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 562           The calculated SDRAM timing parameters may not be 100%
 563           accurate - This option is therefore marked experimental.
 564
 565 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 566         bool "Calculate Timings"
 567
 568 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 569         bool "Provide accurate Timings based on target SCLK"
 570         help
 571           Please consult the Blackfin Hardware Reference Manuals as well
 572           as the memory device datasheet.
 573           http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 574 endchoice
 575
 576 menu "Memory Init Control"
 577         depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 578
 579 config MEM_DDRCTL0
 580         depends on BF54x
 581         hex "DDRCTL0"
 582         default 0x0
 583
 584 config MEM_DDRCTL1
 585         depends on BF54x
 586         hex "DDRCTL1"
 587         default 0x0
 588
 589 config MEM_DDRCTL2
 590         depends on BF54x
 591         hex "DDRCTL2"
 592         default 0x0
 593
 594 config MEM_EBIU_DDRQUE
 595         depends on BF54x
 596         hex "DDRQUE"
 597         default 0x0
 598
 599 config MEM_SDRRC
 600         depends on !BF54x
 601         hex "SDRRC"
 602         default 0x0
 603
 604 config MEM_SDGCTL
 605         depends on !BF54x
 606         hex "SDGCTL"
 607         default 0x0
 608 endmenu
 609
 610 #
 611 # Max & Min Speeds for various Chips
 612 #
 613 config MAX_VCO_HZ
 614         int
 615         default 400000000 if BF512
 616         default 400000000 if BF514
 617         default 400000000 if BF516
 618         default 400000000 if BF518
 619         default 400000000 if BF522
 620         default 600000000 if BF523
 621         default 400000000 if BF524
 622         default 600000000 if BF525
 623         default 400000000 if BF526
 624         default 600000000 if BF527
 625         default 400000000 if BF531
 626         default 400000000 if BF532
 627         default 750000000 if BF533
 628         default 500000000 if BF534
 629         default 400000000 if BF536
 630         default 600000000 if BF537
 631         default 533333333 if BF538
 632         default 533333333 if BF539
 633         default 600000000 if BF542
 634         default 533333333 if BF544
 635         default 600000000 if BF547
 636         default 600000000 if BF548
 637         default 533333333 if BF549
 638         default 600000000 if BF561
 639         default 800000000 if BF609
 640
 641 config MIN_VCO_HZ
 642         int
 643         default 50000000
 644
 645 config MAX_SCLK_HZ
 646         int
 647         default 200000000 if BF609
 648         default 133333333
 649
 650 config MIN_SCLK_HZ
 651         int
 652         default 27000000
 653
 654 comment "Kernel Timer/Scheduler"
 655
 656 source kernel/Kconfig.hz
 657
 658 config SET_GENERIC_CLOCKEVENTS
 659         bool "Generic clock events"
 660         default y
 661         select GENERIC_CLOCKEVENTS
 662
 663 menu "Clock event device"
 664         depends on GENERIC_CLOCKEVENTS
 665 config TICKSOURCE_GPTMR0
 666         bool "GPTimer0"
 667         depends on !SMP
 668         select BFIN_GPTIMERS
 669
 670 config TICKSOURCE_CORETMR
 671         bool "Core timer"
 672         default y
 673 endmenu
 674
 675 menu "Clock source"
 676         depends on GENERIC_CLOCKEVENTS
 677 config CYCLES_CLOCKSOURCE
 678         bool "CYCLES"
 679         default y
 680         depends on !BFIN_SCRATCH_REG_CYCLES
 681         depends on !SMP
 682         help
 683           If you say Y here, you will enable support for using the 'cycles'
 684           registers as a clock source.  Doing so means you will be unable to
 685           safely write to the 'cycles' register during runtime.  You will
 686           still be able to read it (such as for performance monitoring), but
 687           writing the registers will most likely crash the kernel.
 688
 689 config GPTMR0_CLOCKSOURCE
 690         bool "GPTimer0"
 691         select BFIN_GPTIMERS
 692         depends on !TICKSOURCE_GPTMR0
 693 endmenu
 694
 695 comment "Misc"
 696
 697 choice
 698         prompt "Blackfin Exception Scratch Register"
 699         default BFIN_SCRATCH_REG_RETN
 700         help
 701           Select the resource to reserve for the Exception handler:
 702             - RETN: Non-Maskable Interrupt (NMI)
 703             - RETE: Exception Return (JTAG/ICE)
 704             - CYCLES: Performance counter
 705
 706           If you are unsure, please select "RETN".
 707
 708 config BFIN_SCRATCH_REG_RETN
 709         bool "RETN"
 710         help
 711           Use the RETN register in the Blackfin exception handler
 712           as a stack scratch register.  This means you cannot
 713           safely use NMI on the Blackfin while running Linux, but
 714           you can debug the system with a JTAG ICE and use the
 715           CYCLES performance registers.
 716
 717           If you are unsure, please select "RETN".
 718
 719 config BFIN_SCRATCH_REG_RETE
 720         bool "RETE"
 721         help
 722           Use the RETE register in the Blackfin exception handler
 723           as a stack scratch register.  This means you cannot
 724           safely use a JTAG ICE while debugging a Blackfin board,
 725           but you can safely use the CYCLES performance registers
 726           and the NMI.
 727
 728           If you are unsure, please select "RETN".
 729
 730 config BFIN_SCRATCH_REG_CYCLES
 731         bool "CYCLES"
 732         help
 733           Use the CYCLES register in the Blackfin exception handler
 734           as a stack scratch register.  This means you cannot
 735           safely use the CYCLES performance registers on a Blackfin
 736           board at anytime, but you can debug the system with a JTAG
 737           ICE and use the NMI.
 738
 739           If you are unsure, please select "RETN".
 740
 741 endchoice
 742
 743 endmenu
 744
 745
 746 menu "Blackfin Kernel Optimizations"
 747
 748 comment "Memory Optimizations"
 749
 750 config I_ENTRY_L1
 751         bool "Locate interrupt entry code in L1 Memory"
 752         default y
 753         depends on !SMP
 754         help
 755           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 756           into L1 instruction memory. (less latency)
 757
 758 config EXCPT_IRQ_SYSC_L1
 759         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 760         default y
 761         depends on !SMP
 762         help
 763           If enabled, the entire ASM lowlevel exception and interrupt entry code
 764           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 765           (less latency)
 766
 767 config DO_IRQ_L1
 768         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 769         default y
 770         depends on !SMP
 771         help
 772           If enabled, the frequently called do_irq dispatcher function is linked
 773           into L1 instruction memory. (less latency)
 774
 775 config CORE_TIMER_IRQ_L1
 776         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 777         default y
 778         depends on !SMP
 779         help
 780           If enabled, the frequently called timer_interrupt() function is linked
 781           into L1 instruction memory. (less latency)
 782
 783 config IDLE_L1
 784         bool "Locate frequently idle function in L1 Memory"
 785         default y
 786         depends on !SMP
 787         help
 788           If enabled, the frequently called idle function is linked
 789           into L1 instruction memory. (less latency)
 790
 791 config SCHEDULE_L1
 792         bool "Locate kernel schedule function in L1 Memory"
 793         default y
 794         depends on !SMP
 795         help
 796           If enabled, the frequently called kernel schedule is linked
 797           into L1 instruction memory. (less latency)
 798
 799 config ARITHMETIC_OPS_L1
 800         bool "Locate kernel owned arithmetic functions in L1 Memory"
 801         default y
 802         depends on !SMP
 803         help
 804           If enabled, arithmetic functions are linked
 805           into L1 instruction memory. (less latency)
 806
 807 config ACCESS_OK_L1
 808         bool "Locate access_ok function in L1 Memory"
 809         default y
 810         depends on !SMP
 811         help
 812           If enabled, the access_ok function is linked
 813           into L1 instruction memory. (less latency)
 814
 815 config MEMSET_L1
 816         bool "Locate memset function in L1 Memory"
 817         default y
 818         depends on !SMP
 819         help
 820           If enabled, the memset function is linked
 821           into L1 instruction memory. (less latency)
 822
 823 config MEMCPY_L1
 824         bool "Locate memcpy function in L1 Memory"
 825         default y
 826         depends on !SMP
 827         help
 828           If enabled, the memcpy function is linked
 829           into L1 instruction memory. (less latency)
 830
 831 config STRCMP_L1
 832         bool "locate strcmp function in L1 Memory"
 833         default y
 834         depends on !SMP
 835         help
 836           If enabled, the strcmp function is linked
 837           into L1 instruction memory (less latency).
 838
 839 config STRNCMP_L1
 840         bool "locate strncmp function in L1 Memory"
 841         default y
 842         depends on !SMP
 843         help
 844           If enabled, the strncmp function is linked
 845           into L1 instruction memory (less latency).
 846
 847 config STRCPY_L1
 848         bool "locate strcpy function in L1 Memory"
 849         default y
 850         depends on !SMP
 851         help
 852           If enabled, the strcpy function is linked
 853           into L1 instruction memory (less latency).
 854
 855 config STRNCPY_L1
 856         bool "locate strncpy function in L1 Memory"
 857         default y
 858         depends on !SMP
 859         help
 860           If enabled, the strncpy function is linked
 861           into L1 instruction memory (less latency).
 862
 863 config SYS_BFIN_SPINLOCK_L1
 864         bool "Locate sys_bfin_spinlock function in L1 Memory"
 865         default y
 866         depends on !SMP
 867         help
 868           If enabled, sys_bfin_spinlock function is linked
 869           into L1 instruction memory. (less latency)
 870
 871 config CACHELINE_ALIGNED_L1
 872         bool "Locate cacheline_aligned data to L1 Data Memory"
 873         default y if !BF54x
 874         default n if BF54x
 875         depends on !SMP && !BF531 && !CRC32
 876         help
 877           If enabled, cacheline_aligned data is linked
 878           into L1 data memory. (less latency)
 879
 880 config SYSCALL_TAB_L1
 881         bool "Locate Syscall Table L1 Data Memory"
 882         default n
 883         depends on !SMP && !BF531
 884         help
 885           If enabled, the Syscall LUT is linked
 886           into L1 data memory. (less latency)
 887
 888 config CPLB_SWITCH_TAB_L1
 889         bool "Locate CPLB Switch Tables L1 Data Memory"
 890         default n
 891         depends on !SMP && !BF531
 892         help
 893           If enabled, the CPLB Switch Tables are linked
 894           into L1 data memory. (less latency)
 895
 896 config ICACHE_FLUSH_L1
 897         bool "Locate icache flush funcs in L1 Inst Memory"
 898         default y
 899         help
 900           If enabled, the Blackfin icache flushing functions are linked
 901           into L1 instruction memory.
 902
 903           Note that this might be required to address anomalies, but
 904           these functions are pretty small, so it shouldn't be too bad.
 905           If you are using a processor affected by an anomaly, the build
 906           system will double check for you and prevent it.
 907
 908 config DCACHE_FLUSH_L1
 909         bool "Locate dcache flush funcs in L1 Inst Memory"
 910         default y
 911         depends on !SMP
 912         help
 913           If enabled, the Blackfin dcache flushing functions are linked
 914           into L1 instruction memory.
 915
 916 config APP_STACK_L1
 917         bool "Support locating application stack in L1 Scratch Memory"
 918         default y
 919         depends on !SMP
 920         help
 921           If enabled the application stack can be located in L1
 922           scratch memory (less latency).
 923
 924           Currently only works with FLAT binaries.
 925
 926 config EXCEPTION_L1_SCRATCH
 927         bool "Locate exception stack in L1 Scratch Memory"
 928         default n
 929         depends on !SMP && !APP_STACK_L1
 930         help
 931           Whenever an exception occurs, use the L1 Scratch memory for
 932           stack storage.  You cannot place the stacks of FLAT binaries
 933           in L1 when using this option.
 934
 935           If you don't use L1 Scratch, then you should say Y here.
 936
 937 comment "Speed Optimizations"
 938 config BFIN_INS_LOWOVERHEAD
 939         bool "ins[bwl] low overhead, higher interrupt latency"
 940         default y
 941         depends on !SMP
 942         help
 943           Reads on the Blackfin are speculative. In Blackfin terms, this means
 944           they can be interrupted at any time (even after they have been issued
 945           on to the external bus), and re-issued after the interrupt occurs.
 946           For memory - this is not a big deal, since memory does not change if
 947           it sees a read.
 948
 949           If a FIFO is sitting on the end of the read, it will see two reads,
 950           when the core only sees one since the FIFO receives both the read
 951           which is cancelled (and not delivered to the core) and the one which
 952           is re-issued (which is delivered to the core).
 953
 954           To solve this, interrupts are turned off before reads occur to
 955           I/O space. This option controls which the overhead/latency of
 956           controlling interrupts during this time
 957            "n" turns interrupts off every read
 958                 (higher overhead, but lower interrupt latency)
 959            "y" turns interrupts off every loop
 960                 (low overhead, but longer interrupt latency)
 961
 962           default behavior is to leave this set to on (type "Y"). If you are experiencing
 963           interrupt latency issues, it is safe and OK to turn this off.
 964
 965 endmenu
 966
 967 choice
 968         prompt "Kernel executes from"
 969         help
 970           Choose the memory type that the kernel will be running in.
 971
 972 config RAMKERNEL
 973         bool "RAM"
 974         help
 975           The kernel will be resident in RAM when running.
 976
 977 config ROMKERNEL
 978         bool "ROM"
 979         help
 980           The kernel will be resident in FLASH/ROM when running.
 981
 982 endchoice
 983
 984 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
 985 config XIP_KERNEL
 986         bool
 987         default y
 988         depends on ROMKERNEL
 989
 990 source "mm/Kconfig"
 991
 992 config BFIN_GPTIMERS
 993         tristate "Enable Blackfin General Purpose Timers API"
 994         default n
 995         help
 996           Enable support for the General Purpose Timers API.  If you
 997           are unsure, say N.
 998
 999           To compile this driver as a module, choose M here: the module
1000           will be called gptimers.
1001
1002 choice
1003         prompt "Uncached DMA region"
1004         default DMA_UNCACHED_1M
1005 config DMA_UNCACHED_32M
1006         bool "Enable 32M DMA region"
1007 config DMA_UNCACHED_16M
1008         bool "Enable 16M DMA region"
1009 config DMA_UNCACHED_8M
1010         bool "Enable 8M DMA region"
1011 config DMA_UNCACHED_4M
1012         bool "Enable 4M DMA region"
1013 config DMA_UNCACHED_2M
1014         bool "Enable 2M DMA region"
1015 config DMA_UNCACHED_1M
1016         bool "Enable 1M DMA region"
1017 config DMA_UNCACHED_512K
1018         bool "Enable 512K DMA region"
1019 config DMA_UNCACHED_256K
1020         bool "Enable 256K DMA region"
1021 config DMA_UNCACHED_128K
1022         bool "Enable 128K DMA region"
1023 config DMA_UNCACHED_NONE
1024         bool "Disable DMA region"
1025 endchoice
1026
1027
1028 comment "Cache Support"
1029
1030 config BFIN_ICACHE
1031         bool "Enable ICACHE"
1032         default y
1033 config BFIN_EXTMEM_ICACHEABLE
1034         bool "Enable ICACHE for external memory"
1035         depends on BFIN_ICACHE
1036         default y
1037 config BFIN_L2_ICACHEABLE
1038         bool "Enable ICACHE for L2 SRAM"
1039         depends on BFIN_ICACHE
1040         depends on (BF54x || BF561 || BF60x) && !SMP
1041         default n
1042
1043 config BFIN_DCACHE
1044         bool "Enable DCACHE"
1045         default y
1046 config BFIN_DCACHE_BANKA
1047         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1048         depends on BFIN_DCACHE && !BF531
1049         default n
1050 config BFIN_EXTMEM_DCACHEABLE
1051         bool "Enable DCACHE for external memory"
1052         depends on BFIN_DCACHE
1053         default y
1054 choice
1055         prompt "External memory DCACHE policy"
1056         depends on BFIN_EXTMEM_DCACHEABLE
1057         default BFIN_EXTMEM_WRITEBACK if !SMP
1058         default BFIN_EXTMEM_WRITETHROUGH if SMP
1059 config BFIN_EXTMEM_WRITEBACK
1060         bool "Write back"
1061         depends on !SMP
1062         help
1063           Write Back Policy:
1064             Cached data will be written back to SDRAM only when needed.
1065             This can give a nice increase in performance, but beware of
1066             broken drivers that do not properly invalidate/flush their
1067             cache.
1068
1069           Write Through Policy:
1070             Cached data will always be written back to SDRAM when the
1071             cache is updated.  This is a completely safe setting, but
1072             performance is worse than Write Back.
1073
1074           If you are unsure of the options and you want to be safe,
1075           then go with Write Through.
1076
1077 config BFIN_EXTMEM_WRITETHROUGH
1078         bool "Write through"
1079         help
1080           Write Back Policy:
1081             Cached data will be written back to SDRAM only when needed.
1082             This can give a nice increase in performance, but beware of
1083             broken drivers that do not properly invalidate/flush their
1084             cache.
1085
1086           Write Through Policy:
1087             Cached data will always be written back to SDRAM when the
1088             cache is updated.  This is a completely safe setting, but
1089             performance is worse than Write Back.
1090
1091           If you are unsure of the options and you want to be safe,
1092           then go with Write Through.
1093
1094 endchoice
1095
1096 config BFIN_L2_DCACHEABLE
1097         bool "Enable DCACHE for L2 SRAM"
1098         depends on BFIN_DCACHE
1099         depends on (BF54x || BF561 || BF60x) && !SMP
1100         default n
1101 choice
1102         prompt "L2 SRAM DCACHE policy"
1103         depends on BFIN_L2_DCACHEABLE
1104         default BFIN_L2_WRITEBACK
1105 config BFIN_L2_WRITEBACK
1106         bool "Write back"
1107
1108 config BFIN_L2_WRITETHROUGH
1109         bool "Write through"
1110 endchoice
1111
1112
1113 comment "Memory Protection Unit"
1114 config MPU
1115         bool "Enable the memory protection unit"
1116         default n
1117         help
1118           Use the processor's MPU to protect applications from accessing
1119           memory they do not own.  This comes at a performance penalty
1120           and is recommended only for debugging.
1121
1122 comment "Asynchronous Memory Configuration"
1123
1124 menu "EBIU_AMGCTL Global Control"
1125         depends on !BF60x
1126 config C_AMCKEN
1127         bool "Enable CLKOUT"
1128         default y
1129
1130 config C_CDPRIO
1131         bool "DMA has priority over core for ext. accesses"
1132         default n
1133
1134 config C_B0PEN
1135         depends on BF561
1136         bool "Bank 0 16 bit packing enable"
1137         default y
1138
1139 config C_B1PEN
1140         depends on BF561
1141         bool "Bank 1 16 bit packing enable"
1142         default y
1143
1144 config C_B2PEN
1145         depends on BF561
1146         bool "Bank 2 16 bit packing enable"
1147         default y
1148
1149 config C_B3PEN
1150         depends on BF561
1151         bool "Bank 3 16 bit packing enable"
1152         default n
1153
1154 choice
1155         prompt "Enable Asynchronous Memory Banks"
1156         default C_AMBEN_ALL
1157
1158 config C_AMBEN
1159         bool "Disable All Banks"
1160
1161 config C_AMBEN_B0
1162         bool "Enable Bank 0"
1163
1164 config C_AMBEN_B0_B1
1165         bool "Enable Bank 0 & 1"
1166
1167 config C_AMBEN_B0_B1_B2
1168         bool "Enable Bank 0 & 1 & 2"
1169
1170 config C_AMBEN_ALL
1171         bool "Enable All Banks"
1172 endchoice
1173 endmenu
1174
1175 menu "EBIU_AMBCTL Control"
1176         depends on !BF60x
1177 config BANK_0
1178         hex "Bank 0 (AMBCTL0.L)"
1179         default 0x7BB0
1180         help
1181           These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1182           used to control the Asynchronous Memory Bank 0 settings.
1183
1184 config BANK_1
1185         hex "Bank 1 (AMBCTL0.H)"
1186         default 0x7BB0
1187         default 0x5558 if BF54x
1188         help
1189           These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1190           used to control the Asynchronous Memory Bank 1 settings.
1191
1192 config BANK_2
1193         hex "Bank 2 (AMBCTL1.L)"
1194         default 0x7BB0
1195         help
1196           These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1197           used to control the Asynchronous Memory Bank 2 settings.
1198
1199 config BANK_3
1200         hex "Bank 3 (AMBCTL1.H)"
1201         default 0x99B3
1202         help
1203           These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1204           used to control the Asynchronous Memory Bank 3 settings.
1205
1206 endmenu
1207
1208 config EBIU_MBSCTLVAL
1209         hex "EBIU Bank Select Control Register"
1210         depends on BF54x
1211         default 0
1212
1213 config EBIU_MODEVAL
1214         hex "Flash Memory Mode Control Register"
1215         depends on BF54x
1216         default 1
1217
1218 config EBIU_FCTLVAL
1219         hex "Flash Memory Bank Control Register"
1220         depends on BF54x
1221         default 6
1222 endmenu
1223
1224 #############################################################################
1225 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1226
1227 config PCI
1228         bool "PCI support"
1229         depends on BROKEN
1230         help
1231           Support for PCI bus.
1232
1233 source "drivers/pci/Kconfig"
1234
1235 source "drivers/pcmcia/Kconfig"
1236
1237 endmenu
1238
1239 menu "Executable file formats"
1240
1241 source "fs/Kconfig.binfmt"
1242
1243 endmenu
1244
1245 menu "Power management options"
1246
1247 source "kernel/power/Kconfig"
1248
1249 config ARCH_SUSPEND_POSSIBLE
1250         def_bool y
1251
1252 choice
1253         prompt "Standby Power Saving Mode"
1254         depends on PM && !BF60x
1255         default PM_BFIN_SLEEP_DEEPER
1256 config  PM_BFIN_SLEEP_DEEPER
1257         bool "Sleep Deeper"
1258         help
1259           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1260           power dissipation by disabling the clock to the processor core (CCLK).
1261           Furthermore, Standby sets the internal power supply voltage (VDDINT)
1262           to 0.85 V to provide the greatest power savings, while preserving the
1263           processor state.
1264           The PLL and system clock (SCLK) continue to operate at a very low
1265           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1266           the SDRAM is put into Self Refresh Mode. Typically an external event
1267           such as GPIO interrupt or RTC activity wakes up the processor.
1268           Various Peripherals such as UART, SPORT, PPI may not function as
1269           normal during Sleep Deeper, due to the reduced SCLK frequency.
1270           When in the sleep mode, system DMA access to L1 memory is not supported.
1271
1272           If unsure, select "Sleep Deeper".
1273
1274 config  PM_BFIN_SLEEP
1275         bool "Sleep"
1276         help
1277           Sleep Mode (High Power Savings) - The sleep mode reduces power
1278           dissipation by disabling the clock to the processor core (CCLK).
1279           The PLL and system clock (SCLK), however, continue to operate in
1280           this mode. Typically an external event or RTC activity will wake
1281           up the processor. When in the sleep mode, system DMA access to L1
1282           memory is not supported.
1283
1284           If unsure, select "Sleep Deeper".
1285 endchoice
1286
1287 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1288         depends on PM
1289
1290 config PM_BFIN_WAKE_PH6
1291         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1292         depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1293         default n
1294         help
1295           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1296
1297 config PM_BFIN_WAKE_GP
1298         bool "Allow Wake-Up from GPIOs"
1299         depends on PM && BF54x
1300         default n
1301         help
1302           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1303           (all processors, except ADSP-BF549). This option sets
1304           the general-purpose wake-up enable (GPWE) control bit to enable
1305           wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1306           On ADSP-BF549 this option enables the same functionality on the
1307           /MRXON pin also PH7.
1308
1309 config PM_BFIN_WAKE_PA15
1310         bool "Allow Wake-Up from PA15"
1311         depends on PM && BF60x
1312         default n
1313         help
1314           Enable PA15 Wake-Up
1315
1316 config PM_BFIN_WAKE_PA15_POL
1317         int "Wake-up priority"
1318         depends on PM_BFIN_WAKE_PA15
1319         default 0
1320         help
1321           Wake-Up priority 0(low) 1(high)
1322
1323 config PM_BFIN_WAKE_PB15
1324         bool "Allow Wake-Up from PB15"
1325         depends on PM && BF60x
1326         default n
1327         help
1328           Enable PB15 Wake-Up
1329
1330 config PM_BFIN_WAKE_PB15_POL
1331         int "Wake-up priority"
1332         depends on PM_BFIN_WAKE_PB15
1333         default 0
1334         help
1335           Wake-Up priority 0(low) 1(high)
1336
1337 config PM_BFIN_WAKE_PC15
1338         bool "Allow Wake-Up from PC15"
1339         depends on PM && BF60x
1340         default n
1341         help
1342           Enable PC15 Wake-Up
1343
1344 config PM_BFIN_WAKE_PC15_POL
1345         int "Wake-up priority"
1346         depends on PM_BFIN_WAKE_PC15
1347         default 0
1348         help
1349           Wake-Up priority 0(low) 1(high)
1350
1351 config PM_BFIN_WAKE_PD06
1352         bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
1353         depends on PM && BF60x
1354         default n
1355         help
1356           Enable PD06(ETH0_PHYINT) Wake-up
1357
1358 config PM_BFIN_WAKE_PD06_POL
1359         int "Wake-up priority"
1360         depends on PM_BFIN_WAKE_PD06
1361         default 0
1362         help
1363           Wake-Up priority 0(low) 1(high)
1364
1365 config PM_BFIN_WAKE_PE12
1366         bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
1367         depends on PM && BF60x
1368         default n
1369         help
1370           Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
1371
1372 config PM_BFIN_WAKE_PE12_POL
1373         int "Wake-up priority"
1374         depends on PM_BFIN_WAKE_PE12
1375         default 0
1376         help
1377           Wake-Up priority 0(low) 1(high)
1378
1379 config PM_BFIN_WAKE_PG04
1380         bool "Allow Wake-Up from PG04(CAN0_RX)"
1381         depends on PM && BF60x
1382         default n
1383         help
1384           Enable PG04(CAN0_RX) Wake-up
1385
1386 config PM_BFIN_WAKE_PG04_POL
1387         int "Wake-up priority"
1388         depends on PM_BFIN_WAKE_PG04
1389         default 0
1390         help
1391           Wake-Up priority 0(low) 1(high)
1392
1393 config PM_BFIN_WAKE_PG13
1394         bool "Allow Wake-Up from PG13"
1395         depends on PM && BF60x
1396         default n
1397         help
1398           Enable PG13 Wake-Up
1399
1400 config PM_BFIN_WAKE_PG13_POL
1401         int "Wake-up priority"
1402         depends on PM_BFIN_WAKE_PG13
1403         default 0
1404         help
1405           Wake-Up priority 0(low) 1(high)
1406
1407 config PM_BFIN_WAKE_USB
1408         bool "Allow Wake-Up from (USB)"
1409         depends on PM && BF60x
1410         default n
1411         help
1412           Enable (USB) Wake-up
1413
1414 config PM_BFIN_WAKE_USB_POL
1415         int "Wake-up priority"
1416         depends on PM_BFIN_WAKE_USB
1417         default 0
1418         help
1419           Wake-Up priority 0(low) 1(high)
1420
1421 endmenu
1422
1423 menu "CPU Frequency scaling"
1424
1425 source "drivers/cpufreq/Kconfig"
1426
1427 config BFIN_CPU_FREQ
1428         bool
1429         depends on CPU_FREQ
1430         default y
1431
1432 config CPU_VOLTAGE
1433         bool "CPU Voltage scaling"
1434         depends on CPU_FREQ
1435         default n
1436         help
1437           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1438           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1439           manuals. There is a theoretical risk that during VDDINT transitions
1440           the PLL may unlock.
1441
1442 endmenu
1443
1444 source "net/Kconfig"
1445
1446 source "drivers/Kconfig"
1447
1448 source "drivers/firmware/Kconfig"
1449
1450 source "fs/Kconfig"
1451
1452 source "arch/blackfin/Kconfig.debug"
1453
1454 source "security/Kconfig"
1455
1456 source "crypto/Kconfig"
1457
1458 source "lib/Kconfig"