2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
18 config RWSEM_GENERIC_SPINLOCK
21 config RWSEM_XCHGADD_ALGORITHM
27 select HAVE_ARCH_TRACEHOOK
28 select HAVE_DYNAMIC_FTRACE
29 select HAVE_FTRACE_MCOUNT_RECORD
30 select HAVE_FUNCTION_GRAPH_TRACER
31 select HAVE_FUNCTION_TRACER
32 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
34 select HAVE_KERNEL_GZIP if RAMKERNEL
35 select HAVE_KERNEL_BZIP2 if RAMKERNEL
36 select HAVE_KERNEL_LZMA if RAMKERNEL
37 select HAVE_KERNEL_LZO if RAMKERNEL
39 select ARCH_WANT_OPTIONAL_GPIOLIB
51 config GENERIC_FIND_NEXT_BIT
54 config GENERIC_HARDIRQS
57 config GENERIC_IRQ_PROBE
60 config GENERIC_HARDIRQS_NO__DO_IRQ
66 config FORCE_MAX_ZONEORDER
70 config GENERIC_CALIBRATE_DELAY
73 config LOCKDEP_SUPPORT
76 config STACKTRACE_SUPPORT
79 config TRACE_IRQFLAGS_SUPPORT
84 source "kernel/Kconfig.preempt"
86 source "kernel/Kconfig.freezer"
88 menu "Blackfin Processor Options"
90 comment "Processor and Board Settings"
99 BF512 Processor Support.
104 BF514 Processor Support.
109 BF516 Processor Support.
114 BF518 Processor Support.
119 BF522 Processor Support.
124 BF523 Processor Support.
129 BF524 Processor Support.
134 BF525 Processor Support.
139 BF526 Processor Support.
144 BF527 Processor Support.
149 BF531 Processor Support.
154 BF532 Processor Support.
159 BF533 Processor Support.
164 BF534 Processor Support.
169 BF536 Processor Support.
174 BF537 Processor Support.
179 BF538 Processor Support.
184 BF539 Processor Support.
189 BF542 Processor Support.
194 BF542 Processor Support.
199 BF544 Processor Support.
204 BF544 Processor Support.
209 BF547 Processor Support.
214 BF547 Processor Support.
219 BF548 Processor Support.
224 BF548 Processor Support.
229 BF549 Processor Support.
234 BF549 Processor Support.
239 BF561 Processor Support.
245 select TICKSOURCE_CORETMR
246 bool "Symmetric multi-processing support"
248 This enables support for systems with more than one CPU,
249 like the dual core BF561. If you have a system with only one
250 CPU, say N. If you have a system with more than one CPU, say Y.
252 If you don't know what to do here, say N.
260 bool "Support for hot-pluggable CPUs"
261 depends on SMP && HOTPLUG
269 config HAVE_LEGACY_PER_CPU_AREA
275 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
276 default 2 if (BF537 || BF536 || BF534)
277 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
278 default 4 if (BF538 || BF539)
282 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
283 default 3 if (BF537 || BF536 || BF534 || BF54xM)
284 default 5 if (BF561 || BF538 || BF539)
285 default 6 if (BF533 || BF532 || BF531)
289 default BF_REV_0_0 if (BF51x || BF52x)
290 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
291 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
295 depends on (BF51x || BF52x || (BF54x && !BF54xM))
299 depends on (BF51x || BF52x || (BF54x && !BF54xM))
303 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
307 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
311 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
315 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
319 depends on (BF533 || BF532 || BF531)
331 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
334 config MEM_MT48LC64M4A2FB_7E
336 depends on (BFIN533_STAMP)
339 config MEM_MT48LC16M16A2TG_75
341 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
342 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
343 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
344 || BFIN527_BLUETECHNIX_CM)
347 config MEM_MT48LC32M8A2_75
349 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
352 config MEM_MT48LC8M32B2B5_7
354 depends on (BFIN561_BLUETECHNIX_CM)
357 config MEM_MT48LC32M16A2TG_75
359 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP)
362 config MEM_MT48H32M16LFCJ_75
364 depends on (BFIN526_EZBRD)
367 source "arch/blackfin/mach-bf518/Kconfig"
368 source "arch/blackfin/mach-bf527/Kconfig"
369 source "arch/blackfin/mach-bf533/Kconfig"
370 source "arch/blackfin/mach-bf561/Kconfig"
371 source "arch/blackfin/mach-bf537/Kconfig"
372 source "arch/blackfin/mach-bf538/Kconfig"
373 source "arch/blackfin/mach-bf548/Kconfig"
375 menu "Board customizations"
378 bool "Default bootloader kernel arguments"
381 string "Initial kernel command string"
382 depends on CMDLINE_BOOL
383 default "console=ttyBF0,57600"
385 If you don't have a boot loader capable of passing a command line string
386 to the kernel, you may specify one here. As a minimum, you should specify
387 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
390 hex "Kernel load address for booting"
392 range 0x1000 0x20000000
394 This option allows you to set the load address of the kernel.
395 This can be useful if you are on a board which has a small amount
396 of memory or you wish to reserve some memory at the beginning of
399 Note that you need to keep this value above 4k (0x1000) as this
400 memory region is used to capture NULL pointer references as well
401 as some core kernel functions.
404 hex "Kernel ROM Base"
407 range 0x20000000 0x20400000 if !(BF54x || BF561)
408 range 0x20000000 0x30000000 if (BF54x || BF561)
410 Make sure your ROM base does not include any file-header
411 information that is prepended to the kernel.
413 For example, the bootable U-Boot format (created with
414 mkimage) has a 64 byte header (0x40). So while the image
415 you write to flash might start at say 0x20080000, you have
416 to add 0x40 to get the kernel's ROM base as it will come
419 comment "Clock/PLL Setup"
422 int "Frequency of the crystal on the board in Hz"
423 default "10000000" if BFIN532_IP0X
424 default "11059200" if BFIN533_STAMP
425 default "24576000" if PNAV10
426 default "25000000" # most people use this
427 default "27000000" if BFIN533_EZKIT
428 default "30000000" if BFIN561_EZKIT
430 The frequency of CLKIN crystal oscillator on the board in Hz.
431 Warning: This value should match the crystal on the board. Otherwise,
432 peripherals won't work properly.
434 config BFIN_KERNEL_CLOCK
435 bool "Re-program Clocks while Kernel boots?"
438 This option decides if kernel clocks are re-programed from the
439 bootloader settings. If the clocks are not set, the SDRAM settings
440 are also not changed, and the Bootloader does 100% of the hardware
445 depends on BFIN_KERNEL_CLOCK
450 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
453 If this is set the clock will be divided by 2, before it goes to the PLL.
457 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
459 default "22" if BFIN533_EZKIT
460 default "45" if BFIN533_STAMP
461 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
462 default "22" if BFIN533_BLUETECHNIX_CM
463 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
464 default "20" if BFIN561_EZKIT
465 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
467 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
468 PLL Frequency = (Crystal Frequency) * (this setting)
471 prompt "Core Clock Divider"
472 depends on BFIN_KERNEL_CLOCK
475 This sets the frequency of the core. It can be 1, 2, 4 or 8
476 Core Frequency = (PLL frequency) / (this setting)
492 int "System Clock Divider"
493 depends on BFIN_KERNEL_CLOCK
497 This sets the frequency of the system clock (including SDRAM or DDR).
498 This can be between 1 and 15
499 System Clock = (PLL frequency) / (this setting)
502 prompt "DDR SDRAM Chip Type"
503 depends on BFIN_KERNEL_CLOCK
505 default MEM_MT46V32M16_5B
507 config MEM_MT46V32M16_6T
510 config MEM_MT46V32M16_5B
515 prompt "DDR/SDRAM Timing"
516 depends on BFIN_KERNEL_CLOCK
517 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
519 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
520 The calculated SDRAM timing parameters may not be 100%
521 accurate - This option is therefore marked experimental.
523 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
524 bool "Calculate Timings (EXPERIMENTAL)"
525 depends on EXPERIMENTAL
527 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
528 bool "Provide accurate Timings based on target SCLK"
530 Please consult the Blackfin Hardware Reference Manuals as well
531 as the memory device datasheet.
532 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
535 menu "Memory Init Control"
536 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
553 config MEM_EBIU_DDRQUE
570 # Max & Min Speeds for various Chips
574 default 400000000 if BF512
575 default 400000000 if BF514
576 default 400000000 if BF516
577 default 400000000 if BF518
578 default 400000000 if BF522
579 default 600000000 if BF523
580 default 400000000 if BF524
581 default 600000000 if BF525
582 default 400000000 if BF526
583 default 600000000 if BF527
584 default 400000000 if BF531
585 default 400000000 if BF532
586 default 750000000 if BF533
587 default 500000000 if BF534
588 default 400000000 if BF536
589 default 600000000 if BF537
590 default 533333333 if BF538
591 default 533333333 if BF539
592 default 600000000 if BF542
593 default 533333333 if BF544
594 default 600000000 if BF547
595 default 600000000 if BF548
596 default 533333333 if BF549
597 default 600000000 if BF561
611 comment "Kernel Timer/Scheduler"
613 source kernel/Kconfig.hz
615 config GENERIC_CLOCKEVENTS
616 bool "Generic clock events"
619 menu "Clock event device"
620 depends on GENERIC_CLOCKEVENTS
621 config TICKSOURCE_GPTMR0
626 config TICKSOURCE_CORETMR
632 depends on GENERIC_CLOCKEVENTS
633 config CYCLES_CLOCKSOURCE
636 depends on !BFIN_SCRATCH_REG_CYCLES
639 If you say Y here, you will enable support for using the 'cycles'
640 registers as a clock source. Doing so means you will be unable to
641 safely write to the 'cycles' register during runtime. You will
642 still be able to read it (such as for performance monitoring), but
643 writing the registers will most likely crash the kernel.
645 config GPTMR0_CLOCKSOURCE
648 depends on !TICKSOURCE_GPTMR0
651 config ARCH_USES_GETTIMEOFFSET
652 depends on !GENERIC_CLOCKEVENTS
655 source kernel/time/Kconfig
660 prompt "Blackfin Exception Scratch Register"
661 default BFIN_SCRATCH_REG_RETN
663 Select the resource to reserve for the Exception handler:
664 - RETN: Non-Maskable Interrupt (NMI)
665 - RETE: Exception Return (JTAG/ICE)
666 - CYCLES: Performance counter
668 If you are unsure, please select "RETN".
670 config BFIN_SCRATCH_REG_RETN
673 Use the RETN register in the Blackfin exception handler
674 as a stack scratch register. This means you cannot
675 safely use NMI on the Blackfin while running Linux, but
676 you can debug the system with a JTAG ICE and use the
677 CYCLES performance registers.
679 If you are unsure, please select "RETN".
681 config BFIN_SCRATCH_REG_RETE
684 Use the RETE register in the Blackfin exception handler
685 as a stack scratch register. This means you cannot
686 safely use a JTAG ICE while debugging a Blackfin board,
687 but you can safely use the CYCLES performance registers
690 If you are unsure, please select "RETN".
692 config BFIN_SCRATCH_REG_CYCLES
695 Use the CYCLES register in the Blackfin exception handler
696 as a stack scratch register. This means you cannot
697 safely use the CYCLES performance registers on a Blackfin
698 board at anytime, but you can debug the system with a JTAG
701 If you are unsure, please select "RETN".
708 menu "Blackfin Kernel Optimizations"
711 comment "Memory Optimizations"
714 bool "Locate interrupt entry code in L1 Memory"
717 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
718 into L1 instruction memory. (less latency)
720 config EXCPT_IRQ_SYSC_L1
721 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
724 If enabled, the entire ASM lowlevel exception and interrupt entry code
725 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
729 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
732 If enabled, the frequently called do_irq dispatcher function is linked
733 into L1 instruction memory. (less latency)
735 config CORE_TIMER_IRQ_L1
736 bool "Locate frequently called timer_interrupt() function in L1 Memory"
739 If enabled, the frequently called timer_interrupt() function is linked
740 into L1 instruction memory. (less latency)
743 bool "Locate frequently idle function in L1 Memory"
746 If enabled, the frequently called idle function is linked
747 into L1 instruction memory. (less latency)
750 bool "Locate kernel schedule function in L1 Memory"
753 If enabled, the frequently called kernel schedule is linked
754 into L1 instruction memory. (less latency)
756 config ARITHMETIC_OPS_L1
757 bool "Locate kernel owned arithmetic functions in L1 Memory"
760 If enabled, arithmetic functions are linked
761 into L1 instruction memory. (less latency)
764 bool "Locate access_ok function in L1 Memory"
767 If enabled, the access_ok function is linked
768 into L1 instruction memory. (less latency)
771 bool "Locate memset function in L1 Memory"
774 If enabled, the memset function is linked
775 into L1 instruction memory. (less latency)
778 bool "Locate memcpy function in L1 Memory"
781 If enabled, the memcpy function is linked
782 into L1 instruction memory. (less latency)
785 bool "locate strcmp function in L1 Memory"
788 If enabled, the strcmp function is linked
789 into L1 instruction memory (less latency).
792 bool "locate strncmp function in L1 Memory"
795 If enabled, the strncmp function is linked
796 into L1 instruction memory (less latency).
799 bool "locate strcpy function in L1 Memory"
802 If enabled, the strcpy function is linked
803 into L1 instruction memory (less latency).
806 bool "locate strncpy function in L1 Memory"
809 If enabled, the strncpy function is linked
810 into L1 instruction memory (less latency).
812 config SYS_BFIN_SPINLOCK_L1
813 bool "Locate sys_bfin_spinlock function in L1 Memory"
816 If enabled, sys_bfin_spinlock function is linked
817 into L1 instruction memory. (less latency)
819 config IP_CHECKSUM_L1
820 bool "Locate IP Checksum function in L1 Memory"
823 If enabled, the IP Checksum function is linked
824 into L1 instruction memory. (less latency)
826 config CACHELINE_ALIGNED_L1
827 bool "Locate cacheline_aligned data to L1 Data Memory"
832 If enabled, cacheline_aligned data is linked
833 into L1 data memory. (less latency)
835 config SYSCALL_TAB_L1
836 bool "Locate Syscall Table L1 Data Memory"
840 If enabled, the Syscall LUT is linked
841 into L1 data memory. (less latency)
843 config CPLB_SWITCH_TAB_L1
844 bool "Locate CPLB Switch Tables L1 Data Memory"
848 If enabled, the CPLB Switch Tables are linked
849 into L1 data memory. (less latency)
851 config CACHE_FLUSH_L1
852 bool "Locate cache flush funcs in L1 Inst Memory"
855 If enabled, the Blackfin cache flushing functions are linked
856 into L1 instruction memory.
858 Note that this might be required to address anomalies, but
859 these functions are pretty small, so it shouldn't be too bad.
860 If you are using a processor affected by an anomaly, the build
861 system will double check for you and prevent it.
864 bool "Support locating application stack in L1 Scratch Memory"
867 If enabled the application stack can be located in L1
868 scratch memory (less latency).
870 Currently only works with FLAT binaries.
872 config EXCEPTION_L1_SCRATCH
873 bool "Locate exception stack in L1 Scratch Memory"
875 depends on !APP_STACK_L1
877 Whenever an exception occurs, use the L1 Scratch memory for
878 stack storage. You cannot place the stacks of FLAT binaries
879 in L1 when using this option.
881 If you don't use L1 Scratch, then you should say Y here.
883 comment "Speed Optimizations"
884 config BFIN_INS_LOWOVERHEAD
885 bool "ins[bwl] low overhead, higher interrupt latency"
888 Reads on the Blackfin are speculative. In Blackfin terms, this means
889 they can be interrupted at any time (even after they have been issued
890 on to the external bus), and re-issued after the interrupt occurs.
891 For memory - this is not a big deal, since memory does not change if
894 If a FIFO is sitting on the end of the read, it will see two reads,
895 when the core only sees one since the FIFO receives both the read
896 which is cancelled (and not delivered to the core) and the one which
897 is re-issued (which is delivered to the core).
899 To solve this, interrupts are turned off before reads occur to
900 I/O space. This option controls which the overhead/latency of
901 controlling interrupts during this time
902 "n" turns interrupts off every read
903 (higher overhead, but lower interrupt latency)
904 "y" turns interrupts off every loop
905 (low overhead, but longer interrupt latency)
907 default behavior is to leave this set to on (type "Y"). If you are experiencing
908 interrupt latency issues, it is safe and OK to turn this off.
913 prompt "Kernel executes from"
915 Choose the memory type that the kernel will be running in.
920 The kernel will be resident in RAM when running.
925 The kernel will be resident in FLASH/ROM when running.
932 tristate "Enable Blackfin General Purpose Timers API"
935 Enable support for the General Purpose Timers API. If you
938 To compile this driver as a module, choose M here: the module
939 will be called gptimers.
942 prompt "Uncached DMA region"
943 default DMA_UNCACHED_1M
944 config DMA_UNCACHED_4M
945 bool "Enable 4M DMA region"
946 config DMA_UNCACHED_2M
947 bool "Enable 2M DMA region"
948 config DMA_UNCACHED_1M
949 bool "Enable 1M DMA region"
950 config DMA_UNCACHED_512K
951 bool "Enable 512K DMA region"
952 config DMA_UNCACHED_256K
953 bool "Enable 256K DMA region"
954 config DMA_UNCACHED_128K
955 bool "Enable 128K DMA region"
956 config DMA_UNCACHED_NONE
957 bool "Disable DMA region"
961 comment "Cache Support"
966 config BFIN_EXTMEM_ICACHEABLE
967 bool "Enable ICACHE for external memory"
968 depends on BFIN_ICACHE
970 config BFIN_L2_ICACHEABLE
971 bool "Enable ICACHE for L2 SRAM"
972 depends on BFIN_ICACHE
973 depends on BF54x || BF561
979 config BFIN_DCACHE_BANKA
980 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
981 depends on BFIN_DCACHE && !BF531
983 config BFIN_EXTMEM_DCACHEABLE
984 bool "Enable DCACHE for external memory"
985 depends on BFIN_DCACHE
988 prompt "External memory DCACHE policy"
989 depends on BFIN_EXTMEM_DCACHEABLE
990 default BFIN_EXTMEM_WRITEBACK if !SMP
991 default BFIN_EXTMEM_WRITETHROUGH if SMP
992 config BFIN_EXTMEM_WRITEBACK
997 Cached data will be written back to SDRAM only when needed.
998 This can give a nice increase in performance, but beware of
999 broken drivers that do not properly invalidate/flush their
1002 Write Through Policy:
1003 Cached data will always be written back to SDRAM when the
1004 cache is updated. This is a completely safe setting, but
1005 performance is worse than Write Back.
1007 If you are unsure of the options and you want to be safe,
1008 then go with Write Through.
1010 config BFIN_EXTMEM_WRITETHROUGH
1011 bool "Write through"
1014 Cached data will be written back to SDRAM only when needed.
1015 This can give a nice increase in performance, but beware of
1016 broken drivers that do not properly invalidate/flush their
1019 Write Through Policy:
1020 Cached data will always be written back to SDRAM when the
1021 cache is updated. This is a completely safe setting, but
1022 performance is worse than Write Back.
1024 If you are unsure of the options and you want to be safe,
1025 then go with Write Through.
1029 config BFIN_L2_DCACHEABLE
1030 bool "Enable DCACHE for L2 SRAM"
1031 depends on BFIN_DCACHE
1032 depends on (BF54x || BF561) && !SMP
1035 prompt "L2 SRAM DCACHE policy"
1036 depends on BFIN_L2_DCACHEABLE
1037 default BFIN_L2_WRITEBACK
1038 config BFIN_L2_WRITEBACK
1041 config BFIN_L2_WRITETHROUGH
1042 bool "Write through"
1046 comment "Memory Protection Unit"
1048 bool "Enable the memory protection unit (EXPERIMENTAL)"
1051 Use the processor's MPU to protect applications from accessing
1052 memory they do not own. This comes at a performance penalty
1053 and is recommended only for debugging.
1055 comment "Asynchronous Memory Configuration"
1057 menu "EBIU_AMGCTL Global Control"
1059 bool "Enable CLKOUT"
1063 bool "DMA has priority over core for ext. accesses"
1068 bool "Bank 0 16 bit packing enable"
1073 bool "Bank 1 16 bit packing enable"
1078 bool "Bank 2 16 bit packing enable"
1083 bool "Bank 3 16 bit packing enable"
1087 prompt "Enable Asynchronous Memory Banks"
1091 bool "Disable All Banks"
1094 bool "Enable Bank 0"
1096 config C_AMBEN_B0_B1
1097 bool "Enable Bank 0 & 1"
1099 config C_AMBEN_B0_B1_B2
1100 bool "Enable Bank 0 & 1 & 2"
1103 bool "Enable All Banks"
1107 menu "EBIU_AMBCTL Control"
1109 hex "Bank 0 (AMBCTL0.L)"
1112 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1113 used to control the Asynchronous Memory Bank 0 settings.
1116 hex "Bank 1 (AMBCTL0.H)"
1118 default 0x5558 if BF54x
1120 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1121 used to control the Asynchronous Memory Bank 1 settings.
1124 hex "Bank 2 (AMBCTL1.L)"
1127 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1128 used to control the Asynchronous Memory Bank 2 settings.
1131 hex "Bank 3 (AMBCTL1.H)"
1134 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1135 used to control the Asynchronous Memory Bank 3 settings.
1139 config EBIU_MBSCTLVAL
1140 hex "EBIU Bank Select Control Register"
1145 hex "Flash Memory Mode Control Register"
1150 hex "Flash Memory Bank Control Register"
1155 #############################################################################
1156 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1162 Support for PCI bus.
1164 source "drivers/pci/Kconfig"
1166 source "drivers/pcmcia/Kconfig"
1168 source "drivers/pci/hotplug/Kconfig"
1172 menu "Executable file formats"
1174 source "fs/Kconfig.binfmt"
1178 menu "Power management options"
1180 source "kernel/power/Kconfig"
1182 config ARCH_SUSPEND_POSSIBLE
1186 prompt "Standby Power Saving Mode"
1188 default PM_BFIN_SLEEP_DEEPER
1189 config PM_BFIN_SLEEP_DEEPER
1192 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1193 power dissipation by disabling the clock to the processor core (CCLK).
1194 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1195 to 0.85 V to provide the greatest power savings, while preserving the
1197 The PLL and system clock (SCLK) continue to operate at a very low
1198 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1199 the SDRAM is put into Self Refresh Mode. Typically an external event
1200 such as GPIO interrupt or RTC activity wakes up the processor.
1201 Various Peripherals such as UART, SPORT, PPI may not function as
1202 normal during Sleep Deeper, due to the reduced SCLK frequency.
1203 When in the sleep mode, system DMA access to L1 memory is not supported.
1205 If unsure, select "Sleep Deeper".
1207 config PM_BFIN_SLEEP
1210 Sleep Mode (High Power Savings) - The sleep mode reduces power
1211 dissipation by disabling the clock to the processor core (CCLK).
1212 The PLL and system clock (SCLK), however, continue to operate in
1213 this mode. Typically an external event or RTC activity will wake
1214 up the processor. When in the sleep mode, system DMA access to L1
1215 memory is not supported.
1217 If unsure, select "Sleep Deeper".
1220 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1223 config PM_BFIN_WAKE_PH6
1224 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1225 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1228 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1230 config PM_BFIN_WAKE_GP
1231 bool "Allow Wake-Up from GPIOs"
1232 depends on PM && BF54x
1235 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1236 (all processors, except ADSP-BF549). This option sets
1237 the general-purpose wake-up enable (GPWE) control bit to enable
1238 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1239 On ADSP-BF549 this option enables the the same functionality on the
1240 /MRXON pin also PH7.
1244 menu "CPU Frequency scaling"
1246 source "drivers/cpufreq/Kconfig"
1248 config BFIN_CPU_FREQ
1251 select CPU_FREQ_TABLE
1255 bool "CPU Voltage scaling"
1256 depends on EXPERIMENTAL
1260 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1261 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1262 manuals. There is a theoretical risk that during VDDINT transitions
1267 source "net/Kconfig"
1269 source "drivers/Kconfig"
1271 source "drivers/firmware/Kconfig"
1275 source "arch/blackfin/Kconfig.debug"
1277 source "security/Kconfig"
1279 source "crypto/Kconfig"
1281 source "lib/Kconfig"
projects / mirror_ubuntu-bionic-kernel.git / blob