arch/blackfin/Kconfig

   1 config MMU
   2         def_bool n
   3
   4 config FPU
   5         def_bool n
   6
   7 config RWSEM_GENERIC_SPINLOCK
   8         def_bool y
   9
  10 config RWSEM_XCHGADD_ALGORITHM
  11         def_bool n
  12
  13 config BLACKFIN
  14         def_bool y
  15         select HAVE_ARCH_KGDB
  16         select HAVE_ARCH_TRACEHOOK
  17         select HAVE_DYNAMIC_FTRACE
  18         select HAVE_FTRACE_MCOUNT_RECORD
  19         select HAVE_FUNCTION_GRAPH_TRACER
  20         select HAVE_FUNCTION_TRACER
  21         select HAVE_FUNCTION_TRACE_MCOUNT_TEST
  22         select HAVE_IDE
  23         select HAVE_KERNEL_GZIP if RAMKERNEL
  24         select HAVE_KERNEL_BZIP2 if RAMKERNEL
  25         select HAVE_KERNEL_LZMA if RAMKERNEL
  26         select HAVE_KERNEL_LZO if RAMKERNEL
  27         select HAVE_OPROFILE
  28         select HAVE_PERF_EVENTS
  29         select ARCH_HAVE_CUSTOM_GPIO_H
  30         select ARCH_REQUIRE_GPIOLIB
  31         select HAVE_UID16
  32         select HAVE_UNDERSCORE_SYMBOL_PREFIX
  33         select VIRT_TO_BUS
  34         select ARCH_WANT_IPC_PARSE_VERSION
  35         select GENERIC_ATOMIC64
  36         select GENERIC_IRQ_PROBE
  37         select USE_GENERIC_SMP_HELPERS if SMP
  38         select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
  39         select GENERIC_SMP_IDLE_THREAD
  40         select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
  41         select HAVE_MOD_ARCH_SPECIFIC
  42         select MODULES_USE_ELF_RELA
  43         select HAVE_DEBUG_STACKOVERFLOW
  44
  45 config GENERIC_CSUM
  46         def_bool y
  47
  48 config GENERIC_BUG
  49         def_bool y
  50         depends on BUG
  51
  52 config ZONE_DMA
  53         def_bool y
  54
  55 config GENERIC_GPIO
  56         def_bool y
  57
  58 config FORCE_MAX_ZONEORDER
  59         int
  60         default "14"
  61
  62 config GENERIC_CALIBRATE_DELAY
  63         def_bool y
  64
  65 config LOCKDEP_SUPPORT
  66         def_bool y
  67
  68 config STACKTRACE_SUPPORT
  69         def_bool y
  70
  71 config TRACE_IRQFLAGS_SUPPORT
  72         def_bool y
  73
  74 source "init/Kconfig"
  75
  76 source "kernel/Kconfig.preempt"
  77
  78 source "kernel/Kconfig.freezer"
  79
  80 menu "Blackfin Processor Options"
  81
  82 comment "Processor and Board Settings"
  83
  84 choice
  85         prompt "CPU"
  86         default BF533
  87
  88 config BF512
  89         bool "BF512"
  90         help
  91           BF512 Processor Support.
  92
  93 config BF514
  94         bool "BF514"
  95         help
  96           BF514 Processor Support.
  97
  98 config BF516
  99         bool "BF516"
 100         help
 101           BF516 Processor Support.
 102
 103 config BF518
 104         bool "BF518"
 105         help
 106           BF518 Processor Support.
 107
 108 config BF522
 109         bool "BF522"
 110         help
 111           BF522 Processor Support.
 112
 113 config BF523
 114         bool "BF523"
 115         help
 116           BF523 Processor Support.
 117
 118 config BF524
 119         bool "BF524"
 120         help
 121           BF524 Processor Support.
 122
 123 config BF525
 124         bool "BF525"
 125         help
 126           BF525 Processor Support.
 127
 128 config BF526
 129         bool "BF526"
 130         help
 131           BF526 Processor Support.
 132
 133 config BF527
 134         bool "BF527"
 135         help
 136           BF527 Processor Support.
 137
 138 config BF531
 139         bool "BF531"
 140         help
 141           BF531 Processor Support.
 142
 143 config BF532
 144         bool "BF532"
 145         help
 146           BF532 Processor Support.
 147
 148 config BF533
 149         bool "BF533"
 150         help
 151           BF533 Processor Support.
 152
 153 config BF534
 154         bool "BF534"
 155         help
 156           BF534 Processor Support.
 157
 158 config BF536
 159         bool "BF536"
 160         help
 161           BF536 Processor Support.
 162
 163 config BF537
 164         bool "BF537"
 165         help
 166           BF537 Processor Support.
 167
 168 config BF538
 169         bool "BF538"
 170         help
 171           BF538 Processor Support.
 172
 173 config BF539
 174         bool "BF539"
 175         help
 176           BF539 Processor Support.
 177
 178 config BF542_std
 179         bool "BF542"
 180         help
 181           BF542 Processor Support.
 182
 183 config BF542M
 184         bool "BF542m"
 185         help
 186           BF542 Processor Support.
 187
 188 config BF544_std
 189         bool "BF544"
 190         help
 191           BF544 Processor Support.
 192
 193 config BF544M
 194         bool "BF544m"
 195         help
 196           BF544 Processor Support.
 197
 198 config BF547_std
 199         bool "BF547"
 200         help
 201           BF547 Processor Support.
 202
 203 config BF547M
 204         bool "BF547m"
 205         help
 206           BF547 Processor Support.
 207
 208 config BF548_std
 209         bool "BF548"
 210         help
 211           BF548 Processor Support.
 212
 213 config BF548M
 214         bool "BF548m"
 215         help
 216           BF548 Processor Support.
 217
 218 config BF549_std
 219         bool "BF549"
 220         help
 221           BF549 Processor Support.
 222
 223 config BF549M
 224         bool "BF549m"
 225         help
 226           BF549 Processor Support.
 227
 228 config BF561
 229         bool "BF561"
 230         help
 231           BF561 Processor Support.
 232
 233 config BF609
 234         bool "BF609"
 235         select CLKDEV_LOOKUP
 236         help
 237           BF609 Processor Support.
 238
 239 endchoice
 240
 241 config SMP
 242         depends on BF561
 243         select TICKSOURCE_CORETMR
 244         bool "Symmetric multi-processing support"
 245         ---help---
 246           This enables support for systems with more than one CPU,
 247           like the dual core BF561. If you have a system with only one
 248           CPU, say N. If you have a system with more than one CPU, say Y.
 249
 250           If you don't know what to do here, say N.
 251
 252 config NR_CPUS
 253         int
 254         depends on SMP
 255         default 2 if BF561
 256
 257 config HOTPLUG_CPU
 258         bool "Support for hot-pluggable CPUs"
 259         depends on SMP
 260         default y
 261
 262 config BF_REV_MIN
 263         int
 264         default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
 265         default 2 if (BF537 || BF536 || BF534)
 266         default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
 267         default 4 if (BF538 || BF539)
 268
 269 config BF_REV_MAX
 270         int
 271         default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
 272         default 3 if (BF537 || BF536 || BF534 || BF54xM)
 273         default 5 if (BF561 || BF538 || BF539)
 274         default 6 if (BF533 || BF532 || BF531)
 275
 276 choice
 277         prompt "Silicon Rev"
 278         default BF_REV_0_0 if (BF51x || BF52x || BF60x)
 279         default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
 280         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
 281
 282 config BF_REV_0_0
 283         bool "0.0"
 284         depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
 285
 286 config BF_REV_0_1
 287         bool "0.1"
 288         depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
 289
 290 config BF_REV_0_2
 291         bool "0.2"
 292         depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
 293
 294 config BF_REV_0_3
 295         bool "0.3"
 296         depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 297
 298 config BF_REV_0_4
 299         bool "0.4"
 300         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x)
 301
 302 config BF_REV_0_5
 303         bool "0.5"
 304         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 305
 306 config BF_REV_0_6
 307         bool "0.6"
 308         depends on (BF533 || BF532 || BF531)
 309
 310 config BF_REV_ANY
 311         bool "any"
 312
 313 config BF_REV_NONE
 314         bool "none"
 315
 316 endchoice
 317
 318 config BF53x
 319         bool
 320         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 321         default y
 322
 323 config GPIO_ADI
 324         def_bool y
 325         depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561)
 326
 327 config PINCTRL
 328         def_bool y
 329         depends on BF54x || BF60x
 330
 331 config MEM_MT48LC64M4A2FB_7E
 332         bool
 333         depends on (BFIN533_STAMP)
 334         default y
 335
 336 config MEM_MT48LC16M16A2TG_75
 337         bool
 338         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 339                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
 340                 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
 341                 || BFIN527_BLUETECHNIX_CM)
 342         default y
 343
 344 config MEM_MT48LC32M8A2_75
 345         bool
 346         depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 347         default y
 348
 349 config MEM_MT48LC8M32B2B5_7
 350         bool
 351         depends on (BFIN561_BLUETECHNIX_CM)
 352         default y
 353
 354 config MEM_MT48LC32M16A2TG_75
 355         bool
 356         depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
 357         default y
 358
 359 config MEM_MT48H32M16LFCJ_75
 360         bool
 361         depends on (BFIN526_EZBRD)
 362         default y
 363
 364 config MEM_MT47H64M16
 365         bool
 366         depends on (BFIN609_EZKIT)
 367         default y
 368
 369 source "arch/blackfin/mach-bf518/Kconfig"
 370 source "arch/blackfin/mach-bf527/Kconfig"
 371 source "arch/blackfin/mach-bf533/Kconfig"
 372 source "arch/blackfin/mach-bf561/Kconfig"
 373 source "arch/blackfin/mach-bf537/Kconfig"
 374 source "arch/blackfin/mach-bf538/Kconfig"
 375 source "arch/blackfin/mach-bf548/Kconfig"
 376 source "arch/blackfin/mach-bf609/Kconfig"
 377
 378 menu "Board customizations"
 379
 380 config CMDLINE_BOOL
 381         bool "Default bootloader kernel arguments"
 382
 383 config CMDLINE
 384         string "Initial kernel command string"
 385         depends on CMDLINE_BOOL
 386         default "console=ttyBF0,57600"
 387         help
 388           If you don't have a boot loader capable of passing a command line string
 389           to the kernel, you may specify one here. As a minimum, you should specify
 390           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 391
 392 config BOOT_LOAD
 393         hex "Kernel load address for booting"
 394         default "0x1000"
 395         range 0x1000 0x20000000
 396         help
 397           This option allows you to set the load address of the kernel.
 398           This can be useful if you are on a board which has a small amount
 399           of memory or you wish to reserve some memory at the beginning of
 400           the address space.
 401
 402           Note that you need to keep this value above 4k (0x1000) as this
 403           memory region is used to capture NULL pointer references as well
 404           as some core kernel functions.
 405
 406 config PHY_RAM_BASE_ADDRESS
 407         hex "Physical RAM Base"
 408         default 0x0
 409         help
 410           set BF609 FPGA physical SRAM base address
 411
 412 config ROM_BASE
 413         hex "Kernel ROM Base"
 414         depends on ROMKERNEL
 415         default "0x20040040"
 416         range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
 417         range 0x20000000 0x30000000 if (BF54x || BF561)
 418         range 0xB0000000 0xC0000000 if (BF60x)
 419         help
 420           Make sure your ROM base does not include any file-header
 421           information that is prepended to the kernel.
 422
 423           For example, the bootable U-Boot format (created with
 424           mkimage) has a 64 byte header (0x40).  So while the image
 425           you write to flash might start at say 0x20080000, you have
 426           to add 0x40 to get the kernel's ROM base as it will come
 427           after the header.
 428
 429 comment "Clock/PLL Setup"
 430
 431 config CLKIN_HZ
 432         int "Frequency of the crystal on the board in Hz"
 433         default "10000000" if BFIN532_IP0X
 434         default "11059200" if BFIN533_STAMP
 435         default "24576000" if PNAV10
 436         default "25000000" # most people use this
 437         default "27000000" if BFIN533_EZKIT
 438         default "30000000" if BFIN561_EZKIT
 439         default "24000000" if BFIN527_AD7160EVAL
 440         help
 441           The frequency of CLKIN crystal oscillator on the board in Hz.
 442           Warning: This value should match the crystal on the board. Otherwise,
 443           peripherals won't work properly.
 444
 445 config BFIN_KERNEL_CLOCK
 446         bool "Re-program Clocks while Kernel boots?"
 447         default n
 448         help
 449           This option decides if kernel clocks are re-programed from the
 450           bootloader settings. If the clocks are not set, the SDRAM settings
 451           are also not changed, and the Bootloader does 100% of the hardware
 452           configuration.
 453
 454 config PLL_BYPASS
 455         bool "Bypass PLL"
 456         depends on BFIN_KERNEL_CLOCK && (!BF60x)
 457         default n
 458
 459 config CLKIN_HALF
 460         bool "Half Clock In"
 461         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 462         default n
 463         help
 464           If this is set the clock will be divided by 2, before it goes to the PLL.
 465
 466 config VCO_MULT
 467         int "VCO Multiplier"
 468         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 469         range 1 64
 470         default "22" if BFIN533_EZKIT
 471         default "45" if BFIN533_STAMP
 472         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 473         default "22" if BFIN533_BLUETECHNIX_CM
 474         default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 475         default "20" if (BFIN561_EZKIT || BF609)
 476         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 477         default "25" if BFIN527_AD7160EVAL
 478         help
 479           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 480           PLL Frequency = (Crystal Frequency) * (this setting)
 481
 482 choice
 483         prompt "Core Clock Divider"
 484         depends on BFIN_KERNEL_CLOCK
 485         default CCLK_DIV_1
 486         help
 487           This sets the frequency of the core. It can be 1, 2, 4 or 8
 488           Core Frequency = (PLL frequency) / (this setting)
 489
 490 config CCLK_DIV_1
 491         bool "1"
 492
 493 config CCLK_DIV_2
 494         bool "2"
 495
 496 config CCLK_DIV_4
 497         bool "4"
 498
 499 config CCLK_DIV_8
 500         bool "8"
 501 endchoice
 502
 503 config SCLK_DIV
 504         int "System Clock Divider"
 505         depends on BFIN_KERNEL_CLOCK
 506         range 1 15
 507         default 4
 508         help
 509           This sets the frequency of the system clock (including SDRAM or DDR) on
 510           !BF60x else it set the clock for system buses and provides the
 511           source from which SCLK0 and SCLK1 are derived.
 512           This can be between 1 and 15
 513           System Clock = (PLL frequency) / (this setting)
 514
 515 config SCLK0_DIV
 516         int "System Clock0 Divider"
 517         depends on BFIN_KERNEL_CLOCK && BF60x
 518         range 1 15
 519         default 1
 520         help
 521           This sets the frequency of the system clock0 for PVP and all other
 522           peripherals not clocked by SCLK1.
 523           This can be between 1 and 15
 524           System Clock0 = (System Clock) / (this setting)
 525
 526 config SCLK1_DIV
 527         int "System Clock1 Divider"
 528         depends on BFIN_KERNEL_CLOCK && BF60x
 529         range 1 15
 530         default 1
 531         help
 532           This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
 533           This can be between 1 and 15
 534           System Clock1 = (System Clock) / (this setting)
 535
 536 config DCLK_DIV
 537         int "DDR Clock Divider"
 538         depends on BFIN_KERNEL_CLOCK && BF60x
 539         range 1 15
 540         default 2
 541         help
 542           This sets the frequency of the DDR memory.
 543           This can be between 1 and 15
 544           DDR Clock = (PLL frequency) / (this setting)
 545
 546 choice
 547         prompt "DDR SDRAM Chip Type"
 548         depends on BFIN_KERNEL_CLOCK
 549         depends on BF54x
 550         default MEM_MT46V32M16_5B
 551
 552 config MEM_MT46V32M16_6T
 553         bool "MT46V32M16_6T"
 554
 555 config MEM_MT46V32M16_5B
 556         bool "MT46V32M16_5B"
 557 endchoice
 558
 559 choice
 560         prompt "DDR/SDRAM Timing"
 561         depends on BFIN_KERNEL_CLOCK && !BF60x
 562         default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 563         help
 564           This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 565           The calculated SDRAM timing parameters may not be 100%
 566           accurate - This option is therefore marked experimental.
 567
 568 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 569         bool "Calculate Timings"
 570
 571 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 572         bool "Provide accurate Timings based on target SCLK"
 573         help
 574           Please consult the Blackfin Hardware Reference Manuals as well
 575           as the memory device datasheet.
 576           http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 577 endchoice
 578
 579 menu "Memory Init Control"
 580         depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 581
 582 config MEM_DDRCTL0
 583         depends on BF54x
 584         hex "DDRCTL0"
 585         default 0x0
 586
 587 config MEM_DDRCTL1
 588         depends on BF54x
 589         hex "DDRCTL1"
 590         default 0x0
 591
 592 config MEM_DDRCTL2
 593         depends on BF54x
 594         hex "DDRCTL2"
 595         default 0x0
 596
 597 config MEM_EBIU_DDRQUE
 598         depends on BF54x
 599         hex "DDRQUE"
 600         default 0x0
 601
 602 config MEM_SDRRC
 603         depends on !BF54x
 604         hex "SDRRC"
 605         default 0x0
 606
 607 config MEM_SDGCTL
 608         depends on !BF54x
 609         hex "SDGCTL"
 610         default 0x0
 611 endmenu
 612
 613 #
 614 # Max & Min Speeds for various Chips
 615 #
 616 config MAX_VCO_HZ
 617         int
 618         default 400000000 if BF512
 619         default 400000000 if BF514
 620         default 400000000 if BF516
 621         default 400000000 if BF518
 622         default 400000000 if BF522
 623         default 600000000 if BF523
 624         default 400000000 if BF524
 625         default 600000000 if BF525
 626         default 400000000 if BF526
 627         default 600000000 if BF527
 628         default 400000000 if BF531
 629         default 400000000 if BF532
 630         default 750000000 if BF533
 631         default 500000000 if BF534
 632         default 400000000 if BF536
 633         default 600000000 if BF537
 634         default 533333333 if BF538
 635         default 533333333 if BF539
 636         default 600000000 if BF542
 637         default 533333333 if BF544
 638         default 600000000 if BF547
 639         default 600000000 if BF548
 640         default 533333333 if BF549
 641         default 600000000 if BF561
 642         default 800000000 if BF609
 643
 644 config MIN_VCO_HZ
 645         int
 646         default 50000000
 647
 648 config MAX_SCLK_HZ
 649         int
 650         default 200000000 if BF609
 651         default 133333333
 652
 653 config MIN_SCLK_HZ
 654         int
 655         default 27000000
 656
 657 comment "Kernel Timer/Scheduler"
 658
 659 source kernel/Kconfig.hz
 660
 661 config SET_GENERIC_CLOCKEVENTS
 662         bool "Generic clock events"
 663         default y
 664         select GENERIC_CLOCKEVENTS
 665
 666 menu "Clock event device"
 667         depends on GENERIC_CLOCKEVENTS
 668 config TICKSOURCE_GPTMR0
 669         bool "GPTimer0"
 670         depends on !SMP
 671         select BFIN_GPTIMERS
 672
 673 config TICKSOURCE_CORETMR
 674         bool "Core timer"
 675         default y
 676 endmenu
 677
 678 menu "Clock souce"
 679         depends on GENERIC_CLOCKEVENTS
 680 config CYCLES_CLOCKSOURCE
 681         bool "CYCLES"
 682         default y
 683         depends on !BFIN_SCRATCH_REG_CYCLES
 684         depends on !SMP
 685         help
 686           If you say Y here, you will enable support for using the 'cycles'
 687           registers as a clock source.  Doing so means you will be unable to
 688           safely write to the 'cycles' register during runtime.  You will
 689           still be able to read it (such as for performance monitoring), but
 690           writing the registers will most likely crash the kernel.
 691
 692 config GPTMR0_CLOCKSOURCE
 693         bool "GPTimer0"
 694         select BFIN_GPTIMERS
 695         depends on !TICKSOURCE_GPTMR0
 696 endmenu
 697
 698 comment "Misc"
 699
 700 choice
 701         prompt "Blackfin Exception Scratch Register"
 702         default BFIN_SCRATCH_REG_RETN
 703         help
 704           Select the resource to reserve for the Exception handler:
 705             - RETN: Non-Maskable Interrupt (NMI)
 706             - RETE: Exception Return (JTAG/ICE)
 707             - CYCLES: Performance counter
 708
 709           If you are unsure, please select "RETN".
 710
 711 config BFIN_SCRATCH_REG_RETN
 712         bool "RETN"
 713         help
 714           Use the RETN register in the Blackfin exception handler
 715           as a stack scratch register.  This means you cannot
 716           safely use NMI on the Blackfin while running Linux, but
 717           you can debug the system with a JTAG ICE and use the
 718           CYCLES performance registers.
 719
 720           If you are unsure, please select "RETN".
 721
 722 config BFIN_SCRATCH_REG_RETE
 723         bool "RETE"
 724         help
 725           Use the RETE register in the Blackfin exception handler
 726           as a stack scratch register.  This means you cannot
 727           safely use a JTAG ICE while debugging a Blackfin board,
 728           but you can safely use the CYCLES performance registers
 729           and the NMI.
 730
 731           If you are unsure, please select "RETN".
 732
 733 config BFIN_SCRATCH_REG_CYCLES
 734         bool "CYCLES"
 735         help
 736           Use the CYCLES register in the Blackfin exception handler
 737           as a stack scratch register.  This means you cannot
 738           safely use the CYCLES performance registers on a Blackfin
 739           board at anytime, but you can debug the system with a JTAG
 740           ICE and use the NMI.
 741
 742           If you are unsure, please select "RETN".
 743
 744 endchoice
 745
 746 endmenu
 747
 748
 749 menu "Blackfin Kernel Optimizations"
 750
 751 comment "Memory Optimizations"
 752
 753 config I_ENTRY_L1
 754         bool "Locate interrupt entry code in L1 Memory"
 755         default y
 756         depends on !SMP
 757         help
 758           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 759           into L1 instruction memory. (less latency)
 760
 761 config EXCPT_IRQ_SYSC_L1
 762         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 763         default y
 764         depends on !SMP
 765         help
 766           If enabled, the entire ASM lowlevel exception and interrupt entry code
 767           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 768           (less latency)
 769
 770 config DO_IRQ_L1
 771         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 772         default y
 773         depends on !SMP
 774         help
 775           If enabled, the frequently called do_irq dispatcher function is linked
 776           into L1 instruction memory. (less latency)
 777
 778 config CORE_TIMER_IRQ_L1
 779         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 780         default y
 781         depends on !SMP
 782         help
 783           If enabled, the frequently called timer_interrupt() function is linked
 784           into L1 instruction memory. (less latency)
 785
 786 config IDLE_L1
 787         bool "Locate frequently idle function in L1 Memory"
 788         default y
 789         depends on !SMP
 790         help
 791           If enabled, the frequently called idle function is linked
 792           into L1 instruction memory. (less latency)
 793
 794 config SCHEDULE_L1
 795         bool "Locate kernel schedule function in L1 Memory"
 796         default y
 797         depends on !SMP
 798         help
 799           If enabled, the frequently called kernel schedule is linked
 800           into L1 instruction memory. (less latency)
 801
 802 config ARITHMETIC_OPS_L1
 803         bool "Locate kernel owned arithmetic functions in L1 Memory"
 804         default y
 805         depends on !SMP
 806         help
 807           If enabled, arithmetic functions are linked
 808           into L1 instruction memory. (less latency)
 809
 810 config ACCESS_OK_L1
 811         bool "Locate access_ok function in L1 Memory"
 812         default y
 813         depends on !SMP
 814         help
 815           If enabled, the access_ok function is linked
 816           into L1 instruction memory. (less latency)
 817
 818 config MEMSET_L1
 819         bool "Locate memset function in L1 Memory"
 820         default y
 821         depends on !SMP
 822         help
 823           If enabled, the memset function is linked
 824           into L1 instruction memory. (less latency)
 825
 826 config MEMCPY_L1
 827         bool "Locate memcpy function in L1 Memory"
 828         default y
 829         depends on !SMP
 830         help
 831           If enabled, the memcpy function is linked
 832           into L1 instruction memory. (less latency)
 833
 834 config STRCMP_L1
 835         bool "locate strcmp function in L1 Memory"
 836         default y
 837         depends on !SMP
 838         help
 839           If enabled, the strcmp function is linked
 840           into L1 instruction memory (less latency).
 841
 842 config STRNCMP_L1
 843         bool "locate strncmp function in L1 Memory"
 844         default y
 845         depends on !SMP
 846         help
 847           If enabled, the strncmp function is linked
 848           into L1 instruction memory (less latency).
 849
 850 config STRCPY_L1
 851         bool "locate strcpy function in L1 Memory"
 852         default y
 853         depends on !SMP
 854         help
 855           If enabled, the strcpy function is linked
 856           into L1 instruction memory (less latency).
 857
 858 config STRNCPY_L1
 859         bool "locate strncpy function in L1 Memory"
 860         default y
 861         depends on !SMP
 862         help
 863           If enabled, the strncpy function is linked
 864           into L1 instruction memory (less latency).
 865
 866 config SYS_BFIN_SPINLOCK_L1
 867         bool "Locate sys_bfin_spinlock function in L1 Memory"
 868         default y
 869         depends on !SMP
 870         help
 871           If enabled, sys_bfin_spinlock function is linked
 872           into L1 instruction memory. (less latency)
 873
 874 config IP_CHECKSUM_L1
 875         bool "Locate IP Checksum function in L1 Memory"
 876         default n
 877         depends on !SMP
 878         help
 879           If enabled, the IP Checksum function is linked
 880           into L1 instruction memory. (less latency)
 881
 882 config CACHELINE_ALIGNED_L1
 883         bool "Locate cacheline_aligned data to L1 Data Memory"
 884         default y if !BF54x
 885         default n if BF54x
 886         depends on !SMP && !BF531 && !CRC32
 887         help
 888           If enabled, cacheline_aligned data is linked
 889           into L1 data memory. (less latency)
 890
 891 config SYSCALL_TAB_L1
 892         bool "Locate Syscall Table L1 Data Memory"
 893         default n
 894         depends on !SMP && !BF531
 895         help
 896           If enabled, the Syscall LUT is linked
 897           into L1 data memory. (less latency)
 898
 899 config CPLB_SWITCH_TAB_L1
 900         bool "Locate CPLB Switch Tables L1 Data Memory"
 901         default n
 902         depends on !SMP && !BF531
 903         help
 904           If enabled, the CPLB Switch Tables are linked
 905           into L1 data memory. (less latency)
 906
 907 config ICACHE_FLUSH_L1
 908         bool "Locate icache flush funcs in L1 Inst Memory"
 909         default y
 910         help
 911           If enabled, the Blackfin icache flushing functions are linked
 912           into L1 instruction memory.
 913
 914           Note that this might be required to address anomalies, but
 915           these functions are pretty small, so it shouldn't be too bad.
 916           If you are using a processor affected by an anomaly, the build
 917           system will double check for you and prevent it.
 918
 919 config DCACHE_FLUSH_L1
 920         bool "Locate dcache flush funcs in L1 Inst Memory"
 921         default y
 922         depends on !SMP
 923         help
 924           If enabled, the Blackfin dcache flushing functions are linked
 925           into L1 instruction memory.
 926
 927 config APP_STACK_L1
 928         bool "Support locating application stack in L1 Scratch Memory"
 929         default y
 930         depends on !SMP
 931         help
 932           If enabled the application stack can be located in L1
 933           scratch memory (less latency).
 934
 935           Currently only works with FLAT binaries.
 936
 937 config EXCEPTION_L1_SCRATCH
 938         bool "Locate exception stack in L1 Scratch Memory"
 939         default n
 940         depends on !SMP && !APP_STACK_L1
 941         help
 942           Whenever an exception occurs, use the L1 Scratch memory for
 943           stack storage.  You cannot place the stacks of FLAT binaries
 944           in L1 when using this option.
 945
 946           If you don't use L1 Scratch, then you should say Y here.
 947
 948 comment "Speed Optimizations"
 949 config BFIN_INS_LOWOVERHEAD
 950         bool "ins[bwl] low overhead, higher interrupt latency"
 951         default y
 952         depends on !SMP
 953         help
 954           Reads on the Blackfin are speculative. In Blackfin terms, this means
 955           they can be interrupted at any time (even after they have been issued
 956           on to the external bus), and re-issued after the interrupt occurs.
 957           For memory - this is not a big deal, since memory does not change if
 958           it sees a read.
 959
 960           If a FIFO is sitting on the end of the read, it will see two reads,
 961           when the core only sees one since the FIFO receives both the read
 962           which is cancelled (and not delivered to the core) and the one which
 963           is re-issued (which is delivered to the core).
 964
 965           To solve this, interrupts are turned off before reads occur to
 966           I/O space. This option controls which the overhead/latency of
 967           controlling interrupts during this time
 968            "n" turns interrupts off every read
 969                 (higher overhead, but lower interrupt latency)
 970            "y" turns interrupts off every loop
 971                 (low overhead, but longer interrupt latency)
 972
 973           default behavior is to leave this set to on (type "Y"). If you are experiencing
 974           interrupt latency issues, it is safe and OK to turn this off.
 975
 976 endmenu
 977
 978 choice
 979         prompt "Kernel executes from"
 980         help
 981           Choose the memory type that the kernel will be running in.
 982
 983 config RAMKERNEL
 984         bool "RAM"
 985         help
 986           The kernel will be resident in RAM when running.
 987
 988 config ROMKERNEL
 989         bool "ROM"
 990         help
 991           The kernel will be resident in FLASH/ROM when running.
 992
 993 endchoice
 994
 995 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
 996 config XIP_KERNEL
 997         bool
 998         default y
 999         depends on ROMKERNEL
1000
1001 source "mm/Kconfig"
1002
1003 config BFIN_GPTIMERS
1004         tristate "Enable Blackfin General Purpose Timers API"
1005         default n
1006         help
1007           Enable support for the General Purpose Timers API.  If you
1008           are unsure, say N.
1009
1010           To compile this driver as a module, choose M here: the module
1011           will be called gptimers.
1012
1013 choice
1014         prompt "Uncached DMA region"
1015         default DMA_UNCACHED_1M
1016 config DMA_UNCACHED_32M
1017         bool "Enable 32M DMA region"
1018 config DMA_UNCACHED_16M
1019         bool "Enable 16M DMA region"
1020 config DMA_UNCACHED_8M
1021         bool "Enable 8M DMA region"
1022 config DMA_UNCACHED_4M
1023         bool "Enable 4M DMA region"
1024 config DMA_UNCACHED_2M
1025         bool "Enable 2M DMA region"
1026 config DMA_UNCACHED_1M
1027         bool "Enable 1M DMA region"
1028 config DMA_UNCACHED_512K
1029         bool "Enable 512K DMA region"
1030 config DMA_UNCACHED_256K
1031         bool "Enable 256K DMA region"
1032 config DMA_UNCACHED_128K
1033         bool "Enable 128K DMA region"
1034 config DMA_UNCACHED_NONE
1035         bool "Disable DMA region"
1036 endchoice
1037
1038
1039 comment "Cache Support"
1040
1041 config BFIN_ICACHE
1042         bool "Enable ICACHE"
1043         default y
1044 config BFIN_EXTMEM_ICACHEABLE
1045         bool "Enable ICACHE for external memory"
1046         depends on BFIN_ICACHE
1047         default y
1048 config BFIN_L2_ICACHEABLE
1049         bool "Enable ICACHE for L2 SRAM"
1050         depends on BFIN_ICACHE
1051         depends on (BF54x || BF561 || BF60x) && !SMP
1052         default n
1053
1054 config BFIN_DCACHE
1055         bool "Enable DCACHE"
1056         default y
1057 config BFIN_DCACHE_BANKA
1058         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1059         depends on BFIN_DCACHE && !BF531
1060         default n
1061 config BFIN_EXTMEM_DCACHEABLE
1062         bool "Enable DCACHE for external memory"
1063         depends on BFIN_DCACHE
1064         default y
1065 choice
1066         prompt "External memory DCACHE policy"
1067         depends on BFIN_EXTMEM_DCACHEABLE
1068         default BFIN_EXTMEM_WRITEBACK if !SMP
1069         default BFIN_EXTMEM_WRITETHROUGH if SMP
1070 config BFIN_EXTMEM_WRITEBACK
1071         bool "Write back"
1072         depends on !SMP
1073         help
1074           Write Back Policy:
1075             Cached data will be written back to SDRAM only when needed.
1076             This can give a nice increase in performance, but beware of
1077             broken drivers that do not properly invalidate/flush their
1078             cache.
1079
1080           Write Through Policy:
1081             Cached data will always be written back to SDRAM when the
1082             cache is updated.  This is a completely safe setting, but
1083             performance is worse than Write Back.
1084
1085           If you are unsure of the options and you want to be safe,
1086           then go with Write Through.
1087
1088 config BFIN_EXTMEM_WRITETHROUGH
1089         bool "Write through"
1090         help
1091           Write Back Policy:
1092             Cached data will be written back to SDRAM only when needed.
1093             This can give a nice increase in performance, but beware of
1094             broken drivers that do not properly invalidate/flush their
1095             cache.
1096
1097           Write Through Policy:
1098             Cached data will always be written back to SDRAM when the
1099             cache is updated.  This is a completely safe setting, but
1100             performance is worse than Write Back.
1101
1102           If you are unsure of the options and you want to be safe,
1103           then go with Write Through.
1104
1105 endchoice
1106
1107 config BFIN_L2_DCACHEABLE
1108         bool "Enable DCACHE for L2 SRAM"
1109         depends on BFIN_DCACHE
1110         depends on (BF54x || BF561 || BF60x) && !SMP
1111         default n
1112 choice
1113         prompt "L2 SRAM DCACHE policy"
1114         depends on BFIN_L2_DCACHEABLE
1115         default BFIN_L2_WRITEBACK
1116 config BFIN_L2_WRITEBACK
1117         bool "Write back"
1118
1119 config BFIN_L2_WRITETHROUGH
1120         bool "Write through"
1121 endchoice
1122
1123
1124 comment "Memory Protection Unit"
1125 config MPU
1126         bool "Enable the memory protection unit"
1127         default n
1128         help
1129           Use the processor's MPU to protect applications from accessing
1130           memory they do not own.  This comes at a performance penalty
1131           and is recommended only for debugging.
1132
1133 comment "Asynchronous Memory Configuration"
1134
1135 menu "EBIU_AMGCTL Global Control"
1136         depends on !BF60x
1137 config C_AMCKEN
1138         bool "Enable CLKOUT"
1139         default y
1140
1141 config C_CDPRIO
1142         bool "DMA has priority over core for ext. accesses"
1143         default n
1144
1145 config C_B0PEN
1146         depends on BF561
1147         bool "Bank 0 16 bit packing enable"
1148         default y
1149
1150 config C_B1PEN
1151         depends on BF561
1152         bool "Bank 1 16 bit packing enable"
1153         default y
1154
1155 config C_B2PEN
1156         depends on BF561
1157         bool "Bank 2 16 bit packing enable"
1158         default y
1159
1160 config C_B3PEN
1161         depends on BF561
1162         bool "Bank 3 16 bit packing enable"
1163         default n
1164
1165 choice
1166         prompt "Enable Asynchronous Memory Banks"
1167         default C_AMBEN_ALL
1168
1169 config C_AMBEN
1170         bool "Disable All Banks"
1171
1172 config C_AMBEN_B0
1173         bool "Enable Bank 0"
1174
1175 config C_AMBEN_B0_B1
1176         bool "Enable Bank 0 & 1"
1177
1178 config C_AMBEN_B0_B1_B2
1179         bool "Enable Bank 0 & 1 & 2"
1180
1181 config C_AMBEN_ALL
1182         bool "Enable All Banks"
1183 endchoice
1184 endmenu
1185
1186 menu "EBIU_AMBCTL Control"
1187         depends on !BF60x
1188 config BANK_0
1189         hex "Bank 0 (AMBCTL0.L)"
1190         default 0x7BB0
1191         help
1192           These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1193           used to control the Asynchronous Memory Bank 0 settings.
1194
1195 config BANK_1
1196         hex "Bank 1 (AMBCTL0.H)"
1197         default 0x7BB0
1198         default 0x5558 if BF54x
1199         help
1200           These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1201           used to control the Asynchronous Memory Bank 1 settings.
1202
1203 config BANK_2
1204         hex "Bank 2 (AMBCTL1.L)"
1205         default 0x7BB0
1206         help
1207           These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1208           used to control the Asynchronous Memory Bank 2 settings.
1209
1210 config BANK_3
1211         hex "Bank 3 (AMBCTL1.H)"
1212         default 0x99B3
1213         help
1214           These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1215           used to control the Asynchronous Memory Bank 3 settings.
1216
1217 endmenu
1218
1219 config EBIU_MBSCTLVAL
1220         hex "EBIU Bank Select Control Register"
1221         depends on BF54x
1222         default 0
1223
1224 config EBIU_MODEVAL
1225         hex "Flash Memory Mode Control Register"
1226         depends on BF54x
1227         default 1
1228
1229 config EBIU_FCTLVAL
1230         hex "Flash Memory Bank Control Register"
1231         depends on BF54x
1232         default 6
1233 endmenu
1234
1235 #############################################################################
1236 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1237
1238 config PCI
1239         bool "PCI support"
1240         depends on BROKEN
1241         help
1242           Support for PCI bus.
1243
1244 source "drivers/pci/Kconfig"
1245
1246 source "drivers/pcmcia/Kconfig"
1247
1248 source "drivers/pci/hotplug/Kconfig"
1249
1250 endmenu
1251
1252 menu "Executable file formats"
1253
1254 source "fs/Kconfig.binfmt"
1255
1256 endmenu
1257
1258 menu "Power management options"
1259
1260 source "kernel/power/Kconfig"
1261
1262 config ARCH_SUSPEND_POSSIBLE
1263         def_bool y
1264
1265 choice
1266         prompt "Standby Power Saving Mode"
1267         depends on PM && !BF60x
1268         default PM_BFIN_SLEEP_DEEPER
1269 config  PM_BFIN_SLEEP_DEEPER
1270         bool "Sleep Deeper"
1271         help
1272           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1273           power dissipation by disabling the clock to the processor core (CCLK).
1274           Furthermore, Standby sets the internal power supply voltage (VDDINT)
1275           to 0.85 V to provide the greatest power savings, while preserving the
1276           processor state.
1277           The PLL and system clock (SCLK) continue to operate at a very low
1278           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1279           the SDRAM is put into Self Refresh Mode. Typically an external event
1280           such as GPIO interrupt or RTC activity wakes up the processor.
1281           Various Peripherals such as UART, SPORT, PPI may not function as
1282           normal during Sleep Deeper, due to the reduced SCLK frequency.
1283           When in the sleep mode, system DMA access to L1 memory is not supported.
1284
1285           If unsure, select "Sleep Deeper".
1286
1287 config  PM_BFIN_SLEEP
1288         bool "Sleep"
1289         help
1290           Sleep Mode (High Power Savings) - The sleep mode reduces power
1291           dissipation by disabling the clock to the processor core (CCLK).
1292           The PLL and system clock (SCLK), however, continue to operate in
1293           this mode. Typically an external event or RTC activity will wake
1294           up the processor. When in the sleep mode, system DMA access to L1
1295           memory is not supported.
1296
1297           If unsure, select "Sleep Deeper".
1298 endchoice
1299
1300 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1301         depends on PM
1302
1303 config PM_BFIN_WAKE_PH6
1304         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1305         depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1306         default n
1307         help
1308           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1309
1310 config PM_BFIN_WAKE_GP
1311         bool "Allow Wake-Up from GPIOs"
1312         depends on PM && BF54x
1313         default n
1314         help
1315           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1316           (all processors, except ADSP-BF549). This option sets
1317           the general-purpose wake-up enable (GPWE) control bit to enable
1318           wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1319           On ADSP-BF549 this option enables the same functionality on the
1320           /MRXON pin also PH7.
1321
1322 config PM_BFIN_WAKE_PA15
1323         bool "Allow Wake-Up from PA15"
1324         depends on PM && BF60x
1325         default n
1326         help
1327           Enable PA15 Wake-Up
1328
1329 config PM_BFIN_WAKE_PA15_POL
1330         int "Wake-up priority"
1331         depends on PM_BFIN_WAKE_PA15
1332         default 0
1333         help
1334           Wake-Up priority 0(low) 1(high)
1335
1336 config PM_BFIN_WAKE_PB15
1337         bool "Allow Wake-Up from PB15"
1338         depends on PM && BF60x
1339         default n
1340         help
1341           Enable PB15 Wake-Up
1342
1343 config PM_BFIN_WAKE_PB15_POL
1344         int "Wake-up priority"
1345         depends on PM_BFIN_WAKE_PB15
1346         default 0
1347         help
1348           Wake-Up priority 0(low) 1(high)
1349
1350 config PM_BFIN_WAKE_PC15
1351         bool "Allow Wake-Up from PC15"
1352         depends on PM && BF60x
1353         default n
1354         help
1355           Enable PC15 Wake-Up
1356
1357 config PM_BFIN_WAKE_PC15_POL
1358         int "Wake-up priority"
1359         depends on PM_BFIN_WAKE_PC15
1360         default 0
1361         help
1362           Wake-Up priority 0(low) 1(high)
1363
1364 config PM_BFIN_WAKE_PD06
1365         bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
1366         depends on PM && BF60x
1367         default n
1368         help
1369           Enable PD06(ETH0_PHYINT) Wake-up
1370
1371 config PM_BFIN_WAKE_PD06_POL
1372         int "Wake-up priority"
1373         depends on PM_BFIN_WAKE_PD06
1374         default 0
1375         help
1376           Wake-Up priority 0(low) 1(high)
1377
1378 config PM_BFIN_WAKE_PE12
1379         bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
1380         depends on PM && BF60x
1381         default n
1382         help
1383           Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
1384
1385 config PM_BFIN_WAKE_PE12_POL
1386         int "Wake-up priority"
1387         depends on PM_BFIN_WAKE_PE12
1388         default 0
1389         help
1390           Wake-Up priority 0(low) 1(high)
1391
1392 config PM_BFIN_WAKE_PG04
1393         bool "Allow Wake-Up from PG04(CAN0_RX)"
1394         depends on PM && BF60x
1395         default n
1396         help
1397           Enable PG04(CAN0_RX) Wake-up
1398
1399 config PM_BFIN_WAKE_PG04_POL
1400         int "Wake-up priority"
1401         depends on PM_BFIN_WAKE_PG04
1402         default 0
1403         help
1404           Wake-Up priority 0(low) 1(high)
1405
1406 config PM_BFIN_WAKE_PG13
1407         bool "Allow Wake-Up from PG13"
1408         depends on PM && BF60x
1409         default n
1410         help
1411           Enable PG13 Wake-Up
1412
1413 config PM_BFIN_WAKE_PG13_POL
1414         int "Wake-up priority"
1415         depends on PM_BFIN_WAKE_PG13
1416         default 0
1417         help
1418           Wake-Up priority 0(low) 1(high)
1419
1420 config PM_BFIN_WAKE_USB
1421         bool "Allow Wake-Up from (USB)"
1422         depends on PM && BF60x
1423         default n
1424         help
1425           Enable (USB) Wake-up
1426
1427 config PM_BFIN_WAKE_USB_POL
1428         int "Wake-up priority"
1429         depends on PM_BFIN_WAKE_USB
1430         default 0
1431         help
1432           Wake-Up priority 0(low) 1(high)
1433
1434 endmenu
1435
1436 menu "CPU Frequency scaling"
1437
1438 source "drivers/cpufreq/Kconfig"
1439
1440 config BFIN_CPU_FREQ
1441         bool
1442         depends on CPU_FREQ
1443         select CPU_FREQ_TABLE
1444         default y
1445
1446 config CPU_VOLTAGE
1447         bool "CPU Voltage scaling"
1448         depends on CPU_FREQ
1449         default n
1450         help
1451           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1452           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1453           manuals. There is a theoretical risk that during VDDINT transitions
1454           the PLL may unlock.
1455
1456 endmenu
1457
1458 source "net/Kconfig"
1459
1460 source "drivers/Kconfig"
1461
1462 source "drivers/firmware/Kconfig"
1463
1464 source "fs/Kconfig"
1465
1466 source "arch/blackfin/Kconfig.debug"
1467
1468 source "security/Kconfig"
1469
1470 source "crypto/Kconfig"
1471
1472 source "lib/Kconfig"