7 config RWSEM_GENERIC_SPINLOCK
10 config RWSEM_XCHGADD_ALGORITHM
16 select HAVE_ARCH_TRACEHOOK
17 select HAVE_DYNAMIC_FTRACE
18 select HAVE_FTRACE_MCOUNT_RECORD
19 select HAVE_FUNCTION_GRAPH_TRACER
20 select HAVE_FUNCTION_TRACER
21 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
23 select HAVE_KERNEL_GZIP if RAMKERNEL
24 select HAVE_KERNEL_BZIP2 if RAMKERNEL
25 select HAVE_KERNEL_LZMA if RAMKERNEL
26 select HAVE_KERNEL_LZO if RAMKERNEL
28 select HAVE_PERF_EVENTS
29 select ARCH_HAVE_CUSTOM_GPIO_H
30 select ARCH_REQUIRE_GPIOLIB
32 select HAVE_UNDERSCORE_SYMBOL_PREFIX
34 select ARCH_WANT_IPC_PARSE_VERSION
35 select GENERIC_ATOMIC64
36 select GENERIC_IRQ_PROBE
37 select USE_GENERIC_SMP_HELPERS if SMP
38 select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
39 select GENERIC_SMP_IDLE_THREAD
40 select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
41 select HAVE_MOD_ARCH_SPECIFIC
42 select MODULES_USE_ELF_RELA
43 select HAVE_DEBUG_STACKOVERFLOW
55 config FORCE_MAX_ZONEORDER
59 config GENERIC_CALIBRATE_DELAY
62 config LOCKDEP_SUPPORT
65 config STACKTRACE_SUPPORT
68 config TRACE_IRQFLAGS_SUPPORT
73 source "kernel/Kconfig.preempt"
75 source "kernel/Kconfig.freezer"
77 menu "Blackfin Processor Options"
79 comment "Processor and Board Settings"
88 BF512 Processor Support.
93 BF514 Processor Support.
98 BF516 Processor Support.
103 BF518 Processor Support.
108 BF522 Processor Support.
113 BF523 Processor Support.
118 BF524 Processor Support.
123 BF525 Processor Support.
128 BF526 Processor Support.
133 BF527 Processor Support.
138 BF531 Processor Support.
143 BF532 Processor Support.
148 BF533 Processor Support.
153 BF534 Processor Support.
158 BF536 Processor Support.
163 BF537 Processor Support.
168 BF538 Processor Support.
173 BF539 Processor Support.
178 BF542 Processor Support.
183 BF542 Processor Support.
188 BF544 Processor Support.
193 BF544 Processor Support.
198 BF547 Processor Support.
203 BF547 Processor Support.
208 BF548 Processor Support.
213 BF548 Processor Support.
218 BF549 Processor Support.
223 BF549 Processor Support.
228 BF561 Processor Support.
234 BF609 Processor Support.
240 select TICKSOURCE_CORETMR
241 bool "Symmetric multi-processing support"
243 This enables support for systems with more than one CPU,
244 like the dual core BF561. If you have a system with only one
245 CPU, say N. If you have a system with more than one CPU, say Y.
247 If you don't know what to do here, say N.
255 bool "Support for hot-pluggable CPUs"
261 default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
262 default 2 if (BF537 || BF536 || BF534)
263 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
264 default 4 if (BF538 || BF539)
268 default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
269 default 3 if (BF537 || BF536 || BF534 || BF54xM)
270 default 5 if (BF561 || BF538 || BF539)
271 default 6 if (BF533 || BF532 || BF531)
275 default BF_REV_0_0 if (BF51x || BF52x || BF60x)
276 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
277 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
281 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
285 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
289 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
293 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
297 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x)
301 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
305 depends on (BF533 || BF532 || BF531)
317 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
322 depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561)
326 depends on BF54x || BF60x
328 config MEM_MT48LC64M4A2FB_7E
330 depends on (BFIN533_STAMP)
333 config MEM_MT48LC16M16A2TG_75
335 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
336 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
337 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
338 || BFIN527_BLUETECHNIX_CM)
341 config MEM_MT48LC32M8A2_75
343 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
346 config MEM_MT48LC8M32B2B5_7
348 depends on (BFIN561_BLUETECHNIX_CM)
351 config MEM_MT48LC32M16A2TG_75
353 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
356 config MEM_MT48H32M16LFCJ_75
358 depends on (BFIN526_EZBRD)
361 config MEM_MT47H64M16
363 depends on (BFIN609_EZKIT)
366 source "arch/blackfin/mach-bf518/Kconfig"
367 source "arch/blackfin/mach-bf527/Kconfig"
368 source "arch/blackfin/mach-bf533/Kconfig"
369 source "arch/blackfin/mach-bf561/Kconfig"
370 source "arch/blackfin/mach-bf537/Kconfig"
371 source "arch/blackfin/mach-bf538/Kconfig"
372 source "arch/blackfin/mach-bf548/Kconfig"
373 source "arch/blackfin/mach-bf609/Kconfig"
375 menu "Board customizations"
378 bool "Default bootloader kernel arguments"
381 string "Initial kernel command string"
382 depends on CMDLINE_BOOL
383 default "console=ttyBF0,57600"
385 If you don't have a boot loader capable of passing a command line string
386 to the kernel, you may specify one here. As a minimum, you should specify
387 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
390 hex "Kernel load address for booting"
392 range 0x1000 0x20000000
394 This option allows you to set the load address of the kernel.
395 This can be useful if you are on a board which has a small amount
396 of memory or you wish to reserve some memory at the beginning of
399 Note that you need to keep this value above 4k (0x1000) as this
400 memory region is used to capture NULL pointer references as well
401 as some core kernel functions.
403 config PHY_RAM_BASE_ADDRESS
404 hex "Physical RAM Base"
407 set BF609 FPGA physical SRAM base address
410 hex "Kernel ROM Base"
413 range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
414 range 0x20000000 0x30000000 if (BF54x || BF561)
415 range 0xB0000000 0xC0000000 if (BF60x)
417 Make sure your ROM base does not include any file-header
418 information that is prepended to the kernel.
420 For example, the bootable U-Boot format (created with
421 mkimage) has a 64 byte header (0x40). So while the image
422 you write to flash might start at say 0x20080000, you have
423 to add 0x40 to get the kernel's ROM base as it will come
426 comment "Clock/PLL Setup"
429 int "Frequency of the crystal on the board in Hz"
430 default "10000000" if BFIN532_IP0X
431 default "11059200" if BFIN533_STAMP
432 default "24576000" if PNAV10
433 default "25000000" # most people use this
434 default "27000000" if BFIN533_EZKIT
435 default "30000000" if BFIN561_EZKIT
436 default "24000000" if BFIN527_AD7160EVAL
438 The frequency of CLKIN crystal oscillator on the board in Hz.
439 Warning: This value should match the crystal on the board. Otherwise,
440 peripherals won't work properly.
442 config BFIN_KERNEL_CLOCK
443 bool "Re-program Clocks while Kernel boots?"
446 This option decides if kernel clocks are re-programed from the
447 bootloader settings. If the clocks are not set, the SDRAM settings
448 are also not changed, and the Bootloader does 100% of the hardware
453 depends on BFIN_KERNEL_CLOCK && (!BF60x)
458 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
461 If this is set the clock will be divided by 2, before it goes to the PLL.
465 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
467 default "22" if BFIN533_EZKIT
468 default "45" if BFIN533_STAMP
469 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
470 default "22" if BFIN533_BLUETECHNIX_CM
471 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
472 default "20" if (BFIN561_EZKIT || BF609)
473 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
474 default "25" if BFIN527_AD7160EVAL
476 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
477 PLL Frequency = (Crystal Frequency) * (this setting)
480 prompt "Core Clock Divider"
481 depends on BFIN_KERNEL_CLOCK
484 This sets the frequency of the core. It can be 1, 2, 4 or 8
485 Core Frequency = (PLL frequency) / (this setting)
501 int "System Clock Divider"
502 depends on BFIN_KERNEL_CLOCK
506 This sets the frequency of the system clock (including SDRAM or DDR) on
507 !BF60x else it set the clock for system buses and provides the
508 source from which SCLK0 and SCLK1 are derived.
509 This can be between 1 and 15
510 System Clock = (PLL frequency) / (this setting)
513 int "System Clock0 Divider"
514 depends on BFIN_KERNEL_CLOCK && BF60x
518 This sets the frequency of the system clock0 for PVP and all other
519 peripherals not clocked by SCLK1.
520 This can be between 1 and 15
521 System Clock0 = (System Clock) / (this setting)
524 int "System Clock1 Divider"
525 depends on BFIN_KERNEL_CLOCK && BF60x
529 This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
530 This can be between 1 and 15
531 System Clock1 = (System Clock) / (this setting)
534 int "DDR Clock Divider"
535 depends on BFIN_KERNEL_CLOCK && BF60x
539 This sets the frequency of the DDR memory.
540 This can be between 1 and 15
541 DDR Clock = (PLL frequency) / (this setting)
544 prompt "DDR SDRAM Chip Type"
545 depends on BFIN_KERNEL_CLOCK
547 default MEM_MT46V32M16_5B
549 config MEM_MT46V32M16_6T
552 config MEM_MT46V32M16_5B
557 prompt "DDR/SDRAM Timing"
558 depends on BFIN_KERNEL_CLOCK && !BF60x
559 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
561 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
562 The calculated SDRAM timing parameters may not be 100%
563 accurate - This option is therefore marked experimental.
565 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
566 bool "Calculate Timings"
568 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
569 bool "Provide accurate Timings based on target SCLK"
571 Please consult the Blackfin Hardware Reference Manuals as well
572 as the memory device datasheet.
573 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
576 menu "Memory Init Control"
577 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
594 config MEM_EBIU_DDRQUE
611 # Max & Min Speeds for various Chips
615 default 400000000 if BF512
616 default 400000000 if BF514
617 default 400000000 if BF516
618 default 400000000 if BF518
619 default 400000000 if BF522
620 default 600000000 if BF523
621 default 400000000 if BF524
622 default 600000000 if BF525
623 default 400000000 if BF526
624 default 600000000 if BF527
625 default 400000000 if BF531
626 default 400000000 if BF532
627 default 750000000 if BF533
628 default 500000000 if BF534
629 default 400000000 if BF536
630 default 600000000 if BF537
631 default 533333333 if BF538
632 default 533333333 if BF539
633 default 600000000 if BF542
634 default 533333333 if BF544
635 default 600000000 if BF547
636 default 600000000 if BF548
637 default 533333333 if BF549
638 default 600000000 if BF561
639 default 800000000 if BF609
647 default 200000000 if BF609
654 comment "Kernel Timer/Scheduler"
656 source kernel/Kconfig.hz
658 config SET_GENERIC_CLOCKEVENTS
659 bool "Generic clock events"
661 select GENERIC_CLOCKEVENTS
663 menu "Clock event device"
664 depends on GENERIC_CLOCKEVENTS
665 config TICKSOURCE_GPTMR0
670 config TICKSOURCE_CORETMR
676 depends on GENERIC_CLOCKEVENTS
677 config CYCLES_CLOCKSOURCE
680 depends on !BFIN_SCRATCH_REG_CYCLES
683 If you say Y here, you will enable support for using the 'cycles'
684 registers as a clock source. Doing so means you will be unable to
685 safely write to the 'cycles' register during runtime. You will
686 still be able to read it (such as for performance monitoring), but
687 writing the registers will most likely crash the kernel.
689 config GPTMR0_CLOCKSOURCE
692 depends on !TICKSOURCE_GPTMR0
698 prompt "Blackfin Exception Scratch Register"
699 default BFIN_SCRATCH_REG_RETN
701 Select the resource to reserve for the Exception handler:
702 - RETN: Non-Maskable Interrupt (NMI)
703 - RETE: Exception Return (JTAG/ICE)
704 - CYCLES: Performance counter
706 If you are unsure, please select "RETN".
708 config BFIN_SCRATCH_REG_RETN
711 Use the RETN register in the Blackfin exception handler
712 as a stack scratch register. This means you cannot
713 safely use NMI on the Blackfin while running Linux, but
714 you can debug the system with a JTAG ICE and use the
715 CYCLES performance registers.
717 If you are unsure, please select "RETN".
719 config BFIN_SCRATCH_REG_RETE
722 Use the RETE register in the Blackfin exception handler
723 as a stack scratch register. This means you cannot
724 safely use a JTAG ICE while debugging a Blackfin board,
725 but you can safely use the CYCLES performance registers
728 If you are unsure, please select "RETN".
730 config BFIN_SCRATCH_REG_CYCLES
733 Use the CYCLES register in the Blackfin exception handler
734 as a stack scratch register. This means you cannot
735 safely use the CYCLES performance registers on a Blackfin
736 board at anytime, but you can debug the system with a JTAG
739 If you are unsure, please select "RETN".
746 menu "Blackfin Kernel Optimizations"
748 comment "Memory Optimizations"
751 bool "Locate interrupt entry code in L1 Memory"
755 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
756 into L1 instruction memory. (less latency)
758 config EXCPT_IRQ_SYSC_L1
759 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
763 If enabled, the entire ASM lowlevel exception and interrupt entry code
764 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
768 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
772 If enabled, the frequently called do_irq dispatcher function is linked
773 into L1 instruction memory. (less latency)
775 config CORE_TIMER_IRQ_L1
776 bool "Locate frequently called timer_interrupt() function in L1 Memory"
780 If enabled, the frequently called timer_interrupt() function is linked
781 into L1 instruction memory. (less latency)
784 bool "Locate frequently idle function in L1 Memory"
788 If enabled, the frequently called idle function is linked
789 into L1 instruction memory. (less latency)
792 bool "Locate kernel schedule function in L1 Memory"
796 If enabled, the frequently called kernel schedule is linked
797 into L1 instruction memory. (less latency)
799 config ARITHMETIC_OPS_L1
800 bool "Locate kernel owned arithmetic functions in L1 Memory"
804 If enabled, arithmetic functions are linked
805 into L1 instruction memory. (less latency)
808 bool "Locate access_ok function in L1 Memory"
812 If enabled, the access_ok function is linked
813 into L1 instruction memory. (less latency)
816 bool "Locate memset function in L1 Memory"
820 If enabled, the memset function is linked
821 into L1 instruction memory. (less latency)
824 bool "Locate memcpy function in L1 Memory"
828 If enabled, the memcpy function is linked
829 into L1 instruction memory. (less latency)
832 bool "locate strcmp function in L1 Memory"
836 If enabled, the strcmp function is linked
837 into L1 instruction memory (less latency).
840 bool "locate strncmp function in L1 Memory"
844 If enabled, the strncmp function is linked
845 into L1 instruction memory (less latency).
848 bool "locate strcpy function in L1 Memory"
852 If enabled, the strcpy function is linked
853 into L1 instruction memory (less latency).
856 bool "locate strncpy function in L1 Memory"
860 If enabled, the strncpy function is linked
861 into L1 instruction memory (less latency).
863 config SYS_BFIN_SPINLOCK_L1
864 bool "Locate sys_bfin_spinlock function in L1 Memory"
868 If enabled, sys_bfin_spinlock function is linked
869 into L1 instruction memory. (less latency)
871 config IP_CHECKSUM_L1
872 bool "Locate IP Checksum function in L1 Memory"
876 If enabled, the IP Checksum function is linked
877 into L1 instruction memory. (less latency)
879 config CACHELINE_ALIGNED_L1
880 bool "Locate cacheline_aligned data to L1 Data Memory"
883 depends on !SMP && !BF531 && !CRC32
885 If enabled, cacheline_aligned data is linked
886 into L1 data memory. (less latency)
888 config SYSCALL_TAB_L1
889 bool "Locate Syscall Table L1 Data Memory"
891 depends on !SMP && !BF531
893 If enabled, the Syscall LUT is linked
894 into L1 data memory. (less latency)
896 config CPLB_SWITCH_TAB_L1
897 bool "Locate CPLB Switch Tables L1 Data Memory"
899 depends on !SMP && !BF531
901 If enabled, the CPLB Switch Tables are linked
902 into L1 data memory. (less latency)
904 config ICACHE_FLUSH_L1
905 bool "Locate icache flush funcs in L1 Inst Memory"
908 If enabled, the Blackfin icache flushing functions are linked
909 into L1 instruction memory.
911 Note that this might be required to address anomalies, but
912 these functions are pretty small, so it shouldn't be too bad.
913 If you are using a processor affected by an anomaly, the build
914 system will double check for you and prevent it.
916 config DCACHE_FLUSH_L1
917 bool "Locate dcache flush funcs in L1 Inst Memory"
921 If enabled, the Blackfin dcache flushing functions are linked
922 into L1 instruction memory.
925 bool "Support locating application stack in L1 Scratch Memory"
929 If enabled the application stack can be located in L1
930 scratch memory (less latency).
932 Currently only works with FLAT binaries.
934 config EXCEPTION_L1_SCRATCH
935 bool "Locate exception stack in L1 Scratch Memory"
937 depends on !SMP && !APP_STACK_L1
939 Whenever an exception occurs, use the L1 Scratch memory for
940 stack storage. You cannot place the stacks of FLAT binaries
941 in L1 when using this option.
943 If you don't use L1 Scratch, then you should say Y here.
945 comment "Speed Optimizations"
946 config BFIN_INS_LOWOVERHEAD
947 bool "ins[bwl] low overhead, higher interrupt latency"
951 Reads on the Blackfin are speculative. In Blackfin terms, this means
952 they can be interrupted at any time (even after they have been issued
953 on to the external bus), and re-issued after the interrupt occurs.
954 For memory - this is not a big deal, since memory does not change if
957 If a FIFO is sitting on the end of the read, it will see two reads,
958 when the core only sees one since the FIFO receives both the read
959 which is cancelled (and not delivered to the core) and the one which
960 is re-issued (which is delivered to the core).
962 To solve this, interrupts are turned off before reads occur to
963 I/O space. This option controls which the overhead/latency of
964 controlling interrupts during this time
965 "n" turns interrupts off every read
966 (higher overhead, but lower interrupt latency)
967 "y" turns interrupts off every loop
968 (low overhead, but longer interrupt latency)
970 default behavior is to leave this set to on (type "Y"). If you are experiencing
971 interrupt latency issues, it is safe and OK to turn this off.
976 prompt "Kernel executes from"
978 Choose the memory type that the kernel will be running in.
983 The kernel will be resident in RAM when running.
988 The kernel will be resident in FLASH/ROM when running.
992 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
1000 config BFIN_GPTIMERS
1001 tristate "Enable Blackfin General Purpose Timers API"
1004 Enable support for the General Purpose Timers API. If you
1007 To compile this driver as a module, choose M here: the module
1008 will be called gptimers.
1011 prompt "Uncached DMA region"
1012 default DMA_UNCACHED_1M
1013 config DMA_UNCACHED_32M
1014 bool "Enable 32M DMA region"
1015 config DMA_UNCACHED_16M
1016 bool "Enable 16M DMA region"
1017 config DMA_UNCACHED_8M
1018 bool "Enable 8M DMA region"
1019 config DMA_UNCACHED_4M
1020 bool "Enable 4M DMA region"
1021 config DMA_UNCACHED_2M
1022 bool "Enable 2M DMA region"
1023 config DMA_UNCACHED_1M
1024 bool "Enable 1M DMA region"
1025 config DMA_UNCACHED_512K
1026 bool "Enable 512K DMA region"
1027 config DMA_UNCACHED_256K
1028 bool "Enable 256K DMA region"
1029 config DMA_UNCACHED_128K
1030 bool "Enable 128K DMA region"
1031 config DMA_UNCACHED_NONE
1032 bool "Disable DMA region"
1036 comment "Cache Support"
1039 bool "Enable ICACHE"
1041 config BFIN_EXTMEM_ICACHEABLE
1042 bool "Enable ICACHE for external memory"
1043 depends on BFIN_ICACHE
1045 config BFIN_L2_ICACHEABLE
1046 bool "Enable ICACHE for L2 SRAM"
1047 depends on BFIN_ICACHE
1048 depends on (BF54x || BF561 || BF60x) && !SMP
1052 bool "Enable DCACHE"
1054 config BFIN_DCACHE_BANKA
1055 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1056 depends on BFIN_DCACHE && !BF531
1058 config BFIN_EXTMEM_DCACHEABLE
1059 bool "Enable DCACHE for external memory"
1060 depends on BFIN_DCACHE
1063 prompt "External memory DCACHE policy"
1064 depends on BFIN_EXTMEM_DCACHEABLE
1065 default BFIN_EXTMEM_WRITEBACK if !SMP
1066 default BFIN_EXTMEM_WRITETHROUGH if SMP
1067 config BFIN_EXTMEM_WRITEBACK
1072 Cached data will be written back to SDRAM only when needed.
1073 This can give a nice increase in performance, but beware of
1074 broken drivers that do not properly invalidate/flush their
1077 Write Through Policy:
1078 Cached data will always be written back to SDRAM when the
1079 cache is updated. This is a completely safe setting, but
1080 performance is worse than Write Back.
1082 If you are unsure of the options and you want to be safe,
1083 then go with Write Through.
1085 config BFIN_EXTMEM_WRITETHROUGH
1086 bool "Write through"
1089 Cached data will be written back to SDRAM only when needed.
1090 This can give a nice increase in performance, but beware of
1091 broken drivers that do not properly invalidate/flush their
1094 Write Through Policy:
1095 Cached data will always be written back to SDRAM when the
1096 cache is updated. This is a completely safe setting, but
1097 performance is worse than Write Back.
1099 If you are unsure of the options and you want to be safe,
1100 then go with Write Through.
1104 config BFIN_L2_DCACHEABLE
1105 bool "Enable DCACHE for L2 SRAM"
1106 depends on BFIN_DCACHE
1107 depends on (BF54x || BF561 || BF60x) && !SMP
1110 prompt "L2 SRAM DCACHE policy"
1111 depends on BFIN_L2_DCACHEABLE
1112 default BFIN_L2_WRITEBACK
1113 config BFIN_L2_WRITEBACK
1116 config BFIN_L2_WRITETHROUGH
1117 bool "Write through"
1121 comment "Memory Protection Unit"
1123 bool "Enable the memory protection unit"
1126 Use the processor's MPU to protect applications from accessing
1127 memory they do not own. This comes at a performance penalty
1128 and is recommended only for debugging.
1130 comment "Asynchronous Memory Configuration"
1132 menu "EBIU_AMGCTL Global Control"
1135 bool "Enable CLKOUT"
1139 bool "DMA has priority over core for ext. accesses"
1144 bool "Bank 0 16 bit packing enable"
1149 bool "Bank 1 16 bit packing enable"
1154 bool "Bank 2 16 bit packing enable"
1159 bool "Bank 3 16 bit packing enable"
1163 prompt "Enable Asynchronous Memory Banks"
1167 bool "Disable All Banks"
1170 bool "Enable Bank 0"
1172 config C_AMBEN_B0_B1
1173 bool "Enable Bank 0 & 1"
1175 config C_AMBEN_B0_B1_B2
1176 bool "Enable Bank 0 & 1 & 2"
1179 bool "Enable All Banks"
1183 menu "EBIU_AMBCTL Control"
1186 hex "Bank 0 (AMBCTL0.L)"
1189 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1190 used to control the Asynchronous Memory Bank 0 settings.
1193 hex "Bank 1 (AMBCTL0.H)"
1195 default 0x5558 if BF54x
1197 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1198 used to control the Asynchronous Memory Bank 1 settings.
1201 hex "Bank 2 (AMBCTL1.L)"
1204 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1205 used to control the Asynchronous Memory Bank 2 settings.
1208 hex "Bank 3 (AMBCTL1.H)"
1211 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1212 used to control the Asynchronous Memory Bank 3 settings.
1216 config EBIU_MBSCTLVAL
1217 hex "EBIU Bank Select Control Register"
1222 hex "Flash Memory Mode Control Register"
1227 hex "Flash Memory Bank Control Register"
1232 #############################################################################
1233 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1239 Support for PCI bus.
1241 source "drivers/pci/Kconfig"
1243 source "drivers/pcmcia/Kconfig"
1245 source "drivers/pci/hotplug/Kconfig"
1249 menu "Executable file formats"
1251 source "fs/Kconfig.binfmt"
1255 menu "Power management options"
1257 source "kernel/power/Kconfig"
1259 config ARCH_SUSPEND_POSSIBLE
1263 prompt "Standby Power Saving Mode"
1264 depends on PM && !BF60x
1265 default PM_BFIN_SLEEP_DEEPER
1266 config PM_BFIN_SLEEP_DEEPER
1269 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1270 power dissipation by disabling the clock to the processor core (CCLK).
1271 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1272 to 0.85 V to provide the greatest power savings, while preserving the
1274 The PLL and system clock (SCLK) continue to operate at a very low
1275 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1276 the SDRAM is put into Self Refresh Mode. Typically an external event
1277 such as GPIO interrupt or RTC activity wakes up the processor.
1278 Various Peripherals such as UART, SPORT, PPI may not function as
1279 normal during Sleep Deeper, due to the reduced SCLK frequency.
1280 When in the sleep mode, system DMA access to L1 memory is not supported.
1282 If unsure, select "Sleep Deeper".
1284 config PM_BFIN_SLEEP
1287 Sleep Mode (High Power Savings) - The sleep mode reduces power
1288 dissipation by disabling the clock to the processor core (CCLK).
1289 The PLL and system clock (SCLK), however, continue to operate in
1290 this mode. Typically an external event or RTC activity will wake
1291 up the processor. When in the sleep mode, system DMA access to L1
1292 memory is not supported.
1294 If unsure, select "Sleep Deeper".
1297 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1300 config PM_BFIN_WAKE_PH6
1301 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1302 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1305 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1307 config PM_BFIN_WAKE_GP
1308 bool "Allow Wake-Up from GPIOs"
1309 depends on PM && BF54x
1312 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1313 (all processors, except ADSP-BF549). This option sets
1314 the general-purpose wake-up enable (GPWE) control bit to enable
1315 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1316 On ADSP-BF549 this option enables the same functionality on the
1317 /MRXON pin also PH7.
1319 config PM_BFIN_WAKE_PA15
1320 bool "Allow Wake-Up from PA15"
1321 depends on PM && BF60x
1326 config PM_BFIN_WAKE_PA15_POL
1327 int "Wake-up priority"
1328 depends on PM_BFIN_WAKE_PA15
1331 Wake-Up priority 0(low) 1(high)
1333 config PM_BFIN_WAKE_PB15
1334 bool "Allow Wake-Up from PB15"
1335 depends on PM && BF60x
1340 config PM_BFIN_WAKE_PB15_POL
1341 int "Wake-up priority"
1342 depends on PM_BFIN_WAKE_PB15
1345 Wake-Up priority 0(low) 1(high)
1347 config PM_BFIN_WAKE_PC15
1348 bool "Allow Wake-Up from PC15"
1349 depends on PM && BF60x
1354 config PM_BFIN_WAKE_PC15_POL
1355 int "Wake-up priority"
1356 depends on PM_BFIN_WAKE_PC15
1359 Wake-Up priority 0(low) 1(high)
1361 config PM_BFIN_WAKE_PD06
1362 bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
1363 depends on PM && BF60x
1366 Enable PD06(ETH0_PHYINT) Wake-up
1368 config PM_BFIN_WAKE_PD06_POL
1369 int "Wake-up priority"
1370 depends on PM_BFIN_WAKE_PD06
1373 Wake-Up priority 0(low) 1(high)
1375 config PM_BFIN_WAKE_PE12
1376 bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
1377 depends on PM && BF60x
1380 Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
1382 config PM_BFIN_WAKE_PE12_POL
1383 int "Wake-up priority"
1384 depends on PM_BFIN_WAKE_PE12
1387 Wake-Up priority 0(low) 1(high)
1389 config PM_BFIN_WAKE_PG04
1390 bool "Allow Wake-Up from PG04(CAN0_RX)"
1391 depends on PM && BF60x
1394 Enable PG04(CAN0_RX) Wake-up
1396 config PM_BFIN_WAKE_PG04_POL
1397 int "Wake-up priority"
1398 depends on PM_BFIN_WAKE_PG04
1401 Wake-Up priority 0(low) 1(high)
1403 config PM_BFIN_WAKE_PG13
1404 bool "Allow Wake-Up from PG13"
1405 depends on PM && BF60x
1410 config PM_BFIN_WAKE_PG13_POL
1411 int "Wake-up priority"
1412 depends on PM_BFIN_WAKE_PG13
1415 Wake-Up priority 0(low) 1(high)
1417 config PM_BFIN_WAKE_USB
1418 bool "Allow Wake-Up from (USB)"
1419 depends on PM && BF60x
1422 Enable (USB) Wake-up
1424 config PM_BFIN_WAKE_USB_POL
1425 int "Wake-up priority"
1426 depends on PM_BFIN_WAKE_USB
1429 Wake-Up priority 0(low) 1(high)
1433 menu "CPU Frequency scaling"
1435 source "drivers/cpufreq/Kconfig"
1437 config BFIN_CPU_FREQ
1440 select CPU_FREQ_TABLE
1444 bool "CPU Voltage scaling"
1448 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1449 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1450 manuals. There is a theoretical risk that during VDDINT transitions
1455 source "net/Kconfig"
1457 source "drivers/Kconfig"
1459 source "drivers/firmware/Kconfig"
1463 source "arch/blackfin/Kconfig.debug"
1465 source "security/Kconfig"
1467 source "crypto/Kconfig"
1469 source "lib/Kconfig"