arch/blackfin/Kconfig

   1 #
   2 # For a description of the syntax of this configuration file,
   3 # see Documentation/kbuild/kconfig-language.txt.
   4 #
   5
   6 mainmenu "Blackfin Kernel Configuration"
   7
   8 config MMU
   9         bool
  10         default n
  11
  12 config FPU
  13         bool
  14         default n
  15
  16 config RWSEM_GENERIC_SPINLOCK
  17         bool
  18         default y
  19
  20 config RWSEM_XCHGADD_ALGORITHM
  21         bool
  22         default n
  23
  24 config BLACKFIN
  25         bool
  26         default y
  27         select HAVE_IDE
  28         select HAVE_OPROFILE
  29
  30 config ZONE_DMA
  31         bool
  32         default y
  33
  34 config GENERIC_FIND_NEXT_BIT
  35         bool
  36         default y
  37
  38 config GENERIC_HWEIGHT
  39         bool
  40         default y
  41
  42 config GENERIC_HARDIRQS
  43         bool
  44         default y
  45
  46 config GENERIC_IRQ_PROBE
  47         bool
  48         default y
  49
  50 config GENERIC_GPIO
  51         bool
  52         default y
  53
  54 config FORCE_MAX_ZONEORDER
  55         int
  56         default "14"
  57
  58 config GENERIC_CALIBRATE_DELAY
  59         bool
  60         default y
  61
  62 config HARDWARE_PM
  63         def_bool y
  64         depends on OPROFILE
  65
  66 source "init/Kconfig"
  67 source "kernel/Kconfig.preempt"
  68
  69 menu "Blackfin Processor Options"
  70
  71 comment "Processor and Board Settings"
  72
  73 choice
  74         prompt "CPU"
  75         default BF533
  76
  77 config BF522
  78         bool "BF522"
  79         help
  80           BF522 Processor Support.
  81
  82 config BF523
  83         bool "BF523"
  84         help
  85           BF523 Processor Support.
  86
  87 config BF524
  88         bool "BF524"
  89         help
  90           BF524 Processor Support.
  91
  92 config BF525
  93         bool "BF525"
  94         help
  95           BF525 Processor Support.
  96
  97 config BF526
  98         bool "BF526"
  99         help
 100           BF526 Processor Support.
 101
 102 config BF527
 103         bool "BF527"
 104         help
 105           BF527 Processor Support.
 106
 107 config BF531
 108         bool "BF531"
 109         help
 110           BF531 Processor Support.
 111
 112 config BF532
 113         bool "BF532"
 114         help
 115           BF532 Processor Support.
 116
 117 config BF533
 118         bool "BF533"
 119         help
 120           BF533 Processor Support.
 121
 122 config BF534
 123         bool "BF534"
 124         help
 125           BF534 Processor Support.
 126
 127 config BF536
 128         bool "BF536"
 129         help
 130           BF536 Processor Support.
 131
 132 config BF537
 133         bool "BF537"
 134         help
 135           BF537 Processor Support.
 136
 137 config BF542
 138         bool "BF542"
 139         help
 140           BF542 Processor Support.
 141
 142 config BF544
 143         bool "BF544"
 144         help
 145           BF544 Processor Support.
 146
 147 config BF547
 148         bool "BF547"
 149         help
 150           BF547 Processor Support.
 151
 152 config BF548
 153         bool "BF548"
 154         help
 155           BF548 Processor Support.
 156
 157 config BF549
 158         bool "BF549"
 159         help
 160           BF549 Processor Support.
 161
 162 config BF561
 163         bool "BF561"
 164         help
 165           Not Supported Yet - Work in progress - BF561 Processor Support.
 166
 167 endchoice
 168
 169 choice
 170         prompt "Silicon Rev"
 171         default BF_REV_0_1 if BF527
 172         default BF_REV_0_2 if BF537
 173         default BF_REV_0_3 if BF533
 174         default BF_REV_0_0 if BF549
 175
 176 config BF_REV_0_0
 177         bool "0.0"
 178         depends on (BF52x || BF54x)
 179
 180 config BF_REV_0_1
 181         bool "0.1"
 182         depends on (BF52x || BF54x)
 183
 184 config BF_REV_0_2
 185         bool "0.2"
 186         depends on (BF537 || BF536 || BF534)
 187
 188 config BF_REV_0_3
 189         bool "0.3"
 190         depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 191
 192 config BF_REV_0_4
 193         bool "0.4"
 194         depends on (BF561 || BF533 || BF532 || BF531)
 195
 196 config BF_REV_0_5
 197         bool "0.5"
 198         depends on (BF561 || BF533 || BF532 || BF531)
 199
 200 config BF_REV_ANY
 201         bool "any"
 202
 203 config BF_REV_NONE
 204         bool "none"
 205
 206 endchoice
 207
 208 config BF52x
 209         bool
 210         depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
 211         default y
 212
 213 config BF53x
 214         bool
 215         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 216         default y
 217
 218 config BF54x
 219         bool
 220         depends on (BF542 || BF544 || BF547 || BF548 || BF549)
 221         default y
 222
 223 config MEM_GENERIC_BOARD
 224         bool
 225         depends on GENERIC_BOARD
 226         default y
 227
 228 config MEM_MT48LC64M4A2FB_7E
 229         bool
 230         depends on (BFIN533_STAMP)
 231         default y
 232
 233 config MEM_MT48LC16M16A2TG_75
 234         bool
 235         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 236                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
 237                 || H8606_HVSISTEMAS)
 238         default y
 239
 240 config MEM_MT48LC32M8A2_75
 241         bool
 242         depends on (BFIN537_STAMP || PNAV10)
 243         default y
 244
 245 config MEM_MT48LC8M32B2B5_7
 246         bool
 247         depends on (BFIN561_BLUETECHNIX_CM)
 248         default y
 249
 250 config MEM_MT48LC32M16A2TG_75
 251         bool
 252         depends on (BFIN527_EZKIT || BFIN532_IP0X)
 253         default y
 254
 255 source "arch/blackfin/mach-bf527/Kconfig"
 256 source "arch/blackfin/mach-bf533/Kconfig"
 257 source "arch/blackfin/mach-bf561/Kconfig"
 258 source "arch/blackfin/mach-bf537/Kconfig"
 259 source "arch/blackfin/mach-bf548/Kconfig"
 260
 261 menu "Board customizations"
 262
 263 config CMDLINE_BOOL
 264         bool "Default bootloader kernel arguments"
 265
 266 config CMDLINE
 267         string "Initial kernel command string"
 268         depends on CMDLINE_BOOL
 269         default "console=ttyBF0,57600"
 270         help
 271           If you don't have a boot loader capable of passing a command line string
 272           to the kernel, you may specify one here. As a minimum, you should specify
 273           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 274
 275 config BOOT_LOAD
 276         hex "Kernel load address for booting"
 277         default "0x1000"
 278         range 0x1000 0x20000000
 279         help
 280           This option allows you to set the load address of the kernel.
 281           This can be useful if you are on a board which has a small amount
 282           of memory or you wish to reserve some memory at the beginning of
 283           the address space.
 284
 285           Note that you need to keep this value above 4k (0x1000) as this
 286           memory region is used to capture NULL pointer references as well
 287           as some core kernel functions.
 288
 289 comment "Clock/PLL Setup"
 290
 291 config CLKIN_HZ
 292         int "Frequency of the crystal on the board in Hz"
 293         default "11059200" if BFIN533_STAMP
 294         default "27000000" if BFIN533_EZKIT
 295         default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
 296         default "30000000" if BFIN561_EZKIT
 297         default "24576000" if PNAV10
 298         default "10000000" if BFIN532_IP0X
 299         help
 300           The frequency of CLKIN crystal oscillator on the board in Hz.
 301           Warning: This value should match the crystal on the board. Otherwise,
 302           peripherals won't work properly.
 303
 304 config BFIN_KERNEL_CLOCK
 305         bool "Re-program Clocks while Kernel boots?"
 306         default n
 307         help
 308           This option decides if kernel clocks are re-programed from the
 309           bootloader settings. If the clocks are not set, the SDRAM settings
 310           are also not changed, and the Bootloader does 100% of the hardware
 311           configuration.
 312
 313 config MEM_SIZE
 314         int "SDRAM Memory Size in MBytes"
 315         depends on BFIN_KERNEL_CLOCK
 316         default 64
 317
 318 config MEM_ADD_WIDTH
 319         int "Memory Address Width"
 320         depends on BFIN_KERNEL_CLOCK
 321         depends on (!BF54x)
 322         range 8 11
 323         default  9 if BFIN533_EZKIT
 324         default  9 if BFIN561_EZKIT
 325         default  9 if H8606_HVSISTEMAS
 326         default 10 if BFIN527_EZKIT
 327         default 10 if BFIN537_STAMP
 328         default 11 if BFIN533_STAMP
 329         default 10 if PNAV10
 330         default 10 if BFIN532_IP0X
 331
 332 config PLL_BYPASS
 333         bool "Bypass PLL"
 334         depends on BFIN_KERNEL_CLOCK
 335         default n
 336
 337 config CLKIN_HALF
 338         bool "Half Clock In"
 339         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 340         default n
 341         help
 342           If this is set the clock will be divided by 2, before it goes to the PLL.
 343
 344 config VCO_MULT
 345         int "VCO Multiplier"
 346         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 347         range 1 64
 348         default "22" if BFIN533_EZKIT
 349         default "45" if BFIN533_STAMP
 350         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
 351         default "22" if BFIN533_BLUETECHNIX_CM
 352         default "20" if BFIN537_BLUETECHNIX_CM
 353         default "20" if BFIN561_BLUETECHNIX_CM
 354         default "20" if BFIN561_EZKIT
 355         default "16" if H8606_HVSISTEMAS
 356         help
 357           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 358           PLL Frequency = (Crystal Frequency) * (this setting)
 359
 360 choice
 361         prompt "Core Clock Divider"
 362         depends on BFIN_KERNEL_CLOCK
 363         default CCLK_DIV_1
 364         help
 365           This sets the frequency of the core. It can be 1, 2, 4 or 8
 366           Core Frequency = (PLL frequency) / (this setting)
 367
 368 config CCLK_DIV_1
 369         bool "1"
 370
 371 config CCLK_DIV_2
 372         bool "2"
 373
 374 config CCLK_DIV_4
 375         bool "4"
 376
 377 config CCLK_DIV_8
 378         bool "8"
 379 endchoice
 380
 381 config SCLK_DIV
 382         int "System Clock Divider"
 383         depends on BFIN_KERNEL_CLOCK
 384         range 1 15
 385         default 5
 386         help
 387           This sets the frequency of the system clock (including SDRAM or DDR).
 388           This can be between 1 and 15
 389           System Clock = (PLL frequency) / (this setting)
 390
 391 config MAX_MEM_SIZE
 392         int "Max SDRAM Memory Size in MBytes"
 393         depends on !BFIN_KERNEL_CLOCK && !MPU
 394         default 512
 395         help
 396           This is the max memory size that the kernel will create CPLB
 397           tables for.  Your system will not be able to handle any more.
 398
 399 choice
 400         prompt "DDR SDRAM Chip Type"
 401         depends on BFIN_KERNEL_CLOCK
 402         depends on BF54x
 403         default MEM_MT46V32M16_5B
 404
 405 config MEM_MT46V32M16_6T
 406         bool "MT46V32M16_6T"
 407
 408 config MEM_MT46V32M16_5B
 409         bool "MT46V32M16_5B"
 410 endchoice
 411
 412 #
 413 # Max & Min Speeds for various Chips
 414 #
 415 config MAX_VCO_HZ
 416         int
 417         default 600000000 if BF522
 418         default 400000000 if BF523
 419         default 400000000 if BF524
 420         default 600000000 if BF525
 421         default 400000000 if BF526
 422         default 600000000 if BF527
 423         default 400000000 if BF531
 424         default 400000000 if BF532
 425         default 750000000 if BF533
 426         default 500000000 if BF534
 427         default 400000000 if BF536
 428         default 600000000 if BF537
 429         default 533333333 if BF538
 430         default 533333333 if BF539
 431         default 600000000 if BF542
 432         default 533333333 if BF544
 433         default 600000000 if BF547
 434         default 600000000 if BF548
 435         default 533333333 if BF549
 436         default 600000000 if BF561
 437
 438 config MIN_VCO_HZ
 439         int
 440         default 50000000
 441
 442 config MAX_SCLK_HZ
 443         int
 444         default 133333333
 445
 446 config MIN_SCLK_HZ
 447         int
 448         default 27000000
 449
 450 comment "Kernel Timer/Scheduler"
 451
 452 source kernel/Kconfig.hz
 453
 454 config GENERIC_TIME
 455         bool "Generic time"
 456         default y
 457
 458 config GENERIC_CLOCKEVENTS
 459         bool "Generic clock events"
 460         depends on GENERIC_TIME
 461         default y
 462
 463 config CYCLES_CLOCKSOURCE
 464         bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
 465         depends on EXPERIMENTAL
 466         depends on GENERIC_CLOCKEVENTS
 467         depends on !BFIN_SCRATCH_REG_CYCLES
 468         default n
 469         help
 470           If you say Y here, you will enable support for using the 'cycles'
 471           registers as a clock source.  Doing so means you will be unable to
 472           safely write to the 'cycles' register during runtime.  You will
 473           still be able to read it (such as for performance monitoring), but
 474           writing the registers will most likely crash the kernel.
 475
 476 source kernel/time/Kconfig
 477
 478 comment "Memory Setup"
 479
 480 comment "Misc"
 481
 482 config ENET_FLASH_PIN
 483         int "PF port/pin used for flash and ethernet sharing"
 484         depends on (BFIN533_STAMP)
 485         default  0
 486         help
 487           PF port/pin used for flash and ethernet sharing to allow other PF
 488           pins to be used on other platforms without having to touch common
 489           code.
 490           For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc.
 491
 492 choice
 493         prompt "Blackfin Exception Scratch Register"
 494         default BFIN_SCRATCH_REG_RETN
 495         help
 496           Select the resource to reserve for the Exception handler:
 497             - RETN: Non-Maskable Interrupt (NMI)
 498             - RETE: Exception Return (JTAG/ICE)
 499             - CYCLES: Performance counter
 500
 501           If you are unsure, please select "RETN".
 502
 503 config BFIN_SCRATCH_REG_RETN
 504         bool "RETN"
 505         help
 506           Use the RETN register in the Blackfin exception handler
 507           as a stack scratch register.  This means you cannot
 508           safely use NMI on the Blackfin while running Linux, but
 509           you can debug the system with a JTAG ICE and use the
 510           CYCLES performance registers.
 511
 512           If you are unsure, please select "RETN".
 513
 514 config BFIN_SCRATCH_REG_RETE
 515         bool "RETE"
 516         help
 517           Use the RETE register in the Blackfin exception handler
 518           as a stack scratch register.  This means you cannot
 519           safely use a JTAG ICE while debugging a Blackfin board,
 520           but you can safely use the CYCLES performance registers
 521           and the NMI.
 522
 523           If you are unsure, please select "RETN".
 524
 525 config BFIN_SCRATCH_REG_CYCLES
 526         bool "CYCLES"
 527         help
 528           Use the CYCLES register in the Blackfin exception handler
 529           as a stack scratch register.  This means you cannot
 530           safely use the CYCLES performance registers on a Blackfin
 531           board at anytime, but you can debug the system with a JTAG
 532           ICE and use the NMI.
 533
 534           If you are unsure, please select "RETN".
 535
 536 endchoice
 537
 538 endmenu
 539
 540
 541 menu "Blackfin Kernel Optimizations"
 542
 543 comment "Memory Optimizations"
 544
 545 config I_ENTRY_L1
 546         bool "Locate interrupt entry code in L1 Memory"
 547         default y
 548         help
 549           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 550           into L1 instruction memory. (less latency)
 551
 552 config EXCPT_IRQ_SYSC_L1
 553         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 554         default y
 555         help
 556           If enabled, the entire ASM lowlevel exception and interrupt entry code
 557           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 558           (less latency)
 559
 560 config DO_IRQ_L1
 561         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 562         default y
 563         help
 564           If enabled, the frequently called do_irq dispatcher function is linked
 565           into L1 instruction memory. (less latency)
 566
 567 config CORE_TIMER_IRQ_L1
 568         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 569         default y
 570         help
 571           If enabled, the frequently called timer_interrupt() function is linked
 572           into L1 instruction memory. (less latency)
 573
 574 config IDLE_L1
 575         bool "Locate frequently idle function in L1 Memory"
 576         default y
 577         help
 578           If enabled, the frequently called idle function is linked
 579           into L1 instruction memory. (less latency)
 580
 581 config SCHEDULE_L1
 582         bool "Locate kernel schedule function in L1 Memory"
 583         default y
 584         help
 585           If enabled, the frequently called kernel schedule is linked
 586           into L1 instruction memory. (less latency)
 587
 588 config ARITHMETIC_OPS_L1
 589         bool "Locate kernel owned arithmetic functions in L1 Memory"
 590         default y
 591         help
 592           If enabled, arithmetic functions are linked
 593           into L1 instruction memory. (less latency)
 594
 595 config ACCESS_OK_L1
 596         bool "Locate access_ok function in L1 Memory"
 597         default y
 598         help
 599           If enabled, the access_ok function is linked
 600           into L1 instruction memory. (less latency)
 601
 602 config MEMSET_L1
 603         bool "Locate memset function in L1 Memory"
 604         default y
 605         help
 606           If enabled, the memset function is linked
 607           into L1 instruction memory. (less latency)
 608
 609 config MEMCPY_L1
 610         bool "Locate memcpy function in L1 Memory"
 611         default y
 612         help
 613           If enabled, the memcpy function is linked
 614           into L1 instruction memory. (less latency)
 615
 616 config SYS_BFIN_SPINLOCK_L1
 617         bool "Locate sys_bfin_spinlock function in L1 Memory"
 618         default y
 619         help
 620           If enabled, sys_bfin_spinlock function is linked
 621           into L1 instruction memory. (less latency)
 622
 623 config IP_CHECKSUM_L1
 624         bool "Locate IP Checksum function in L1 Memory"
 625         default n
 626         help
 627           If enabled, the IP Checksum function is linked
 628           into L1 instruction memory. (less latency)
 629
 630 config CACHELINE_ALIGNED_L1
 631         bool "Locate cacheline_aligned data to L1 Data Memory"
 632         default y if !BF54x
 633         default n if BF54x
 634         depends on !BF531
 635         help
 636           If enabled, cacheline_anligned data is linked
 637           into L1 data memory. (less latency)
 638
 639 config SYSCALL_TAB_L1
 640         bool "Locate Syscall Table L1 Data Memory"
 641         default n
 642         depends on !BF531
 643         help
 644           If enabled, the Syscall LUT is linked
 645           into L1 data memory. (less latency)
 646
 647 config CPLB_SWITCH_TAB_L1
 648         bool "Locate CPLB Switch Tables L1 Data Memory"
 649         default n
 650         depends on !BF531
 651         help
 652           If enabled, the CPLB Switch Tables are linked
 653           into L1 data memory. (less latency)
 654
 655 endmenu
 656
 657
 658 choice
 659         prompt "Kernel executes from"
 660         help
 661           Choose the memory type that the kernel will be running in.
 662
 663 config RAMKERNEL
 664         bool "RAM"
 665         help
 666           The kernel will be resident in RAM when running.
 667
 668 config ROMKERNEL
 669         bool "ROM"
 670         help
 671           The kernel will be resident in FLASH/ROM when running.
 672
 673 endchoice
 674
 675 source "mm/Kconfig"
 676
 677 config BFIN_GPTIMERS
 678         tristate "Enable Blackfin General Purpose Timers API"
 679         default n
 680         help
 681           Enable support for the General Purpose Timers API.  If you
 682           are unsure, say N.
 683
 684           To compile this driver as a module, choose M here: the module
 685           will be called gptimers.ko.
 686
 687 config BFIN_DMA_5XX
 688         bool "Enable DMA Support"
 689         depends on (BF52x || BF53x || BF561 || BF54x)
 690         default y
 691         help
 692           DMA driver for BF5xx.
 693
 694 choice
 695         prompt "Uncached SDRAM region"
 696         default DMA_UNCACHED_1M
 697         depends on BFIN_DMA_5XX
 698 config DMA_UNCACHED_2M
 699         bool "Enable 2M DMA region"
 700 config DMA_UNCACHED_1M
 701         bool "Enable 1M DMA region"
 702 config DMA_UNCACHED_NONE
 703         bool "Disable DMA region"
 704 endchoice
 705
 706
 707 comment "Cache Support"
 708 config BFIN_ICACHE
 709         bool "Enable ICACHE"
 710 config BFIN_DCACHE
 711         bool "Enable DCACHE"
 712 config BFIN_DCACHE_BANKA
 713         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
 714         depends on BFIN_DCACHE && !BF531
 715         default n
 716 config BFIN_ICACHE_LOCK
 717         bool "Enable Instruction Cache Locking"
 718
 719 choice
 720         prompt "Policy"
 721         depends on BFIN_DCACHE
 722         default BFIN_WB
 723 config BFIN_WB
 724         bool "Write back"
 725         help
 726           Write Back Policy:
 727             Cached data will be written back to SDRAM only when needed.
 728             This can give a nice increase in performance, but beware of
 729             broken drivers that do not properly invalidate/flush their
 730             cache.
 731
 732           Write Through Policy:
 733             Cached data will always be written back to SDRAM when the
 734             cache is updated.  This is a completely safe setting, but
 735             performance is worse than Write Back.
 736
 737           If you are unsure of the options and you want to be safe,
 738           then go with Write Through.
 739
 740 config BFIN_WT
 741         bool "Write through"
 742         help
 743           Write Back Policy:
 744             Cached data will be written back to SDRAM only when needed.
 745             This can give a nice increase in performance, but beware of
 746             broken drivers that do not properly invalidate/flush their
 747             cache.
 748
 749           Write Through Policy:
 750             Cached data will always be written back to SDRAM when the
 751             cache is updated.  This is a completely safe setting, but
 752             performance is worse than Write Back.
 753
 754           If you are unsure of the options and you want to be safe,
 755           then go with Write Through.
 756
 757 endchoice
 758
 759 config L1_MAX_PIECE
 760         int "Set the max L1 SRAM pieces"
 761         default 16
 762         help
 763           Set the max memory pieces for the L1 SRAM allocation algorithm.
 764           Min value is 16. Max value is 1024.
 765
 766
 767 config MPU
 768         bool "Enable the memory protection unit (EXPERIMENTAL)"
 769         default n
 770         help
 771           Use the processor's MPU to protect applications from accessing
 772           memory they do not own.  This comes at a performance penalty
 773           and is recommended only for debugging.
 774
 775 comment "Asynchonous Memory Configuration"
 776
 777 menu "EBIU_AMGCTL Global Control"
 778 config C_AMCKEN
 779         bool "Enable CLKOUT"
 780         default y
 781
 782 config C_CDPRIO
 783         bool "DMA has priority over core for ext. accesses"
 784         default n
 785
 786 config C_B0PEN
 787         depends on BF561
 788         bool "Bank 0 16 bit packing enable"
 789         default y
 790
 791 config C_B1PEN
 792         depends on BF561
 793         bool "Bank 1 16 bit packing enable"
 794         default y
 795
 796 config C_B2PEN
 797         depends on BF561
 798         bool "Bank 2 16 bit packing enable"
 799         default y
 800
 801 config C_B3PEN
 802         depends on BF561
 803         bool "Bank 3 16 bit packing enable"
 804         default n
 805
 806 choice
 807         prompt"Enable Asynchonous Memory Banks"
 808         default C_AMBEN_ALL
 809
 810 config C_AMBEN
 811         bool "Disable All Banks"
 812
 813 config C_AMBEN_B0
 814         bool "Enable Bank 0"
 815
 816 config C_AMBEN_B0_B1
 817         bool "Enable Bank 0 & 1"
 818
 819 config C_AMBEN_B0_B1_B2
 820         bool "Enable Bank 0 & 1 & 2"
 821
 822 config C_AMBEN_ALL
 823         bool "Enable All Banks"
 824 endchoice
 825 endmenu
 826
 827 menu "EBIU_AMBCTL Control"
 828 config BANK_0
 829         hex "Bank 0"
 830         default 0x7BB0
 831
 832 config BANK_1
 833         hex "Bank 1"
 834         default 0x7BB0
 835         default 0x5558 if BF54x
 836
 837 config BANK_2
 838         hex "Bank 2"
 839         default 0x7BB0
 840
 841 config BANK_3
 842         hex "Bank 3"
 843         default 0x99B3
 844 endmenu
 845
 846 config EBIU_MBSCTLVAL
 847         hex "EBIU Bank Select Control Register"
 848         depends on BF54x
 849         default 0
 850
 851 config EBIU_MODEVAL
 852         hex "Flash Memory Mode Control Register"
 853         depends on BF54x
 854         default 1
 855
 856 config EBIU_FCTLVAL
 857         hex "Flash Memory Bank Control Register"
 858         depends on BF54x
 859         default 6
 860 endmenu
 861
 862 #############################################################################
 863 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
 864
 865 config PCI
 866         bool "PCI support"
 867         help
 868           Support for PCI bus.
 869
 870 source "drivers/pci/Kconfig"
 871
 872 config HOTPLUG
 873         bool "Support for hot-pluggable device"
 874           help
 875           Say Y here if you want to plug devices into your computer while
 876           the system is running, and be able to use them quickly.  In many
 877           cases, the devices can likewise be unplugged at any time too.
 878
 879           One well known example of this is PCMCIA- or PC-cards, credit-card
 880           size devices such as network cards, modems or hard drives which are
 881           plugged into slots found on all modern laptop computers.  Another
 882           example, used on modern desktops as well as laptops, is USB.
 883
 884           Enable HOTPLUG and KMOD, and build a modular kernel.  Get agent
 885           software (at <http://linux-hotplug.sourceforge.net/>) and install it.
 886           Then your kernel will automatically call out to a user mode "policy
 887           agent" (/sbin/hotplug) to load modules and set up software needed
 888           to use devices as you hotplug them.
 889
 890 source "drivers/pcmcia/Kconfig"
 891
 892 source "drivers/pci/hotplug/Kconfig"
 893
 894 endmenu
 895
 896 menu "Executable file formats"
 897
 898 source "fs/Kconfig.binfmt"
 899
 900 endmenu
 901
 902 menu "Power management options"
 903 source "kernel/power/Kconfig"
 904
 905 config ARCH_SUSPEND_POSSIBLE
 906         def_bool y
 907         depends on !SMP
 908
 909 choice
 910         prompt "Default Power Saving Mode"
 911         depends on PM
 912         default PM_BFIN_SLEEP_DEEPER
 913 config  PM_BFIN_SLEEP_DEEPER
 914         bool "Sleep Deeper"
 915         help
 916           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
 917           power dissipation by disabling the clock to the processor core (CCLK).
 918           Furthermore, Standby sets the internal power supply voltage (VDDINT)
 919           to 0.85 V to provide the greatest power savings, while preserving the
 920           processor state.
 921           The PLL and system clock (SCLK) continue to operate at a very low
 922           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
 923           the SDRAM is put into Self Refresh Mode. Typically an external event
 924           such as GPIO interrupt or RTC activity wakes up the processor.
 925           Various Peripherals such as UART, SPORT, PPI may not function as
 926           normal during Sleep Deeper, due to the reduced SCLK frequency.
 927           When in the sleep mode, system DMA access to L1 memory is not supported.
 928
 929 config  PM_BFIN_SLEEP
 930         bool "Sleep"
 931         help
 932           Sleep Mode (High Power Savings) - The sleep mode reduces power
 933           dissipation by disabling the clock to the processor core (CCLK).
 934           The PLL and system clock (SCLK), however, continue to operate in
 935           this mode. Typically an external event or RTC activity will wake
 936           up the processor. When in the sleep mode,
 937           system DMA access to L1 memory is not supported.
 938 endchoice
 939
 940 config PM_WAKEUP_BY_GPIO
 941         bool "Cause Wakeup Event by GPIO"
 942
 943 config PM_WAKEUP_GPIO_NUMBER
 944         int "Wakeup GPIO number"
 945         range 0 47
 946         depends on PM_WAKEUP_BY_GPIO
 947         default 2 if BFIN537_STAMP
 948
 949 choice
 950         prompt "GPIO Polarity"
 951         depends on PM_WAKEUP_BY_GPIO
 952         default PM_WAKEUP_GPIO_POLAR_H
 953 config  PM_WAKEUP_GPIO_POLAR_H
 954         bool "Active High"
 955 config  PM_WAKEUP_GPIO_POLAR_L
 956         bool "Active Low"
 957 config  PM_WAKEUP_GPIO_POLAR_EDGE_F
 958         bool "Falling EDGE"
 959 config  PM_WAKEUP_GPIO_POLAR_EDGE_R
 960         bool "Rising EDGE"
 961 config  PM_WAKEUP_GPIO_POLAR_EDGE_B
 962         bool "Both EDGE"
 963 endchoice
 964
 965 endmenu
 966
 967 menu "CPU Frequency scaling"
 968
 969 source "drivers/cpufreq/Kconfig"
 970
 971 config CPU_VOLTAGE
 972         bool "CPU Voltage scaling"
 973         depends on EXPERIMENTAL
 974         depends on CPU_FREQ
 975         default n
 976         help
 977           Say Y here if you want CPU voltage scaling according to the CPU frequency.
 978           This option violates the PLL BYPASS recommendation in the Blackfin Processor
 979           manuals. There is a theoretical risk that during VDDINT transitions
 980           the PLL may unlock.
 981
 982 endmenu
 983
 984 source "net/Kconfig"
 985
 986 source "drivers/Kconfig"
 987
 988 source "fs/Kconfig"
 989
 990 source "arch/blackfin/Kconfig.debug"
 991
 992 source "security/Kconfig"
 993
 994 source "crypto/Kconfig"
 995
 996 source "lib/Kconfig"