arch/blackfin/Kconfig

   1 #
   2 # For a description of the syntax of this configuration file,
   3 # see Documentation/kbuild/kconfig-language.txt.
   4 #
   5
   6 mainmenu "Blackfin Kernel Configuration"
   7
   8 config MMU
   9         bool
  10         default n
  11
  12 config FPU
  13         bool
  14         default n
  15
  16 config RWSEM_GENERIC_SPINLOCK
  17         bool
  18         default y
  19
  20 config RWSEM_XCHGADD_ALGORITHM
  21         bool
  22         default n
  23
  24 config BLACKFIN
  25         bool
  26         default y
  27         select HAVE_IDE
  28         select HAVE_OPROFILE
  29
  30 config ZONE_DMA
  31         bool
  32         default y
  33
  34 config GENERIC_FIND_NEXT_BIT
  35         bool
  36         default y
  37
  38 config GENERIC_HWEIGHT
  39         bool
  40         default y
  41
  42 config GENERIC_HARDIRQS
  43         bool
  44         default y
  45
  46 config GENERIC_IRQ_PROBE
  47         bool
  48         default y
  49
  50 config GENERIC_GPIO
  51         bool
  52         default y
  53
  54 config FORCE_MAX_ZONEORDER
  55         int
  56         default "14"
  57
  58 config GENERIC_CALIBRATE_DELAY
  59         bool
  60         default y
  61
  62 config HARDWARE_PM
  63         def_bool y
  64         depends on OPROFILE
  65
  66 source "init/Kconfig"
  67 source "kernel/Kconfig.preempt"
  68
  69 menu "Blackfin Processor Options"
  70
  71 comment "Processor and Board Settings"
  72
  73 choice
  74         prompt "CPU"
  75         default BF533
  76
  77 config BF522
  78         bool "BF522"
  79         help
  80           BF522 Processor Support.
  81
  82 config BF523
  83         bool "BF523"
  84         help
  85           BF523 Processor Support.
  86
  87 config BF524
  88         bool "BF524"
  89         help
  90           BF524 Processor Support.
  91
  92 config BF525
  93         bool "BF525"
  94         help
  95           BF525 Processor Support.
  96
  97 config BF526
  98         bool "BF526"
  99         help
 100           BF526 Processor Support.
 101
 102 config BF527
 103         bool "BF527"
 104         help
 105           BF527 Processor Support.
 106
 107 config BF531
 108         bool "BF531"
 109         help
 110           BF531 Processor Support.
 111
 112 config BF532
 113         bool "BF532"
 114         help
 115           BF532 Processor Support.
 116
 117 config BF533
 118         bool "BF533"
 119         help
 120           BF533 Processor Support.
 121
 122 config BF534
 123         bool "BF534"
 124         help
 125           BF534 Processor Support.
 126
 127 config BF536
 128         bool "BF536"
 129         help
 130           BF536 Processor Support.
 131
 132 config BF537
 133         bool "BF537"
 134         help
 135           BF537 Processor Support.
 136
 137 config BF542
 138         bool "BF542"
 139         help
 140           BF542 Processor Support.
 141
 142 config BF544
 143         bool "BF544"
 144         help
 145           BF544 Processor Support.
 146
 147 config BF547
 148         bool "BF547"
 149         help
 150           BF547 Processor Support.
 151
 152 config BF548
 153         bool "BF548"
 154         help
 155           BF548 Processor Support.
 156
 157 config BF549
 158         bool "BF549"
 159         help
 160           BF549 Processor Support.
 161
 162 config BF561
 163         bool "BF561"
 164         help
 165           Not Supported Yet - Work in progress - BF561 Processor Support.
 166
 167 endchoice
 168
 169 choice
 170         prompt "Silicon Rev"
 171         default BF_REV_0_1 if BF527
 172         default BF_REV_0_2 if BF537
 173         default BF_REV_0_3 if BF533
 174         default BF_REV_0_0 if BF549
 175
 176 config BF_REV_0_0
 177         bool "0.0"
 178         depends on (BF52x || BF54x)
 179
 180 config BF_REV_0_1
 181         bool "0.1"
 182         depends on (BF52x || BF54x)
 183
 184 config BF_REV_0_2
 185         bool "0.2"
 186         depends on (BF537 || BF536 || BF534)
 187
 188 config BF_REV_0_3
 189         bool "0.3"
 190         depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 191
 192 config BF_REV_0_4
 193         bool "0.4"
 194         depends on (BF561 || BF533 || BF532 || BF531)
 195
 196 config BF_REV_0_5
 197         bool "0.5"
 198         depends on (BF561 || BF533 || BF532 || BF531)
 199
 200 config BF_REV_ANY
 201         bool "any"
 202
 203 config BF_REV_NONE
 204         bool "none"
 205
 206 endchoice
 207
 208 config BF52x
 209         bool
 210         depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
 211         default y
 212
 213 config BF53x
 214         bool
 215         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 216         default y
 217
 218 config BF54x
 219         bool
 220         depends on (BF542 || BF544 || BF547 || BF548 || BF549)
 221         default y
 222
 223 config MEM_GENERIC_BOARD
 224         bool
 225         depends on GENERIC_BOARD
 226         default y
 227
 228 config MEM_MT48LC64M4A2FB_7E
 229         bool
 230         depends on (BFIN533_STAMP)
 231         default y
 232
 233 config MEM_MT48LC16M16A2TG_75
 234         bool
 235         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 236                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
 237                 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
 238         default y
 239
 240 config MEM_MT48LC32M8A2_75
 241         bool
 242         depends on (BFIN537_STAMP || PNAV10)
 243         default y
 244
 245 config MEM_MT48LC8M32B2B5_7
 246         bool
 247         depends on (BFIN561_BLUETECHNIX_CM)
 248         default y
 249
 250 config MEM_MT48LC32M16A2TG_75
 251         bool
 252         depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP)
 253         default y
 254
 255 source "arch/blackfin/mach-bf527/Kconfig"
 256 source "arch/blackfin/mach-bf533/Kconfig"
 257 source "arch/blackfin/mach-bf561/Kconfig"
 258 source "arch/blackfin/mach-bf537/Kconfig"
 259 source "arch/blackfin/mach-bf548/Kconfig"
 260
 261 menu "Board customizations"
 262
 263 config CMDLINE_BOOL
 264         bool "Default bootloader kernel arguments"
 265
 266 config CMDLINE
 267         string "Initial kernel command string"
 268         depends on CMDLINE_BOOL
 269         default "console=ttyBF0,57600"
 270         help
 271           If you don't have a boot loader capable of passing a command line string
 272           to the kernel, you may specify one here. As a minimum, you should specify
 273           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 274
 275 config BOOT_LOAD
 276         hex "Kernel load address for booting"
 277         default "0x1000"
 278         range 0x1000 0x20000000
 279         help
 280           This option allows you to set the load address of the kernel.
 281           This can be useful if you are on a board which has a small amount
 282           of memory or you wish to reserve some memory at the beginning of
 283           the address space.
 284
 285           Note that you need to keep this value above 4k (0x1000) as this
 286           memory region is used to capture NULL pointer references as well
 287           as some core kernel functions.
 288
 289 comment "Clock/PLL Setup"
 290
 291 config CLKIN_HZ
 292         int "Frequency of the crystal on the board in Hz"
 293         default "11059200" if BFIN533_STAMP
 294         default "27000000" if BFIN533_EZKIT
 295         default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP)
 296         default "30000000" if BFIN561_EZKIT
 297         default "24576000" if PNAV10
 298         default "10000000" if BFIN532_IP0X
 299         help
 300           The frequency of CLKIN crystal oscillator on the board in Hz.
 301           Warning: This value should match the crystal on the board. Otherwise,
 302           peripherals won't work properly.
 303
 304 config BFIN_KERNEL_CLOCK
 305         bool "Re-program Clocks while Kernel boots?"
 306         default n
 307         help
 308           This option decides if kernel clocks are re-programed from the
 309           bootloader settings. If the clocks are not set, the SDRAM settings
 310           are also not changed, and the Bootloader does 100% of the hardware
 311           configuration.
 312
 313 config PLL_BYPASS
 314         bool "Bypass PLL"
 315         depends on BFIN_KERNEL_CLOCK
 316         default n
 317
 318 config CLKIN_HALF
 319         bool "Half Clock In"
 320         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 321         default n
 322         help
 323           If this is set the clock will be divided by 2, before it goes to the PLL.
 324
 325 config VCO_MULT
 326         int "VCO Multiplier"
 327         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 328         range 1 64
 329         default "22" if BFIN533_EZKIT
 330         default "45" if BFIN533_STAMP
 331         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
 332         default "22" if BFIN533_BLUETECHNIX_CM
 333         default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 334         default "20" if BFIN561_EZKIT
 335         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP)
 336         help
 337           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 338           PLL Frequency = (Crystal Frequency) * (this setting)
 339
 340 choice
 341         prompt "Core Clock Divider"
 342         depends on BFIN_KERNEL_CLOCK
 343         default CCLK_DIV_1
 344         help
 345           This sets the frequency of the core. It can be 1, 2, 4 or 8
 346           Core Frequency = (PLL frequency) / (this setting)
 347
 348 config CCLK_DIV_1
 349         bool "1"
 350
 351 config CCLK_DIV_2
 352         bool "2"
 353
 354 config CCLK_DIV_4
 355         bool "4"
 356
 357 config CCLK_DIV_8
 358         bool "8"
 359 endchoice
 360
 361 config SCLK_DIV
 362         int "System Clock Divider"
 363         depends on BFIN_KERNEL_CLOCK
 364         range 1 15
 365         default 5
 366         help
 367           This sets the frequency of the system clock (including SDRAM or DDR).
 368           This can be between 1 and 15
 369           System Clock = (PLL frequency) / (this setting)
 370
 371 config MAX_MEM_SIZE
 372         int "Max SDRAM Memory Size in MBytes"
 373         depends on !MPU
 374         default 512
 375         help
 376           This is the max memory size that the kernel will create CPLB
 377           tables for.  Your system will not be able to handle any more.
 378
 379 choice
 380         prompt "DDR SDRAM Chip Type"
 381         depends on BFIN_KERNEL_CLOCK
 382         depends on BF54x
 383         default MEM_MT46V32M16_5B
 384
 385 config MEM_MT46V32M16_6T
 386         bool "MT46V32M16_6T"
 387
 388 config MEM_MT46V32M16_5B
 389         bool "MT46V32M16_5B"
 390 endchoice
 391
 392 #
 393 # Max & Min Speeds for various Chips
 394 #
 395 config MAX_VCO_HZ
 396         int
 397         default 600000000 if BF522
 398         default 400000000 if BF523
 399         default 400000000 if BF524
 400         default 600000000 if BF525
 401         default 400000000 if BF526
 402         default 600000000 if BF527
 403         default 400000000 if BF531
 404         default 400000000 if BF532
 405         default 750000000 if BF533
 406         default 500000000 if BF534
 407         default 400000000 if BF536
 408         default 600000000 if BF537
 409         default 533333333 if BF538
 410         default 533333333 if BF539
 411         default 600000000 if BF542
 412         default 533333333 if BF544
 413         default 600000000 if BF547
 414         default 600000000 if BF548
 415         default 533333333 if BF549
 416         default 600000000 if BF561
 417
 418 config MIN_VCO_HZ
 419         int
 420         default 50000000
 421
 422 config MAX_SCLK_HZ
 423         int
 424         default 133333333
 425
 426 config MIN_SCLK_HZ
 427         int
 428         default 27000000
 429
 430 comment "Kernel Timer/Scheduler"
 431
 432 source kernel/Kconfig.hz
 433
 434 config GENERIC_TIME
 435         bool "Generic time"
 436         default y
 437
 438 config GENERIC_CLOCKEVENTS
 439         bool "Generic clock events"
 440         depends on GENERIC_TIME
 441         default y
 442
 443 config CYCLES_CLOCKSOURCE
 444         bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
 445         depends on EXPERIMENTAL
 446         depends on GENERIC_CLOCKEVENTS
 447         depends on !BFIN_SCRATCH_REG_CYCLES
 448         default n
 449         help
 450           If you say Y here, you will enable support for using the 'cycles'
 451           registers as a clock source.  Doing so means you will be unable to
 452           safely write to the 'cycles' register during runtime.  You will
 453           still be able to read it (such as for performance monitoring), but
 454           writing the registers will most likely crash the kernel.
 455
 456 source kernel/time/Kconfig
 457
 458 comment "Memory Setup"
 459
 460 comment "Misc"
 461
 462 choice
 463         prompt "Blackfin Exception Scratch Register"
 464         default BFIN_SCRATCH_REG_RETN
 465         help
 466           Select the resource to reserve for the Exception handler:
 467             - RETN: Non-Maskable Interrupt (NMI)
 468             - RETE: Exception Return (JTAG/ICE)
 469             - CYCLES: Performance counter
 470
 471           If you are unsure, please select "RETN".
 472
 473 config BFIN_SCRATCH_REG_RETN
 474         bool "RETN"
 475         help
 476           Use the RETN register in the Blackfin exception handler
 477           as a stack scratch register.  This means you cannot
 478           safely use NMI on the Blackfin while running Linux, but
 479           you can debug the system with a JTAG ICE and use the
 480           CYCLES performance registers.
 481
 482           If you are unsure, please select "RETN".
 483
 484 config BFIN_SCRATCH_REG_RETE
 485         bool "RETE"
 486         help
 487           Use the RETE register in the Blackfin exception handler
 488           as a stack scratch register.  This means you cannot
 489           safely use a JTAG ICE while debugging a Blackfin board,
 490           but you can safely use the CYCLES performance registers
 491           and the NMI.
 492
 493           If you are unsure, please select "RETN".
 494
 495 config BFIN_SCRATCH_REG_CYCLES
 496         bool "CYCLES"
 497         help
 498           Use the CYCLES register in the Blackfin exception handler
 499           as a stack scratch register.  This means you cannot
 500           safely use the CYCLES performance registers on a Blackfin
 501           board at anytime, but you can debug the system with a JTAG
 502           ICE and use the NMI.
 503
 504           If you are unsure, please select "RETN".
 505
 506 endchoice
 507
 508 endmenu
 509
 510
 511 menu "Blackfin Kernel Optimizations"
 512
 513 comment "Memory Optimizations"
 514
 515 config I_ENTRY_L1
 516         bool "Locate interrupt entry code in L1 Memory"
 517         default y
 518         help
 519           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 520           into L1 instruction memory. (less latency)
 521
 522 config EXCPT_IRQ_SYSC_L1
 523         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 524         default y
 525         help
 526           If enabled, the entire ASM lowlevel exception and interrupt entry code
 527           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 528           (less latency)
 529
 530 config DO_IRQ_L1
 531         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 532         default y
 533         help
 534           If enabled, the frequently called do_irq dispatcher function is linked
 535           into L1 instruction memory. (less latency)
 536
 537 config CORE_TIMER_IRQ_L1
 538         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 539         default y
 540         help
 541           If enabled, the frequently called timer_interrupt() function is linked
 542           into L1 instruction memory. (less latency)
 543
 544 config IDLE_L1
 545         bool "Locate frequently idle function in L1 Memory"
 546         default y
 547         help
 548           If enabled, the frequently called idle function is linked
 549           into L1 instruction memory. (less latency)
 550
 551 config SCHEDULE_L1
 552         bool "Locate kernel schedule function in L1 Memory"
 553         default y
 554         help
 555           If enabled, the frequently called kernel schedule is linked
 556           into L1 instruction memory. (less latency)
 557
 558 config ARITHMETIC_OPS_L1
 559         bool "Locate kernel owned arithmetic functions in L1 Memory"
 560         default y
 561         help
 562           If enabled, arithmetic functions are linked
 563           into L1 instruction memory. (less latency)
 564
 565 config ACCESS_OK_L1
 566         bool "Locate access_ok function in L1 Memory"
 567         default y
 568         help
 569           If enabled, the access_ok function is linked
 570           into L1 instruction memory. (less latency)
 571
 572 config MEMSET_L1
 573         bool "Locate memset function in L1 Memory"
 574         default y
 575         help
 576           If enabled, the memset function is linked
 577           into L1 instruction memory. (less latency)
 578
 579 config MEMCPY_L1
 580         bool "Locate memcpy function in L1 Memory"
 581         default y
 582         help
 583           If enabled, the memcpy function is linked
 584           into L1 instruction memory. (less latency)
 585
 586 config SYS_BFIN_SPINLOCK_L1
 587         bool "Locate sys_bfin_spinlock function in L1 Memory"
 588         default y
 589         help
 590           If enabled, sys_bfin_spinlock function is linked
 591           into L1 instruction memory. (less latency)
 592
 593 config IP_CHECKSUM_L1
 594         bool "Locate IP Checksum function in L1 Memory"
 595         default n
 596         help
 597           If enabled, the IP Checksum function is linked
 598           into L1 instruction memory. (less latency)
 599
 600 config CACHELINE_ALIGNED_L1
 601         bool "Locate cacheline_aligned data to L1 Data Memory"
 602         default y if !BF54x
 603         default n if BF54x
 604         depends on !BF531
 605         help
 606           If enabled, cacheline_anligned data is linked
 607           into L1 data memory. (less latency)
 608
 609 config SYSCALL_TAB_L1
 610         bool "Locate Syscall Table L1 Data Memory"
 611         default n
 612         depends on !BF531
 613         help
 614           If enabled, the Syscall LUT is linked
 615           into L1 data memory. (less latency)
 616
 617 config CPLB_SWITCH_TAB_L1
 618         bool "Locate CPLB Switch Tables L1 Data Memory"
 619         default n
 620         depends on !BF531
 621         help
 622           If enabled, the CPLB Switch Tables are linked
 623           into L1 data memory. (less latency)
 624
 625 comment "Speed Optimizations"
 626 config BFIN_INS_LOWOVERHEAD
 627         bool "ins[bwl] low overhead, higher interrupt latency"
 628         default y
 629         help
 630           Reads on the Blackfin are speculative. In Blackfin terms, this means
 631           they can be interrupted at any time (even after they have been issued
 632           on to the external bus), and re-issued after the interrupt occurs.
 633           For memory - this is not a big deal, since memory does not change if
 634           it sees a read.
 635
 636           If a FIFO is sitting on the end of the read, it will see two reads,
 637           when the core only sees one since the FIFO receives both the read
 638           which is cancelled (and not delivered to the core) and the one which
 639           is re-issued (which is delivered to the core).
 640
 641           To solve this, interrupts are turned off before reads occur to
 642           I/O space. This option controls which the overhead/latency of
 643           controlling interrupts during this time
 644            "n" turns interrupts off every read
 645                 (higher overhead, but lower interrupt latency)
 646            "y" turns interrupts off every loop
 647                 (low overhead, but longer interrupt latency)
 648
 649           default behavior is to leave this set to on (type "Y"). If you are experiencing
 650           interrupt latency issues, it is safe and OK to turn this off.
 651
 652 endmenu
 653
 654
 655 choice
 656         prompt "Kernel executes from"
 657         help
 658           Choose the memory type that the kernel will be running in.
 659
 660 config RAMKERNEL
 661         bool "RAM"
 662         help
 663           The kernel will be resident in RAM when running.
 664
 665 config ROMKERNEL
 666         bool "ROM"
 667         help
 668           The kernel will be resident in FLASH/ROM when running.
 669
 670 endchoice
 671
 672 source "mm/Kconfig"
 673
 674 config BFIN_GPTIMERS
 675         tristate "Enable Blackfin General Purpose Timers API"
 676         default n
 677         help
 678           Enable support for the General Purpose Timers API.  If you
 679           are unsure, say N.
 680
 681           To compile this driver as a module, choose M here: the module
 682           will be called gptimers.ko.
 683
 684 config BFIN_DMA_5XX
 685         bool "Enable DMA Support"
 686         depends on (BF52x || BF53x || BF561 || BF54x)
 687         default y
 688         help
 689           DMA driver for BF5xx.
 690
 691 choice
 692         prompt "Uncached SDRAM region"
 693         default DMA_UNCACHED_1M
 694         depends on BFIN_DMA_5XX
 695 config DMA_UNCACHED_4M
 696         bool "Enable 4M DMA region"
 697 config DMA_UNCACHED_2M
 698         bool "Enable 2M DMA region"
 699 config DMA_UNCACHED_1M
 700         bool "Enable 1M DMA region"
 701 config DMA_UNCACHED_NONE
 702         bool "Disable DMA region"
 703 endchoice
 704
 705
 706 comment "Cache Support"
 707 config BFIN_ICACHE
 708         bool "Enable ICACHE"
 709 config BFIN_DCACHE
 710         bool "Enable DCACHE"
 711 config BFIN_DCACHE_BANKA
 712         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
 713         depends on BFIN_DCACHE && !BF531
 714         default n
 715 config BFIN_ICACHE_LOCK
 716         bool "Enable Instruction Cache Locking"
 717
 718 choice
 719         prompt "Policy"
 720         depends on BFIN_DCACHE
 721         default BFIN_WB
 722 config BFIN_WB
 723         bool "Write back"
 724         help
 725           Write Back Policy:
 726             Cached data will be written back to SDRAM only when needed.
 727             This can give a nice increase in performance, but beware of
 728             broken drivers that do not properly invalidate/flush their
 729             cache.
 730
 731           Write Through Policy:
 732             Cached data will always be written back to SDRAM when the
 733             cache is updated.  This is a completely safe setting, but
 734             performance is worse than Write Back.
 735
 736           If you are unsure of the options and you want to be safe,
 737           then go with Write Through.
 738
 739 config BFIN_WT
 740         bool "Write through"
 741         help
 742           Write Back Policy:
 743             Cached data will be written back to SDRAM only when needed.
 744             This can give a nice increase in performance, but beware of
 745             broken drivers that do not properly invalidate/flush their
 746             cache.
 747
 748           Write Through Policy:
 749             Cached data will always be written back to SDRAM when the
 750             cache is updated.  This is a completely safe setting, but
 751             performance is worse than Write Back.
 752
 753           If you are unsure of the options and you want to be safe,
 754           then go with Write Through.
 755
 756 endchoice
 757
 758 config MPU
 759         bool "Enable the memory protection unit (EXPERIMENTAL)"
 760         default n
 761         help
 762           Use the processor's MPU to protect applications from accessing
 763           memory they do not own.  This comes at a performance penalty
 764           and is recommended only for debugging.
 765
 766 comment "Asynchonous Memory Configuration"
 767
 768 menu "EBIU_AMGCTL Global Control"
 769 config C_AMCKEN
 770         bool "Enable CLKOUT"
 771         default y
 772
 773 config C_CDPRIO
 774         bool "DMA has priority over core for ext. accesses"
 775         default n
 776
 777 config C_B0PEN
 778         depends on BF561
 779         bool "Bank 0 16 bit packing enable"
 780         default y
 781
 782 config C_B1PEN
 783         depends on BF561
 784         bool "Bank 1 16 bit packing enable"
 785         default y
 786
 787 config C_B2PEN
 788         depends on BF561
 789         bool "Bank 2 16 bit packing enable"
 790         default y
 791
 792 config C_B3PEN
 793         depends on BF561
 794         bool "Bank 3 16 bit packing enable"
 795         default n
 796
 797 choice
 798         prompt"Enable Asynchonous Memory Banks"
 799         default C_AMBEN_ALL
 800
 801 config C_AMBEN
 802         bool "Disable All Banks"
 803
 804 config C_AMBEN_B0
 805         bool "Enable Bank 0"
 806
 807 config C_AMBEN_B0_B1
 808         bool "Enable Bank 0 & 1"
 809
 810 config C_AMBEN_B0_B1_B2
 811         bool "Enable Bank 0 & 1 & 2"
 812
 813 config C_AMBEN_ALL
 814         bool "Enable All Banks"
 815 endchoice
 816 endmenu
 817
 818 menu "EBIU_AMBCTL Control"
 819 config BANK_0
 820         hex "Bank 0"
 821         default 0x7BB0
 822
 823 config BANK_1
 824         hex "Bank 1"
 825         default 0x7BB0
 826         default 0x5558 if BF54x
 827
 828 config BANK_2
 829         hex "Bank 2"
 830         default 0x7BB0
 831
 832 config BANK_3
 833         hex "Bank 3"
 834         default 0x99B3
 835 endmenu
 836
 837 config EBIU_MBSCTLVAL
 838         hex "EBIU Bank Select Control Register"
 839         depends on BF54x
 840         default 0
 841
 842 config EBIU_MODEVAL
 843         hex "Flash Memory Mode Control Register"
 844         depends on BF54x
 845         default 1
 846
 847 config EBIU_FCTLVAL
 848         hex "Flash Memory Bank Control Register"
 849         depends on BF54x
 850         default 6
 851 endmenu
 852
 853 #############################################################################
 854 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
 855
 856 config PCI
 857         bool "PCI support"
 858         depends on BROKEN
 859         help
 860           Support for PCI bus.
 861
 862 source "drivers/pci/Kconfig"
 863
 864 config HOTPLUG
 865         bool "Support for hot-pluggable device"
 866           help
 867           Say Y here if you want to plug devices into your computer while
 868           the system is running, and be able to use them quickly.  In many
 869           cases, the devices can likewise be unplugged at any time too.
 870
 871           One well known example of this is PCMCIA- or PC-cards, credit-card
 872           size devices such as network cards, modems or hard drives which are
 873           plugged into slots found on all modern laptop computers.  Another
 874           example, used on modern desktops as well as laptops, is USB.
 875
 876           Enable HOTPLUG and build a modular kernel.  Get agent software
 877           (from <http://linux-hotplug.sourceforge.net/>) and install it.
 878           Then your kernel will automatically call out to a user mode "policy
 879           agent" (/sbin/hotplug) to load modules and set up software needed
 880           to use devices as you hotplug them.
 881
 882 source "drivers/pcmcia/Kconfig"
 883
 884 source "drivers/pci/hotplug/Kconfig"
 885
 886 endmenu
 887
 888 menu "Executable file formats"
 889
 890 source "fs/Kconfig.binfmt"
 891
 892 endmenu
 893
 894 menu "Power management options"
 895 source "kernel/power/Kconfig"
 896
 897 config ARCH_SUSPEND_POSSIBLE
 898         def_bool y
 899         depends on !SMP
 900
 901 choice
 902         prompt "Standby Power Saving Mode"
 903         depends on PM
 904         default PM_BFIN_SLEEP_DEEPER
 905 config  PM_BFIN_SLEEP_DEEPER
 906         bool "Sleep Deeper"
 907         help
 908           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
 909           power dissipation by disabling the clock to the processor core (CCLK).
 910           Furthermore, Standby sets the internal power supply voltage (VDDINT)
 911           to 0.85 V to provide the greatest power savings, while preserving the
 912           processor state.
 913           The PLL and system clock (SCLK) continue to operate at a very low
 914           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
 915           the SDRAM is put into Self Refresh Mode. Typically an external event
 916           such as GPIO interrupt or RTC activity wakes up the processor.
 917           Various Peripherals such as UART, SPORT, PPI may not function as
 918           normal during Sleep Deeper, due to the reduced SCLK frequency.
 919           When in the sleep mode, system DMA access to L1 memory is not supported.
 920
 921           If unsure, select "Sleep Deeper".
 922
 923 config  PM_BFIN_SLEEP
 924         bool "Sleep"
 925         help
 926           Sleep Mode (High Power Savings) - The sleep mode reduces power
 927           dissipation by disabling the clock to the processor core (CCLK).
 928           The PLL and system clock (SCLK), however, continue to operate in
 929           this mode. Typically an external event or RTC activity will wake
 930           up the processor. When in the sleep mode, system DMA access to L1
 931           memory is not supported.
 932
 933           If unsure, select "Sleep Deeper".
 934 endchoice
 935
 936 config PM_WAKEUP_BY_GPIO
 937         bool "Allow Wakeup from Standby by GPIO"
 938
 939 config PM_WAKEUP_GPIO_NUMBER
 940         int "GPIO number"
 941         range 0 47
 942         depends on PM_WAKEUP_BY_GPIO
 943         default 2 if BFIN537_STAMP
 944
 945 choice
 946         prompt "GPIO Polarity"
 947         depends on PM_WAKEUP_BY_GPIO
 948         default PM_WAKEUP_GPIO_POLAR_H
 949 config  PM_WAKEUP_GPIO_POLAR_H
 950         bool "Active High"
 951 config  PM_WAKEUP_GPIO_POLAR_L
 952         bool "Active Low"
 953 config  PM_WAKEUP_GPIO_POLAR_EDGE_F
 954         bool "Falling EDGE"
 955 config  PM_WAKEUP_GPIO_POLAR_EDGE_R
 956         bool "Rising EDGE"
 957 config  PM_WAKEUP_GPIO_POLAR_EDGE_B
 958         bool "Both EDGE"
 959 endchoice
 960
 961 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
 962         depends on PM
 963
 964 config PM_BFIN_WAKE_PH6
 965         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
 966         depends on PM && (BF52x || BF534 || BF536 || BF537)
 967         default n
 968         help
 969           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
 970
 971 config PM_BFIN_WAKE_GP
 972         bool "Allow Wake-Up from GPIOs"
 973         depends on PM && BF54x
 974         default n
 975         help
 976           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
 977 endmenu
 978
 979 menu "CPU Frequency scaling"
 980
 981 source "drivers/cpufreq/Kconfig"
 982
 983 config CPU_VOLTAGE
 984         bool "CPU Voltage scaling"
 985         depends on EXPERIMENTAL
 986         depends on CPU_FREQ
 987         default n
 988         help
 989           Say Y here if you want CPU voltage scaling according to the CPU frequency.
 990           This option violates the PLL BYPASS recommendation in the Blackfin Processor
 991           manuals. There is a theoretical risk that during VDDINT transitions
 992           the PLL may unlock.
 993
 994 endmenu
 995
 996 source "net/Kconfig"
 997
 998 source "drivers/Kconfig"
 999
1000 source "fs/Kconfig"
1001
1002 source "arch/blackfin/Kconfig.debug"
1003
1004 source "security/Kconfig"
1005
1006 source "crypto/Kconfig"
1007
1008 source "lib/Kconfig"