arch/blackfin/include/asm/ptrace.h

   1 /*
   2  * Copyright 2004-2008 Analog Devices Inc.
   3  *
   4  * Licensed under the GPL-2 or later.
   5  */
   6
   7 #ifndef _BFIN_PTRACE_H
   8 #define _BFIN_PTRACE_H
   9
  10 /*
  11  * GCC defines register number like this:
  12  * -----------------------------
  13  *       0 - 7 are data registers R0-R7
  14  *       8 - 15 are address registers P0-P7
  15  *      16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
  16  *      32 - 33 A registers A0 & A1
  17  *      34 -    status register
  18  * -----------------------------
  19  *
  20  * We follows above, except:
  21  *      32-33 --- Low 32-bit of A0&1
  22  *      34-35 --- High 8-bit of A0&1
  23  */
  24
  25 #ifndef __ASSEMBLY__
  26
  27 /* this struct defines the way the registers are stored on the
  28    stack during a system call. */
  29
  30 struct pt_regs {
  31         long orig_pc;
  32         long ipend;
  33         long seqstat;
  34         long rete;
  35         long retn;
  36         long retx;
  37         long pc;                /* PC == RETI */
  38         long rets;
  39         long reserved;          /* Used as scratch during system calls */
  40         long astat;
  41         long lb1;
  42         long lb0;
  43         long lt1;
  44         long lt0;
  45         long lc1;
  46         long lc0;
  47         long a1w;
  48         long a1x;
  49         long a0w;
  50         long a0x;
  51         long b3;
  52         long b2;
  53         long b1;
  54         long b0;
  55         long l3;
  56         long l2;
  57         long l1;
  58         long l0;
  59         long m3;
  60         long m2;
  61         long m1;
  62         long m0;
  63         long i3;
  64         long i2;
  65         long i1;
  66         long i0;
  67         long usp;
  68         long fp;
  69         long p5;
  70         long p4;
  71         long p3;
  72         long p2;
  73         long p1;
  74         long p0;
  75         long r7;
  76         long r6;
  77         long r5;
  78         long r4;
  79         long r3;
  80         long r2;
  81         long r1;
  82         long r0;
  83         long orig_r0;
  84         long orig_p0;
  85         long syscfg;
  86 };
  87
  88 /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
  89 #define PTRACE_GETREGS            12
  90 #define PTRACE_SETREGS            13    /* ptrace signal  */
  91
  92 #define PTRACE_GETFDPIC           31    /* get the ELF fdpic loadmap address */
  93 #define PTRACE_GETFDPIC_EXEC       0    /* [addr] request the executable loadmap */
  94 #define PTRACE_GETFDPIC_INTERP     1    /* [addr] request the interpreter loadmap */
  95
  96 #define PS_S  (0x0002)
  97
  98 #ifdef __KERNEL__
  99
 100 /* user_mode returns true if only one bit is set in IPEND, other than the
 101    master interrupt enable.  */
 102 #define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
 103 #define instruction_pointer(regs) ((regs)->pc)
 104 #define profile_pc(regs) instruction_pointer(regs)
 105 extern void show_regs(struct pt_regs *);
 106
 107 #endif  /*  __KERNEL__  */
 108
 109 #endif                          /* __ASSEMBLY__ */
 110
 111 /*
 112  * Offsets used by 'ptrace' system call interface.
 113  */
 114
 115 #define PT_R0 204
 116 #define PT_R1 200
 117 #define PT_R2 196
 118 #define PT_R3 192
 119 #define PT_R4 188
 120 #define PT_R5 184
 121 #define PT_R6 180
 122 #define PT_R7 176
 123 #define PT_P0 172
 124 #define PT_P1 168
 125 #define PT_P2 164
 126 #define PT_P3 160
 127 #define PT_P4 156
 128 #define PT_P5 152
 129 #define PT_FP 148
 130 #define PT_USP 144
 131 #define PT_I0 140
 132 #define PT_I1 136
 133 #define PT_I2 132
 134 #define PT_I3 128
 135 #define PT_M0 124
 136 #define PT_M1 120
 137 #define PT_M2 116
 138 #define PT_M3 112
 139 #define PT_L0 108
 140 #define PT_L1 104
 141 #define PT_L2 100
 142 #define PT_L3 96
 143 #define PT_B0 92
 144 #define PT_B1 88
 145 #define PT_B2 84
 146 #define PT_B3 80
 147 #define PT_A0X 76
 148 #define PT_A0W 72
 149 #define PT_A1X 68
 150 #define PT_A1W 64
 151 #define PT_LC0 60
 152 #define PT_LC1 56
 153 #define PT_LT0 52
 154 #define PT_LT1 48
 155 #define PT_LB0 44
 156 #define PT_LB1 40
 157 #define PT_ASTAT 36
 158 #define PT_RESERVED 32
 159 #define PT_RETS 28
 160 #define PT_PC 24
 161 #define PT_RETX 20
 162 #define PT_RETN 16
 163 #define PT_RETE 12
 164 #define PT_SEQSTAT 8
 165 #define PT_IPEND 4
 166
 167 #define PT_ORIG_R0 208
 168 #define PT_ORIG_P0 212
 169 #define PT_SYSCFG 216
 170 #define PT_TEXT_ADDR 220
 171 #define PT_TEXT_END_ADDR 224
 172 #define PT_DATA_ADDR 228
 173 #define PT_FDPIC_EXEC 232
 174 #define PT_FDPIC_INTERP 236
 175
 176 #endif                          /* _BFIN_PTRACE_H */