arch/blackfin/include/uapi/asm/bfin_sport.h

   1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
   2 /*
   3  * bfin_sport.h - interface to Blackfin SPORTs
   4  *
   5  * Copyright 2004-2009 Analog Devices Inc.
   6  *
   7  * Licensed under the GPL-2 or later.
   8  */
   9
  10 #ifndef _UAPI__BFIN_SPORT_H__
  11 #define _UAPI__BFIN_SPORT_H__
  12
  13 /* Sport mode: it can be set to TDM, i2s or others */
  14 #define NORM_MODE       0x0
  15 #define TDM_MODE        0x1
  16 #define I2S_MODE        0x2
  17 #define NDSO_MODE       0x3
  18
  19 /* Data format, normal, a-law or u-law */
  20 #define NORM_FORMAT     0x0
  21 #define ALAW_FORMAT     0x2
  22 #define ULAW_FORMAT     0x3
  23
  24 /* Function driver which use sport must initialize the structure */
  25 struct sport_config {
  26         /* TDM (multichannels), I2S or other mode */
  27         unsigned int mode:3;
  28         unsigned int polled;    /* use poll instead of irq when set */
  29
  30         /* if TDM mode is selected, channels must be set */
  31         int channels;   /* Must be in 8 units */
  32         unsigned int frame_delay:4;     /* Delay between frame sync pulse and first bit */
  33
  34         /* I2S mode */
  35         unsigned int right_first:1;     /* Right stereo channel first */
  36
  37         /* In mormal mode, the following item need to be set */
  38         unsigned int lsb_first:1;       /* order of transmit or receive data */
  39         unsigned int fsync:1;   /* Frame sync required */
  40         unsigned int data_indep:1;      /* data independent frame sync generated */
  41         unsigned int act_low:1; /* Active low TFS */
  42         unsigned int late_fsync:1;      /* Late frame sync */
  43         unsigned int tckfe:1;
  44         unsigned int sec_en:1;  /* Secondary side enabled */
  45
  46         /* Choose clock source */
  47         unsigned int int_clk:1; /* Internal or external clock */
  48
  49         /* If external clock is used, the following fields are ignored */
  50         int serial_clk;
  51         int fsync_clk;
  52
  53         unsigned int data_format:2;     /* Normal, u-law or a-law */
  54
  55         int word_len;           /* How length of the word in bits, 3-32 bits */
  56         int dma_enabled;
  57 };
  58
  59 /* Userspace interface */
  60 #define SPORT_IOC_MAGIC         'P'
  61 #define SPORT_IOC_CONFIG        _IOWR('P', 0x01, struct sport_config)
  62 #define SPORT_IOC_GET_SYSTEMCLOCK         _IOR('P', 0x02, unsigned long)
  63 #define SPORT_IOC_SET_BAUDRATE            _IOW('P', 0x03, unsigned long)
  64
  65
  66 /* SPORT_TCR1 Masks */
  67 #define TSPEN           0x0001  /* TX enable */
  68 #define ITCLK           0x0002  /* Internal TX Clock Select */
  69 #define TDTYPE          0x000C  /* TX Data Formatting Select */
  70 #define DTYPE_NORM      0x0000  /* Data Format Normal */
  71 #define DTYPE_ULAW      0x0008  /* Compand Using u-Law */
  72 #define DTYPE_ALAW      0x000C  /* Compand Using A-Law */
  73 #define TLSBIT          0x0010  /* TX Bit Order */
  74 #define ITFS            0x0200  /* Internal TX Frame Sync Select */
  75 #define TFSR            0x0400  /* TX Frame Sync Required Select */
  76 #define DITFS           0x0800  /* Data Independent TX Frame Sync Select */
  77 #define LTFS            0x1000  /* Low TX Frame Sync Select */
  78 #define LATFS           0x2000  /* Late TX Frame Sync Select */
  79 #define TCKFE           0x4000  /* TX Clock Falling Edge Select */
  80
  81 /* SPORT_TCR2 Masks */
  82 #define SLEN            0x001F  /* SPORT TX Word Length (2 - 31) */
  83 #define DP_SLEN(x)      BFIN_DEPOSIT(SLEN, x)
  84 #define EX_SLEN(x)      BFIN_EXTRACT(SLEN, x)
  85 #define TXSE            0x0100  /* TX Secondary Enable */
  86 #define TSFSE           0x0200  /* TX Stereo Frame Sync Enable */
  87 #define TRFST           0x0400  /* TX Right-First Data Order */
  88
  89 /* SPORT_RCR1 Masks */
  90 #define RSPEN           0x0001  /* RX enable */
  91 #define IRCLK           0x0002  /* Internal RX Clock Select */
  92 #define RDTYPE          0x000C  /* RX Data Formatting Select */
  93 /* DTYPE_* defined above */
  94 #define RLSBIT          0x0010  /* RX Bit Order */
  95 #define IRFS            0x0200  /* Internal RX Frame Sync Select */
  96 #define RFSR            0x0400  /* RX Frame Sync Required Select */
  97 #define LRFS            0x1000  /* Low RX Frame Sync Select */
  98 #define LARFS           0x2000  /* Late RX Frame Sync Select */
  99 #define RCKFE           0x4000  /* RX Clock Falling Edge Select */
 100
 101 /* SPORT_RCR2 Masks */
 102 /* SLEN defined above */
 103 #define RXSE            0x0100  /* RX Secondary Enable */
 104 #define RSFSE           0x0200  /* RX Stereo Frame Sync Enable */
 105 #define RRFST           0x0400  /* Right-First Data Order */
 106
 107 /* SPORT_STAT Masks */
 108 #define RXNE            0x0001  /* RX FIFO Not Empty Status */
 109 #define RUVF            0x0002  /* RX Underflow Status */
 110 #define ROVF            0x0004  /* RX Overflow Status */
 111 #define TXF             0x0008  /* TX FIFO Full Status */
 112 #define TUVF            0x0010  /* TX Underflow Status */
 113 #define TOVF            0x0020  /* TX Overflow Status */
 114 #define TXHRE           0x0040  /* TX Hold Register Empty */
 115
 116 /* SPORT_MCMC1 Masks */
 117 #define SP_WOFF         0x03FF  /* Multichannel Window Offset Field */
 118 #define DP_SP_WOFF(x)   BFIN_DEPOSIT(SP_WOFF, x)
 119 #define EX_SP_WOFF(x)   BFIN_EXTRACT(SP_WOFF, x)
 120 #define SP_WSIZE        0xF000  /* Multichannel Window Size Field */
 121 #define DP_SP_WSIZE(x)  BFIN_DEPOSIT(SP_WSIZE, x)
 122 #define EX_SP_WSIZE(x)  BFIN_EXTRACT(SP_WSIZE, x)
 123
 124 /* SPORT_MCMC2 Masks */
 125 #define MCCRM           0x0003  /* Multichannel Clock Recovery Mode */
 126 #define REC_BYPASS      0x0000  /* Bypass Mode (No Clock Recovery) */
 127 #define REC_2FROM4      0x0002  /* Recover 2 MHz Clock from 4 MHz Clock */
 128 #define REC_8FROM16     0x0003  /* Recover 8 MHz Clock from 16 MHz Clock */
 129 #define MCDTXPE         0x0004  /* Multichannel DMA Transmit Packing */
 130 #define MCDRXPE         0x0008  /* Multichannel DMA Receive Packing */
 131 #define MCMEN           0x0010  /* Multichannel Frame Mode Enable */
 132 #define FSDR            0x0080  /* Multichannel Frame Sync to Data Relationship */
 133 #define MFD             0xF000  /* Multichannel Frame Delay */
 134 #define DP_MFD(x)       BFIN_DEPOSIT(MFD, x)
 135 #define EX_MFD(x)       BFIN_EXTRACT(MFD, x)
 136
 137 #endif /* _UAPI__BFIN_SPORT_H__ */