2 * Blackfin architecture-dependent process handling
4 * Copyright 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later
9 #include <linux/module.h>
10 #include <linux/unistd.h>
11 #include <linux/user.h>
12 #include <linux/uaccess.h>
13 #include <linux/slab.h>
14 #include <linux/sched.h>
15 #include <linux/sched/debug.h>
16 #include <linux/sched/task.h>
17 #include <linux/tick.h>
19 #include <linux/err.h>
21 #include <asm/blackfin.h>
22 #include <asm/fixed_code.h>
23 #include <asm/mem_map.h>
26 asmlinkage
void ret_from_fork(void);
28 /* Points to the SDRAM backup memory for the stack that is currently in
29 * L1 scratchpad memory.
31 void *current_l1_stack_save
;
33 /* The number of tasks currently using a L1 stack area. The SRAM is
34 * allocated/deallocated whenever this changes from/to zero.
38 /* Start and length of the area in L1 scratchpad memory which we've allocated
42 unsigned long l1_stack_len
;
44 void (*pm_power_off
)(void) = NULL
;
45 EXPORT_SYMBOL(pm_power_off
);
48 * The idle loop on BFIN
51 void arch_cpu_idle(void)__attribute__((l1_text
));
55 * This is our default idle handler. We need to disable
56 * interrupts here to ensure we don't miss a wakeup call.
58 void arch_cpu_idle(void)
61 ipipe_suspend_domain();
63 hard_local_irq_disable();
65 idle_with_irq_disabled();
67 hard_local_irq_enable();
70 #ifdef CONFIG_HOTPLUG_CPU
71 void arch_cpu_idle_dead(void)
78 * Do necessary setup to start up a newly executed thread.
80 * pass the data segment into user programs if it exists,
81 * it can't hurt anything as far as I can tell
83 void start_thread(struct pt_regs
*regs
, unsigned long new_ip
, unsigned long new_sp
)
87 regs
->p5
= current
->mm
->start_data
;
89 task_thread_info(current
)->l1_task_info
.stack_start
=
90 (void *)current
->mm
->context
.stack_start
;
91 task_thread_info(current
)->l1_task_info
.lowest_sp
= (void *)new_sp
;
92 memcpy(L1_SCRATCH_TASK_INFO
, &task_thread_info(current
)->l1_task_info
,
93 sizeof(*L1_SCRATCH_TASK_INFO
));
97 EXPORT_SYMBOL_GPL(start_thread
);
99 void flush_thread(void)
103 asmlinkage
int bfin_clone(unsigned long clone_flags
, unsigned long newsp
)
105 #ifdef __ARCH_SYNC_CORE_DCACHE
106 if (current
->nr_cpus_allowed
== num_possible_cpus())
107 set_cpus_allowed_ptr(current
, cpumask_of(smp_processor_id()));
111 return do_fork(clone_flags
, newsp
, 0, NULL
, NULL
);
115 copy_thread(unsigned long clone_flags
,
116 unsigned long usp
, unsigned long topstk
,
117 struct task_struct
*p
)
119 struct pt_regs
*childregs
;
122 childregs
= (struct pt_regs
*) (task_stack_page(p
) + THREAD_SIZE
) - 1;
123 v
= ((unsigned long *)childregs
) - 2;
124 if (unlikely(p
->flags
& PF_KTHREAD
)) {
125 memset(childregs
, 0, sizeof(struct pt_regs
));
128 childregs
->orig_p0
= -1;
129 childregs
->ipend
= 0x8000;
130 __asm__
__volatile__("%0 = syscfg;":"=da"(childregs
->syscfg
):);
133 *childregs
= *current_pt_regs();
135 p
->thread
.usp
= usp
? : rdusp();
139 p
->thread
.ksp
= (unsigned long)v
;
140 p
->thread
.pc
= (unsigned long)ret_from_fork
;
145 unsigned long get_wchan(struct task_struct
*p
)
147 unsigned long fp
, pc
;
148 unsigned long stack_page
;
150 if (!p
|| p
== current
|| p
->state
== TASK_RUNNING
)
153 stack_page
= (unsigned long)p
;
156 if (fp
< stack_page
+ sizeof(struct thread_info
) ||
157 fp
>= 8184 + stack_page
)
159 pc
= ((unsigned long *)fp
)[1];
160 if (!in_sched_functions(pc
))
162 fp
= *(unsigned long *)fp
;
164 while (count
++ < 16);
168 void finish_atomic_sections (struct pt_regs
*regs
)
170 int __user
*up0
= (int __user
*)regs
->p0
;
174 /* not in middle of an atomic step, so resume like normal */
177 case ATOMIC_XCHG32
+ 2:
178 put_user(regs
->r1
, up0
);
181 case ATOMIC_CAS32
+ 2:
182 case ATOMIC_CAS32
+ 4:
183 if (regs
->r0
== regs
->r1
)
184 case ATOMIC_CAS32
+ 6:
185 put_user(regs
->r2
, up0
);
188 case ATOMIC_ADD32
+ 2:
189 regs
->r0
= regs
->r1
+ regs
->r0
;
191 case ATOMIC_ADD32
+ 4:
192 put_user(regs
->r0
, up0
);
195 case ATOMIC_SUB32
+ 2:
196 regs
->r0
= regs
->r1
- regs
->r0
;
198 case ATOMIC_SUB32
+ 4:
199 put_user(regs
->r0
, up0
);
202 case ATOMIC_IOR32
+ 2:
203 regs
->r0
= regs
->r1
| regs
->r0
;
205 case ATOMIC_IOR32
+ 4:
206 put_user(regs
->r0
, up0
);
209 case ATOMIC_AND32
+ 2:
210 regs
->r0
= regs
->r1
& regs
->r0
;
212 case ATOMIC_AND32
+ 4:
213 put_user(regs
->r0
, up0
);
216 case ATOMIC_XOR32
+ 2:
217 regs
->r0
= regs
->r1
^ regs
->r0
;
219 case ATOMIC_XOR32
+ 4:
220 put_user(regs
->r0
, up0
);
225 * We've finished the atomic section, and the only thing left for
226 * userspace is to do a RTS, so we might as well handle that too
227 * since we need to update the PC anyways.
229 regs
->pc
= regs
->rets
;
233 int in_mem(unsigned long addr
, unsigned long size
,
234 unsigned long start
, unsigned long end
)
236 return addr
>= start
&& addr
+ size
<= end
;
239 int in_mem_const_off(unsigned long addr
, unsigned long size
, unsigned long off
,
240 unsigned long const_addr
, unsigned long const_size
)
243 in_mem(addr
, size
, const_addr
+ off
, const_addr
+ const_size
);
246 int in_mem_const(unsigned long addr
, unsigned long size
,
247 unsigned long const_addr
, unsigned long const_size
)
249 return in_mem_const_off(addr
, size
, 0, const_addr
, const_size
);
252 #define ASYNC_ENABLED(bnum, bctlnum) 1
254 #define ASYNC_ENABLED(bnum, bctlnum) \
256 (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
257 bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
262 * We can't read EBIU banks that aren't enabled or we end up hanging
263 * on the access to the async space. Make sure we validate accesses
264 * that cross async banks too.
265 * 0 - found, but unusable
270 int in_async(unsigned long addr
, unsigned long size
)
272 if (addr
>= ASYNC_BANK0_BASE
&& addr
< ASYNC_BANK0_BASE
+ ASYNC_BANK0_SIZE
) {
273 if (!ASYNC_ENABLED(0, 0))
275 if (addr
+ size
<= ASYNC_BANK0_BASE
+ ASYNC_BANK0_SIZE
)
277 size
-= ASYNC_BANK0_BASE
+ ASYNC_BANK0_SIZE
- addr
;
278 addr
= ASYNC_BANK0_BASE
+ ASYNC_BANK0_SIZE
;
280 if (addr
>= ASYNC_BANK1_BASE
&& addr
< ASYNC_BANK1_BASE
+ ASYNC_BANK1_SIZE
) {
281 if (!ASYNC_ENABLED(1, 0))
283 if (addr
+ size
<= ASYNC_BANK1_BASE
+ ASYNC_BANK1_SIZE
)
285 size
-= ASYNC_BANK1_BASE
+ ASYNC_BANK1_SIZE
- addr
;
286 addr
= ASYNC_BANK1_BASE
+ ASYNC_BANK1_SIZE
;
288 if (addr
>= ASYNC_BANK2_BASE
&& addr
< ASYNC_BANK2_BASE
+ ASYNC_BANK2_SIZE
) {
289 if (!ASYNC_ENABLED(2, 1))
291 if (addr
+ size
<= ASYNC_BANK2_BASE
+ ASYNC_BANK2_SIZE
)
293 size
-= ASYNC_BANK2_BASE
+ ASYNC_BANK2_SIZE
- addr
;
294 addr
= ASYNC_BANK2_BASE
+ ASYNC_BANK2_SIZE
;
296 if (addr
>= ASYNC_BANK3_BASE
&& addr
< ASYNC_BANK3_BASE
+ ASYNC_BANK3_SIZE
) {
297 if (ASYNC_ENABLED(3, 1))
299 if (addr
+ size
<= ASYNC_BANK3_BASE
+ ASYNC_BANK3_SIZE
)
304 /* not within async bounds */
308 int bfin_mem_access_type(unsigned long addr
, unsigned long size
)
310 int cpu
= raw_smp_processor_id();
312 /* Check that things do not wrap around */
313 if (addr
> ULONG_MAX
- size
)
316 if (in_mem(addr
, size
, FIXED_CODE_START
, physical_mem_end
))
317 return BFIN_MEM_ACCESS_CORE
;
319 if (in_mem_const(addr
, size
, L1_CODE_START
, L1_CODE_LENGTH
))
320 return cpu
== 0 ? BFIN_MEM_ACCESS_ITEST
: BFIN_MEM_ACCESS_IDMA
;
321 if (in_mem_const(addr
, size
, L1_SCRATCH_START
, L1_SCRATCH_LENGTH
))
322 return cpu
== 0 ? BFIN_MEM_ACCESS_CORE_ONLY
: -EFAULT
;
323 if (in_mem_const(addr
, size
, L1_DATA_A_START
, L1_DATA_A_LENGTH
))
324 return cpu
== 0 ? BFIN_MEM_ACCESS_CORE
: BFIN_MEM_ACCESS_IDMA
;
325 if (in_mem_const(addr
, size
, L1_DATA_B_START
, L1_DATA_B_LENGTH
))
326 return cpu
== 0 ? BFIN_MEM_ACCESS_CORE
: BFIN_MEM_ACCESS_IDMA
;
327 #ifdef COREB_L1_CODE_START
328 if (in_mem_const(addr
, size
, COREB_L1_CODE_START
, COREB_L1_CODE_LENGTH
))
329 return cpu
== 1 ? BFIN_MEM_ACCESS_ITEST
: BFIN_MEM_ACCESS_IDMA
;
330 if (in_mem_const(addr
, size
, COREB_L1_SCRATCH_START
, L1_SCRATCH_LENGTH
))
331 return cpu
== 1 ? BFIN_MEM_ACCESS_CORE_ONLY
: -EFAULT
;
332 if (in_mem_const(addr
, size
, COREB_L1_DATA_A_START
, COREB_L1_DATA_A_LENGTH
))
333 return cpu
== 1 ? BFIN_MEM_ACCESS_CORE
: BFIN_MEM_ACCESS_IDMA
;
334 if (in_mem_const(addr
, size
, COREB_L1_DATA_B_START
, COREB_L1_DATA_B_LENGTH
))
335 return cpu
== 1 ? BFIN_MEM_ACCESS_CORE
: BFIN_MEM_ACCESS_IDMA
;
337 if (in_mem_const(addr
, size
, L2_START
, L2_LENGTH
))
338 return BFIN_MEM_ACCESS_CORE
;
340 if (addr
>= SYSMMR_BASE
)
341 return BFIN_MEM_ACCESS_CORE_ONLY
;
343 switch (in_async(addr
, size
)) {
344 case 0: return -EFAULT
;
345 case 1: return BFIN_MEM_ACCESS_CORE
;
346 case 2: /* fall through */;
349 if (in_mem_const(addr
, size
, BOOT_ROM_START
, BOOT_ROM_LENGTH
))
350 return BFIN_MEM_ACCESS_CORE
;
351 if (in_mem_const(addr
, size
, L1_ROM_START
, L1_ROM_LENGTH
))
352 return BFIN_MEM_ACCESS_DMA
;
357 #if defined(CONFIG_ACCESS_CHECK)
358 #ifdef CONFIG_ACCESS_OK_L1
359 __attribute__((l1_text
))
361 /* Return 1 if access to memory range is OK, 0 otherwise */
362 int _access_ok(unsigned long addr
, unsigned long size
)
368 /* Check that things do not wrap around */
369 if (addr
> ULONG_MAX
- size
)
371 if (segment_eq(get_fs(), KERNEL_DS
))
373 #ifdef CONFIG_MTD_UCLINUX
379 if (in_mem(addr
, size
, memory_start
, memory_end
))
381 if (in_mem(addr
, size
, memory_mtd_end
, physical_mem_end
))
383 # ifndef CONFIG_ROMFS_ON_MTD
386 /* For XIP, allow user space to use pointers within the ROMFS. */
387 if (in_mem(addr
, size
, memory_mtd_start
, memory_mtd_end
))
390 if (in_mem(addr
, size
, memory_start
, physical_mem_end
))
394 if (in_mem(addr
, size
, (unsigned long)__init_begin
, (unsigned long)__init_end
))
397 if (in_mem_const(addr
, size
, L1_CODE_START
, L1_CODE_LENGTH
))
399 if (in_mem_const_off(addr
, size
, _etext_l1
- _stext_l1
, L1_CODE_START
, L1_CODE_LENGTH
))
401 if (in_mem_const_off(addr
, size
, _ebss_l1
- _sdata_l1
, L1_DATA_A_START
, L1_DATA_A_LENGTH
))
403 if (in_mem_const_off(addr
, size
, _ebss_b_l1
- _sdata_b_l1
, L1_DATA_B_START
, L1_DATA_B_LENGTH
))
405 #ifdef COREB_L1_CODE_START
406 if (in_mem_const(addr
, size
, COREB_L1_CODE_START
, COREB_L1_CODE_LENGTH
))
408 if (in_mem_const(addr
, size
, COREB_L1_SCRATCH_START
, L1_SCRATCH_LENGTH
))
410 if (in_mem_const(addr
, size
, COREB_L1_DATA_A_START
, COREB_L1_DATA_A_LENGTH
))
412 if (in_mem_const(addr
, size
, COREB_L1_DATA_B_START
, COREB_L1_DATA_B_LENGTH
))
416 #ifndef CONFIG_EXCEPTION_L1_SCRATCH
417 if (in_mem_const(addr
, size
, (unsigned long)l1_stack_base
, l1_stack_len
))
421 aret
= in_async(addr
, size
);
425 if (in_mem_const_off(addr
, size
, _ebss_l2
- _stext_l2
, L2_START
, L2_LENGTH
))
428 if (in_mem_const(addr
, size
, BOOT_ROM_START
, BOOT_ROM_LENGTH
))
430 if (in_mem_const(addr
, size
, L1_ROM_START
, L1_ROM_LENGTH
))
435 EXPORT_SYMBOL(_access_ok
);
436 #endif /* CONFIG_ACCESS_CHECK */