]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blob - arch/blackfin/kernel/setup.c
projects / mirror_ubuntu-focal-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Blackfin arch: match kernel startup messaage with new linker script
[mirror_ubuntu-focal-kernel.git] / arch / blackfin / kernel / setup.c
1 /*
2 * File: arch/blackfin/kernel/setup.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30 #include <linux/delay.h>
31 #include <linux/console.h>
32 #include <linux/bootmem.h>
33 #include <linux/seq_file.h>
34 #include <linux/cpu.h>
35 #include <linux/module.h>
36 #include <linux/tty.h>
37
38 #include <linux/ext2_fs.h>
39 #include <linux/cramfs_fs.h>
40 #include <linux/romfs_fs.h>
41
42 #include <asm/cacheflush.h>
43 #include <asm/blackfin.h>
44 #include <asm/cplbinit.h>
45
46 u16 _bfin_swrst;
47
48 unsigned long memory_start, memory_end, physical_mem_end;
49 unsigned long reserved_mem_dcache_on;
50 unsigned long reserved_mem_icache_on;
51 EXPORT_SYMBOL(memory_start);
52 EXPORT_SYMBOL(memory_end);
53 EXPORT_SYMBOL(physical_mem_end);
54 EXPORT_SYMBOL(_ramend);
55
56 #ifdef CONFIG_MTD_UCLINUX
57 unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
58 unsigned long _ebss;
59 EXPORT_SYMBOL(memory_mtd_end);
60 EXPORT_SYMBOL(memory_mtd_start);
61 EXPORT_SYMBOL(mtd_size);
62 #endif
63
64 char __initdata command_line[COMMAND_LINE_SIZE];
65
66 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
67 static void generate_cpl_tables(void);
68 #endif
69
70 void __init bf53x_cache_init(void)
71 {
72 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
73 generate_cpl_tables();
74 #endif
75
76 #ifdef CONFIG_BLKFIN_CACHE
77 bfin_icache_init();
78 printk(KERN_INFO "Instruction Cache Enabled\n");
79 #endif
80
81 #ifdef CONFIG_BLKFIN_DCACHE
82 bfin_dcache_init();
83 printk(KERN_INFO "Data Cache Enabled"
84 # if defined CONFIG_BLKFIN_WB
85 " (write-back)"
86 # elif defined CONFIG_BLKFIN_WT
87 " (write-through)"
88 # endif
89 "\n");
90 #endif
91 }
92
93 void __init bf53x_relocate_l1_mem(void)
94 {
95 unsigned long l1_code_length;
96 unsigned long l1_data_a_length;
97 unsigned long l1_data_b_length;
98
99 l1_code_length = _etext_l1 - _stext_l1;
100 if (l1_code_length > L1_CODE_LENGTH)
101 l1_code_length = L1_CODE_LENGTH;
102 /* cannot complain as printk is not available as yet.
103 * But we can continue booting and complain later!
104 */
105
106 /* Copy _stext_l1 to _etext_l1 to L1 instruction SRAM */
107 dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length);
108
109 l1_data_a_length = _ebss_l1 - _sdata_l1;
110 if (l1_data_a_length > L1_DATA_A_LENGTH)
111 l1_data_a_length = L1_DATA_A_LENGTH;
112
113 /* Copy _sdata_l1 to _ebss_l1 to L1 data bank A SRAM */
114 dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length);
115
116 l1_data_b_length = _ebss_b_l1 - _sdata_b_l1;
117 if (l1_data_b_length > L1_DATA_B_LENGTH)
118 l1_data_b_length = L1_DATA_B_LENGTH;
119
120 /* Copy _sdata_b_l1 to _ebss_b_l1 to L1 data bank B SRAM */
121 dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
122 l1_data_a_length, l1_data_b_length);
123
124 }
125
126 /*
127 * Initial parsing of the command line. Currently, we support:
128 * - Controlling the linux memory size: mem=xxx[KMG]
129 * - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
130 * $ -> reserved memory is dcacheable
131 * # -> reserved memory is icacheable
132 */
133 static __init void parse_cmdline_early(char *cmdline_p)
134 {
135 char c = ' ', *to = cmdline_p;
136 unsigned int memsize;
137 for (;;) {
138 if (c == ' ') {
139
140 if (!memcmp(to, "mem=", 4)) {
141 to += 4;
142 memsize = memparse(to, &to);
143 if (memsize)
144 _ramend = memsize;
145
146 } else if (!memcmp(to, "max_mem=", 8)) {
147 to += 8;
148 memsize = memparse(to, &to);
149 if (memsize) {
150 physical_mem_end = memsize;
151 if (*to != ' ') {
152 if (*to == '$'
153 || *(to + 1) == '$')
154 reserved_mem_dcache_on =
155 1;
156 if (*to == '#'
157 || *(to + 1) == '#')
158 reserved_mem_icache_on =
159 1;
160 }
161 }
162 }
163
164 }
165 c = *(to++);
166 if (!c)
167 break;
168 }
169 }
170
171 void __init setup_arch(char **cmdline_p)
172 {
173 int bootmap_size;
174 unsigned long l1_length, sclk, cclk;
175 #ifdef CONFIG_MTD_UCLINUX
176 unsigned long mtd_phys = 0;
177 #endif
178
179 #ifdef CONFIG_DUMMY_CONSOLE
180 conswitchp = &dummy_con;
181 #endif
182 cclk = get_cclk();
183 sclk = get_sclk();
184
185 #if !defined(CONFIG_BFIN_KERNEL_CLOCK) && defined(ANOMALY_05000273)
186 if (cclk == sclk)
187 panic("ANOMALY 05000273, SCLK can not be same as CCLK");
188 #endif
189
190 #if defined(ANOMALY_05000266)
191 bfin_read_IMDMA_D0_IRQ_STATUS();
192 bfin_read_IMDMA_D1_IRQ_STATUS();
193 #endif
194
195 #ifdef DEBUG_SERIAL_EARLY_INIT
196 bfin_console_init(); /* early console registration */
197 /* this give a chance to get printk() working before crash. */
198 #endif
199
200 #if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
201 /* we need to initialize the Flashrom device here since we might
202 * do things with flash early on in the boot
203 */
204 flash_probe();
205 #endif
206
207 #if defined(CONFIG_CMDLINE_BOOL)
208 strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
209 command_line[sizeof(command_line) - 1] = 0;
210 #endif
211
212 /* Keep a copy of command line */
213 *cmdline_p = &command_line[0];
214 memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
215 boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
216
217 /* setup memory defaults from the user config */
218 physical_mem_end = 0;
219 _ramend = CONFIG_MEM_SIZE * 1024 * 1024;
220
221 parse_cmdline_early(&command_line[0]);
222
223 if (physical_mem_end == 0)
224 physical_mem_end = _ramend;
225
226 /* by now the stack is part of the init task */
227 memory_end = _ramend - DMA_UNCACHED_REGION;
228
229 _ramstart = (unsigned long)__bss_stop;
230 memory_start = PAGE_ALIGN(_ramstart);
231
232 #if defined(CONFIG_MTD_UCLINUX)
233 /* generic memory mapped MTD driver */
234 memory_mtd_end = memory_end;
235
236 mtd_phys = _ramstart;
237 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
238
239 # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
240 if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
241 mtd_size =
242 PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
243 # endif
244
245 # if defined(CONFIG_CRAMFS)
246 if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
247 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
248 # endif
249
250 # if defined(CONFIG_ROMFS_FS)
251 if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
252 && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1)
253 mtd_size =
254 PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
255 # if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
256 /* Due to a Hardware Anomaly we need to limit the size of usable
257 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
258 * 05000263 - Hardware loop corrupted when taking an ICPLB exception
259 */
260 # if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
261 if (memory_end >= 56 * 1024 * 1024)
262 memory_end = 56 * 1024 * 1024;
263 # else
264 if (memory_end >= 60 * 1024 * 1024)
265 memory_end = 60 * 1024 * 1024;
266 # endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
267 # endif /* ANOMALY_05000263 */
268 # endif /* CONFIG_ROMFS_FS */
269
270 memory_end -= mtd_size;
271
272 if (mtd_size == 0) {
273 console_init();
274 panic("Don't boot kernel without rootfs attached.\n");
275 }
276
277 /* Relocate MTD image to the top of memory after the uncached memory area */
278 dma_memcpy((char *)memory_end, __bss_stop, mtd_size);
279
280 memory_mtd_start = memory_end;
281 _ebss = memory_mtd_start; /* define _ebss for compatible */
282 #endif /* CONFIG_MTD_UCLINUX */
283
284 #if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
285 /* Due to a Hardware Anomaly we need to limit the size of usable
286 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
287 * 05000263 - Hardware loop corrupted when taking an ICPLB exception
288 */
289 #if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
290 if (memory_end >= 56 * 1024 * 1024)
291 memory_end = 56 * 1024 * 1024;
292 #else
293 if (memory_end >= 60 * 1024 * 1024)
294 memory_end = 60 * 1024 * 1024;
295 #endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
296 printk(KERN_NOTICE "Warning: limiting memory to %liMB due to hardware anomaly 05000263\n", memory_end >> 20);
297 #endif /* ANOMALY_05000263 */
298
299 #if !defined(CONFIG_MTD_UCLINUX)
300 memory_end -= SIZE_4K; /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
301 #endif
302 init_mm.start_code = (unsigned long)_stext;
303 init_mm.end_code = (unsigned long)_etext;
304 init_mm.end_data = (unsigned long)_edata;
305 init_mm.brk = (unsigned long)0;
306
307 init_leds();
308
309 printk(KERN_INFO "Blackfin support (C) 2004-2007 Analog Devices, Inc.\n");
310 printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
311 if (bfin_revid() != bfin_compiled_revid())
312 printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
313 bfin_compiled_revid(), bfin_revid());
314 if (bfin_revid() < SUPPORTED_REVID)
315 printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
316 CPU, bfin_revid());
317 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
318
319 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu Mhz System Clock\n",
320 cclk / 1000000, sclk / 1000000);
321
322 #if defined(ANOMALY_05000273)
323 if ((cclk >> 1) <= sclk)
324 printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n");
325 #endif
326
327 printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
328 printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
329
330 printk(KERN_INFO "Memory map:\n"
331 KERN_INFO " text = 0x%p-0x%p\n"
332 KERN_INFO " rodata = 0x%p-0x%p\n"
333 KERN_INFO " data = 0x%p-0x%p\n"
334 KERN_INFO " stack = 0x%p-0x%p\n"
335 KERN_INFO " init = 0x%p-0x%p\n"
336 KERN_INFO " bss = 0x%p-0x%p\n"
337 KERN_INFO " available = 0x%p-0x%p\n"
338 #ifdef CONFIG_MTD_UCLINUX
339 KERN_INFO " rootfs = 0x%p-0x%p\n"
340 #endif
341 #if DMA_UNCACHED_REGION > 0
342 KERN_INFO " DMA Zone = 0x%p-0x%p\n"
343 #endif
344 , _stext, _etext,
345 __start_rodata, __end_rodata,
346 _sdata, _edata,
347 (void*)&init_thread_union, (void*)((int)(&init_thread_union) + 0x2000),
348 __init_begin, __init_end,
349 __bss_start, __bss_stop,
350 (void*)_ramstart, (void*)memory_end
351 #ifdef CONFIG_MTD_UCLINUX
352 , (void*)memory_mtd_start, (void*)(memory_mtd_start + mtd_size)
353 #endif
354 #if DMA_UNCACHED_REGION > 0
355 , (void*)(_ramend - DMA_UNCACHED_REGION), (void*)(_ramend)
356 #endif
357 );
358
359 /*
360 * give all the memory to the bootmap allocator, tell it to put the
361 * boot mem_map at the start of memory
362 */
363 bootmap_size = init_bootmem_node(NODE_DATA(0), memory_start >> PAGE_SHIFT, /* map goes here */
364 PAGE_OFFSET >> PAGE_SHIFT,
365 memory_end >> PAGE_SHIFT);
366 /*
367 * free the usable memory, we have to make sure we do not free
368 * the bootmem bitmap so we then reserve it after freeing it :-)
369 */
370 free_bootmem(memory_start, memory_end - memory_start);
371
372 reserve_bootmem(memory_start, bootmap_size);
373 /*
374 * get kmalloc into gear
375 */
376 paging_init();
377
378 /* check the size of the l1 area */
379 l1_length = _etext_l1 - _stext_l1;
380 if (l1_length > L1_CODE_LENGTH)
381 panic("L1 memory overflow\n");
382
383 l1_length = _ebss_l1 - _sdata_l1;
384 if (l1_length > L1_DATA_A_LENGTH)
385 panic("L1 memory overflow\n");
386
387 #ifdef BF561_FAMILY
388 _bfin_swrst = bfin_read_SICA_SWRST();
389 #else
390 _bfin_swrst = bfin_read_SWRST();
391 #endif
392
393 bf53x_cache_init();
394
395 printk(KERN_INFO "Hardware Trace Enabled\n");
396 bfin_write_TBUFCTL(0x03);
397 }
398
399 static int __init topology_init(void)
400 {
401 #if defined (CONFIG_BF561)
402 static struct cpu cpu[2];
403 register_cpu(&cpu[0], 0);
404 register_cpu(&cpu[1], 1);
405 return 0;
406 #else
407 static struct cpu cpu[1];
408 return register_cpu(cpu, 0);
409 #endif
410 }
411
412 subsys_initcall(topology_init);
413
414 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
415 static u16 __init lock_kernel_check(u32 start, u32 end)
416 {
417 if ((start <= (u32) _stext && end >= (u32) _end)
418 || (start >= (u32) _stext && end <= (u32) _end))
419 return IN_KERNEL;
420 return 0;
421 }
422
423 static unsigned short __init
424 fill_cplbtab(struct cplb_tab *table,
425 unsigned long start, unsigned long end,
426 unsigned long block_size, unsigned long cplb_data)
427 {
428 int i;
429
430 switch (block_size) {
431 case SIZE_4M:
432 i = 3;
433 break;
434 case SIZE_1M:
435 i = 2;
436 break;
437 case SIZE_4K:
438 i = 1;
439 break;
440 case SIZE_1K:
441 default:
442 i = 0;
443 break;
444 }
445
446 cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
447
448 while ((start < end) && (table->pos < table->size)) {
449
450 table->tab[table->pos++] = start;
451
452 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
453 table->tab[table->pos++] =
454 cplb_data | CPLB_LOCK | CPLB_DIRTY;
455 else
456 table->tab[table->pos++] = cplb_data;
457
458 start += block_size;
459 }
460 return 0;
461 }
462
463 static unsigned short __init
464 close_cplbtab(struct cplb_tab *table)
465 {
466
467 while (table->pos < table->size) {
468
469 table->tab[table->pos++] = 0;
470 table->tab[table->pos++] = 0; /* !CPLB_VALID */
471 }
472 return 0;
473 }
474
475 /* helper function */
476 static void __fill_code_cplbtab(struct cplb_tab *t, int i,
477 u32 a_start, u32 a_end)
478 {
479 if (cplb_data[i].psize) {
480 fill_cplbtab(t,
481 cplb_data[i].start,
482 cplb_data[i].end,
483 cplb_data[i].psize,
484 cplb_data[i].i_conf);
485 } else {
486 #if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
487 if (i == SDRAM_KERN) {
488 fill_cplbtab(t,
489 cplb_data[i].start,
490 cplb_data[i].end,
491 SIZE_4M,
492 cplb_data[i].i_conf);
493 } else {
494 #endif
495 fill_cplbtab(t,
496 cplb_data[i].start,
497 a_start,
498 SIZE_1M,
499 cplb_data[i].i_conf);
500 fill_cplbtab(t,
501 a_start,
502 a_end,
503 SIZE_4M,
504 cplb_data[i].i_conf);
505 fill_cplbtab(t, a_end,
506 cplb_data[i].end,
507 SIZE_1M,
508 cplb_data[i].i_conf);
509 }
510 }
511 }
512
513 static void __fill_data_cplbtab(struct cplb_tab *t, int i,
514 u32 a_start, u32 a_end)
515 {
516 if (cplb_data[i].psize) {
517 fill_cplbtab(t,
518 cplb_data[i].start,
519 cplb_data[i].end,
520 cplb_data[i].psize,
521 cplb_data[i].d_conf);
522 } else {
523 fill_cplbtab(t,
524 cplb_data[i].start,
525 a_start, SIZE_1M,
526 cplb_data[i].d_conf);
527 fill_cplbtab(t, a_start,
528 a_end, SIZE_4M,
529 cplb_data[i].d_conf);
530 fill_cplbtab(t, a_end,
531 cplb_data[i].end,
532 SIZE_1M,
533 cplb_data[i].d_conf);
534 }
535 }
536 static void __init generate_cpl_tables(void)
537 {
538
539 u16 i, j, process;
540 u32 a_start, a_end, as, ae, as_1m;
541
542 struct cplb_tab *t_i = NULL;
543 struct cplb_tab *t_d = NULL;
544 struct s_cplb cplb;
545
546 cplb.init_i.size = MAX_CPLBS;
547 cplb.init_d.size = MAX_CPLBS;
548 cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
549 cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
550
551 cplb.init_i.pos = 0;
552 cplb.init_d.pos = 0;
553 cplb.switch_i.pos = 0;
554 cplb.switch_d.pos = 0;
555
556 cplb.init_i.tab = icplb_table;
557 cplb.init_d.tab = dcplb_table;
558 cplb.switch_i.tab = ipdt_table;
559 cplb.switch_d.tab = dpdt_table;
560
561 cplb_data[SDRAM_KERN].end = memory_end;
562
563 #ifdef CONFIG_MTD_UCLINUX
564 cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
565 cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
566 cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
567 # if defined(CONFIG_ROMFS_FS)
568 cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
569
570 /*
571 * The ROMFS_FS size is often not multiple of 1MB.
572 * This can cause multiple CPLB sets covering the same memory area.
573 * This will then cause multiple CPLB hit exceptions.
574 * Workaround: We ensure a contiguous memory area by extending the kernel
575 * memory section over the mtd section.
576 * For ROMFS_FS memory must be covered with ICPLBs anyways.
577 * So there is no difference between kernel and mtd memory setup.
578 */
579
580 cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
581 cplb_data[SDRAM_RAM_MTD].valid = 0;
582
583 # endif
584 #else
585 cplb_data[SDRAM_RAM_MTD].valid = 0;
586 #endif
587
588 cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
589 cplb_data[SDRAM_DMAZ].end = _ramend;
590
591 cplb_data[RES_MEM].start = _ramend;
592 cplb_data[RES_MEM].end = physical_mem_end;
593
594 if (reserved_mem_dcache_on)
595 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
596 else
597 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
598
599 if (reserved_mem_icache_on)
600 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
601 else
602 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
603
604 for (i = ZERO_P; i <= L2_MEM; i++) {
605 if (!cplb_data[i].valid)
606 continue;
607
608 as_1m = cplb_data[i].start % SIZE_1M;
609
610 /*
611 * We need to make sure all sections are properly 1M aligned
612 * However between Kernel Memory and the Kernel mtd section,
613 * depending on the rootfs size, there can be overlapping
614 * memory areas.
615 */
616
617 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
618 #ifdef CONFIG_MTD_UCLINUX
619 if (i == SDRAM_RAM_MTD) {
620 if ((cplb_data[SDRAM_KERN].end + 1) >
621 cplb_data[SDRAM_RAM_MTD].start)
622 cplb_data[SDRAM_RAM_MTD].start =
623 (cplb_data[i].start &
624 (-2*SIZE_1M)) + SIZE_1M;
625 else
626 cplb_data[SDRAM_RAM_MTD].start =
627 (cplb_data[i].start &
628 (-2*SIZE_1M));
629 } else
630 #endif
631 printk(KERN_WARNING
632 "Unaligned Start of %s at 0x%X\n",
633 cplb_data[i].name, cplb_data[i].start);
634 }
635
636 as = cplb_data[i].start % SIZE_4M;
637 ae = cplb_data[i].end % SIZE_4M;
638
639 if (as)
640 a_start = cplb_data[i].start + (SIZE_4M - (as));
641 else
642 a_start = cplb_data[i].start;
643
644 a_end = cplb_data[i].end - ae;
645
646 for (j = INITIAL_T; j <= SWITCH_T; j++) {
647
648 switch (j) {
649 case INITIAL_T:
650 if (cplb_data[i].attr & INITIAL_T) {
651 t_i = &cplb.init_i;
652 t_d = &cplb.init_d;
653 process = 1;
654 } else
655 process = 0;
656 break;
657 case SWITCH_T:
658 if (cplb_data[i].attr & SWITCH_T) {
659 t_i = &cplb.switch_i;
660 t_d = &cplb.switch_d;
661 process = 1;
662 } else
663 process = 0;
664 break;
665 default:
666 process = 0;
667 break;
668 }
669
670 if (!process)
671 continue;
672 if (cplb_data[i].attr & I_CPLB)
673 __fill_code_cplbtab(t_i, i, a_start, a_end);
674
675 if (cplb_data[i].attr & D_CPLB)
676 __fill_data_cplbtab(t_d, i, a_start, a_end);
677 }
678 }
679
680 /* close tables */
681
682 close_cplbtab(&cplb.init_i);
683 close_cplbtab(&cplb.init_d);
684
685 cplb.init_i.tab[cplb.init_i.pos] = -1;
686 cplb.init_d.tab[cplb.init_d.pos] = -1;
687 cplb.switch_i.tab[cplb.switch_i.pos] = -1;
688 cplb.switch_d.tab[cplb.switch_d.pos] = -1;
689
690 }
691
692 #endif
693
694 static u_long get_vco(void)
695 {
696 u_long msel;
697 u_long vco;
698
699 msel = (bfin_read_PLL_CTL() >> 9) & 0x3F;
700 if (0 == msel)
701 msel = 64;
702
703 vco = CONFIG_CLKIN_HZ;
704 vco >>= (1 & bfin_read_PLL_CTL()); /* DF bit */
705 vco = msel * vco;
706 return vco;
707 }
708
709 /*Get the Core clock*/
710 u_long get_cclk(void)
711 {
712 u_long csel, ssel;
713 if (bfin_read_PLL_STAT() & 0x1)
714 return CONFIG_CLKIN_HZ;
715
716 ssel = bfin_read_PLL_DIV();
717 csel = ((ssel >> 4) & 0x03);
718 ssel &= 0xf;
719 if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
720 return get_vco() / ssel;
721 return get_vco() >> csel;
722 }
723
724 EXPORT_SYMBOL(get_cclk);
725
726 /* Get the System clock */
727 u_long get_sclk(void)
728 {
729 u_long ssel;
730
731 if (bfin_read_PLL_STAT() & 0x1)
732 return CONFIG_CLKIN_HZ;
733
734 ssel = (bfin_read_PLL_DIV() & 0xf);
735 if (0 == ssel) {
736 printk(KERN_WARNING "Invalid System Clock\n");
737 ssel = 1;
738 }
739
740 return get_vco() / ssel;
741 }
742
743 EXPORT_SYMBOL(get_sclk);
744
745 /*
746 * Get CPU information for use by the procfs.
747 */
748 static int show_cpuinfo(struct seq_file *m, void *v)
749 {
750 char *cpu, *mmu, *fpu, *name;
751 uint32_t revid;
752
753 u_long cclk = 0, sclk = 0;
754 u_int dcache_size = 0, dsup_banks = 0;
755
756 cpu = CPU;
757 mmu = "none";
758 fpu = "none";
759 revid = bfin_revid();
760 name = bfin_board_name;
761
762 cclk = get_cclk();
763 sclk = get_sclk();
764
765 seq_printf(m, "CPU:\t\tADSP-%s Rev. 0.%d\n"
766 "MMU:\t\t%s\n"
767 "FPU:\t\t%s\n"
768 "Core Clock:\t%9lu Hz\n"
769 "System Clock:\t%9lu Hz\n"
770 "BogoMips:\t%lu.%02lu\n"
771 "Calibration:\t%lu loops\n",
772 cpu, revid, mmu, fpu,
773 cclk,
774 sclk,
775 (loops_per_jiffy * HZ) / 500000,
776 ((loops_per_jiffy * HZ) / 5000) % 100,
777 (loops_per_jiffy * HZ));
778 seq_printf(m, "Board Name:\t%s\n", name);
779 seq_printf(m, "Board Memory:\t%ld MB\n", physical_mem_end >> 20);
780 seq_printf(m, "Kernel Memory:\t%ld MB\n", (unsigned long)_ramend >> 20);
781 if (bfin_read_IMEM_CONTROL() & (ENICPLB | IMC))
782 seq_printf(m, "I-CACHE:\tON\n");
783 else
784 seq_printf(m, "I-CACHE:\tOFF\n");
785 if ((bfin_read_DMEM_CONTROL()) & (ENDCPLB | DMC_ENABLE))
786 seq_printf(m, "D-CACHE:\tON"
787 #if defined CONFIG_BLKFIN_WB
788 " (write-back)"
789 #elif defined CONFIG_BLKFIN_WT
790 " (write-through)"
791 #endif
792 "\n");
793 else
794 seq_printf(m, "D-CACHE:\tOFF\n");
795
796
797 switch(bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) {
798 case ACACHE_BSRAM:
799 seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tSRAM\n");
800 dcache_size = 16;
801 dsup_banks = 1;
802 break;
803 case ACACHE_BCACHE:
804 seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tCACHE\n");
805 dcache_size = 32;
806 dsup_banks = 2;
807 break;
808 case ASRAM_BSRAM:
809 seq_printf(m, "DBANK-A:\tSRAM\n" "DBANK-B:\tSRAM\n");
810 dcache_size = 0;
811 dsup_banks = 0;
812 break;
813 default:
814 break;
815 }
816
817
818 seq_printf(m, "I-CACHE Size:\t%dKB\n", BLKFIN_ICACHESIZE / 1024);
819 seq_printf(m, "D-CACHE Size:\t%dKB\n", dcache_size);
820 seq_printf(m, "I-CACHE Setup:\t%d Sub-banks/%d Ways, %d Lines/Way\n",
821 BLKFIN_ISUBBANKS, BLKFIN_IWAYS, BLKFIN_ILINES);
822 seq_printf(m,
823 "D-CACHE Setup:\t%d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
824 dsup_banks, BLKFIN_DSUBBANKS, BLKFIN_DWAYS,
825 BLKFIN_DLINES);
826 #ifdef CONFIG_BLKFIN_CACHE_LOCK
827 switch (read_iloc()) {
828 case WAY0_L:
829 seq_printf(m, "Way0 Locked-Down\n");
830 break;
831 case WAY1_L:
832 seq_printf(m, "Way1 Locked-Down\n");
833 break;
834 case WAY01_L:
835 seq_printf(m, "Way0,Way1 Locked-Down\n");
836 break;
837 case WAY2_L:
838 seq_printf(m, "Way2 Locked-Down\n");
839 break;
840 case WAY02_L:
841 seq_printf(m, "Way0,Way2 Locked-Down\n");
842 break;
843 case WAY12_L:
844 seq_printf(m, "Way1,Way2 Locked-Down\n");
845 break;
846 case WAY012_L:
847 seq_printf(m, "Way0,Way1 & Way2 Locked-Down\n");
848 break;
849 case WAY3_L:
850 seq_printf(m, "Way3 Locked-Down\n");
851 break;
852 case WAY03_L:
853 seq_printf(m, "Way0,Way3 Locked-Down\n");
854 break;
855 case WAY13_L:
856 seq_printf(m, "Way1,Way3 Locked-Down\n");
857 break;
858 case WAY013_L:
859 seq_printf(m, "Way 0,Way1,Way3 Locked-Down\n");
860 break;
861 case WAY32_L:
862 seq_printf(m, "Way3,Way2 Locked-Down\n");
863 break;
864 case WAY320_L:
865 seq_printf(m, "Way3,Way2,Way0 Locked-Down\n");
866 break;
867 case WAY321_L:
868 seq_printf(m, "Way3,Way2,Way1 Locked-Down\n");
869 break;
870 case WAYALL_L:
871 seq_printf(m, "All Ways are locked\n");
872 break;
873 default:
874 seq_printf(m, "No Ways are locked\n");
875 }
876 #endif
877 return 0;
878 }
879
880 static void *c_start(struct seq_file *m, loff_t *pos)
881 {
882 return *pos < NR_CPUS ? ((void *)0x12345678) : NULL;
883 }
884
885 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
886 {
887 ++*pos;
888 return c_start(m, pos);
889 }
890
891 static void c_stop(struct seq_file *m, void *v)
892 {
893 }
894
895 struct seq_operations cpuinfo_op = {
896 .start = c_start,
897 .next = c_next,
898 .stop = c_stop,
899 .show = show_cpuinfo,
900 };
901
902 void __init cmdline_init(const char *r0)
903 {
904 if (r0)
905 strncpy(command_line, r0, COMMAND_LINE_SIZE);
906 }
Ubuntu Focal Linux kernel mirror