1 /* provide some functions which dump the trace buffer, in a nice way for people
2 * to read it, and understand what is going on
4 * Copyright 2004-2010 Analog Devices Inc.
6 * Licensed under the GPL-2 or later
9 #include <linux/kernel.h>
10 #include <linux/hardirq.h>
11 #include <linux/thread_info.h>
13 #include <linux/oom.h>
14 #include <linux/sched/signal.h>
15 #include <linux/sched/debug.h>
16 #include <linux/uaccess.h>
17 #include <linux/module.h>
18 #include <linux/kallsyms.h>
19 #include <linux/err.h>
21 #include <linux/irq.h>
23 #include <asm/trace.h>
24 #include <asm/fixed_code.h>
25 #include <asm/traps.h>
26 #include <asm/irq_handler.h>
29 void decode_address(char *buf
, unsigned long address
)
31 struct task_struct
*p
;
36 #ifdef CONFIG_KALLSYMS
37 unsigned long symsize
;
44 buf
+= sprintf(buf
, "<0x%08lx> ", address
);
46 #ifdef CONFIG_KALLSYMS
47 /* look up the address and see if we are in kernel space */
48 symname
= kallsyms_lookup(address
, &symsize
, &offset
, &modname
, namebuf
);
51 /* yeah! kernel space! */
54 sprintf(buf
, "{ %s%s%s%s + 0x%lx }",
55 delim
, modname
, delim
, symname
,
56 (unsigned long)offset
);
61 if (address
>= FIXED_CODE_START
&& address
< FIXED_CODE_END
) {
62 /* Problem in fixed code section? */
63 strcat(buf
, "/* Maybe fixed code section */");
66 } else if (address
< CONFIG_BOOT_LOAD
) {
67 /* Problem somewhere before the kernel start address */
68 strcat(buf
, "/* Maybe null pointer? */");
71 } else if (address
>= COREMMR_BASE
) {
72 strcat(buf
, "/* core mmrs */");
75 } else if (address
>= SYSMMR_BASE
) {
76 strcat(buf
, "/* system mmrs */");
79 } else if (address
>= L1_ROM_START
&& address
< L1_ROM_START
+ L1_ROM_LENGTH
) {
80 strcat(buf
, "/* on-chip L1 ROM */");
83 } else if (address
>= L1_SCRATCH_START
&& address
< L1_SCRATCH_START
+ L1_SCRATCH_LENGTH
) {
84 strcat(buf
, "/* on-chip scratchpad */");
87 } else if (address
>= physical_mem_end
&& address
< ASYNC_BANK0_BASE
) {
88 strcat(buf
, "/* unconnected memory */");
91 } else if (address
>= ASYNC_BANK3_BASE
+ ASYNC_BANK3_SIZE
&& address
< BOOT_ROM_START
) {
92 strcat(buf
, "/* reserved memory */");
95 } else if (address
>= L1_DATA_A_START
&& address
< L1_DATA_A_START
+ L1_DATA_A_LENGTH
) {
96 strcat(buf
, "/* on-chip Data Bank A */");
99 } else if (address
>= L1_DATA_B_START
&& address
< L1_DATA_B_START
+ L1_DATA_B_LENGTH
) {
100 strcat(buf
, "/* on-chip Data Bank B */");
105 * Don't walk any of the vmas if we are oopsing, it has been known
106 * to cause problems - corrupt vmas (kernel crashes) cause double faults
108 if (oops_in_progress
) {
109 strcat(buf
, "/* kernel dynamic memory (maybe user-space) */");
113 /* looks like we're off in user-land, so let's walk all the
114 * mappings of all our processes and see if we can't be a whee
117 read_lock(&tasklist_lock
);
118 for_each_process(p
) {
119 struct task_struct
*t
;
121 t
= find_lock_task_mm(p
);
126 if (!down_read_trylock(&mm
->mmap_sem
))
129 for (n
= rb_first(&mm
->mm_rb
); n
; n
= rb_next(n
)) {
130 struct vm_area_struct
*vma
;
132 vma
= rb_entry(n
, struct vm_area_struct
, vm_rb
);
134 if (address
>= vma
->vm_start
&& address
< vma
->vm_end
) {
136 char *name
= t
->comm
;
137 struct file
*file
= vma
->vm_file
;
140 char *d_name
= file_path(file
, _tmpbuf
,
146 /* FLAT does not have its text aligned to the start of
147 * the map while FDPIC ELF does ...
150 /* before we can check flat/fdpic, we need to
151 * make sure current is valid
153 if ((unsigned long)current
>= FIXED_CODE_START
&&
154 !((unsigned long)current
& 0x3)) {
156 (address
> current
->mm
->start_code
) &&
157 (address
< current
->mm
->end_code
))
158 offset
= address
- current
->mm
->start_code
;
160 offset
= (address
- vma
->vm_start
) +
161 (vma
->vm_pgoff
<< PAGE_SHIFT
);
163 sprintf(buf
, "[ %s + 0x%lx ]", name
, offset
);
165 sprintf(buf
, "[ %s vma:0x%lx-0x%lx]",
166 name
, vma
->vm_start
, vma
->vm_end
);
168 up_read(&mm
->mmap_sem
);
172 sprintf(buf
, "[ %s ] dynamic memory", name
);
178 up_read(&mm
->mmap_sem
);
184 * we were unable to find this address anywhere,
185 * or some MMs were skipped because they were in use.
187 sprintf(buf
, "/* kernel dynamic memory */");
190 read_unlock(&tasklist_lock
);
193 #define EXPAND_LEN ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 256 - 1)
196 * Similar to get_user, do some address checking, then dereference
197 * Return true on success, false on bad address
199 bool get_mem16(unsigned short *val
, unsigned short *address
)
201 unsigned long addr
= (unsigned long)address
;
203 /* Check for odd addresses */
207 switch (bfin_mem_access_type(addr
, 2)) {
208 case BFIN_MEM_ACCESS_CORE
:
209 case BFIN_MEM_ACCESS_CORE_ONLY
:
212 case BFIN_MEM_ACCESS_DMA
:
213 dma_memcpy(val
, address
, 2);
215 case BFIN_MEM_ACCESS_ITEST
:
216 isram_memcpy(val
, address
, 2);
218 default: /* invalid access */
223 bool get_instruction(unsigned int *val
, unsigned short *address
)
225 unsigned long addr
= (unsigned long)address
;
226 unsigned short opcode0
, opcode1
;
228 /* Check for odd addresses */
232 /* MMR region will never have instructions */
233 if (addr
>= SYSMMR_BASE
)
236 /* Scratchpad will never have instructions */
237 if (addr
>= L1_SCRATCH_START
&& addr
< L1_SCRATCH_START
+ L1_SCRATCH_LENGTH
)
240 /* Data banks will never have instructions */
241 if (addr
>= BOOT_ROM_START
+ BOOT_ROM_LENGTH
&& addr
< L1_CODE_START
)
244 if (!get_mem16(&opcode0
, address
))
247 /* was this a 32-bit instruction? If so, get the next 16 bits */
248 if ((opcode0
& 0xc000) == 0xc000) {
249 if (!get_mem16(&opcode1
, address
+ 1))
251 *val
= (opcode0
<< 16) + opcode1
;
258 #if defined(CONFIG_DEBUG_BFIN_HWTRACE_ON)
260 * decode the instruction if we are printing out the trace, as it
261 * makes things easier to follow, without running it through objdump
262 * Decode the change of flow, and the common load/store instructions
263 * which are the main cause for faults, and discontinuities in the trace
267 #define ProgCtrl_opcode 0x0000
268 #define ProgCtrl_poprnd_bits 0
269 #define ProgCtrl_poprnd_mask 0xf
270 #define ProgCtrl_prgfunc_bits 4
271 #define ProgCtrl_prgfunc_mask 0xf
272 #define ProgCtrl_code_bits 8
273 #define ProgCtrl_code_mask 0xff
275 static void decode_ProgCtrl_0(unsigned int opcode
)
277 int poprnd
= ((opcode
>> ProgCtrl_poprnd_bits
) & ProgCtrl_poprnd_mask
);
278 int prgfunc
= ((opcode
>> ProgCtrl_prgfunc_bits
) & ProgCtrl_prgfunc_mask
);
280 if (prgfunc
== 0 && poprnd
== 0)
282 else if (prgfunc
== 1 && poprnd
== 0)
284 else if (prgfunc
== 1 && poprnd
== 1)
286 else if (prgfunc
== 1 && poprnd
== 2)
288 else if (prgfunc
== 1 && poprnd
== 3)
290 else if (prgfunc
== 1 && poprnd
== 4)
292 else if (prgfunc
== 2 && poprnd
== 0)
294 else if (prgfunc
== 2 && poprnd
== 3)
296 else if (prgfunc
== 2 && poprnd
== 4)
298 else if (prgfunc
== 2 && poprnd
== 5)
300 else if (prgfunc
== 3)
301 pr_cont("CLI R%i", poprnd
);
302 else if (prgfunc
== 4)
303 pr_cont("STI R%i", poprnd
);
304 else if (prgfunc
== 5)
305 pr_cont("JUMP (P%i)", poprnd
);
306 else if (prgfunc
== 6)
307 pr_cont("CALL (P%i)", poprnd
);
308 else if (prgfunc
== 7)
309 pr_cont("CALL (PC + P%i)", poprnd
);
310 else if (prgfunc
== 8)
311 pr_cont("JUMP (PC + P%i", poprnd
);
312 else if (prgfunc
== 9)
313 pr_cont("RAISE %i", poprnd
);
314 else if (prgfunc
== 10)
315 pr_cont("EXCPT %i", poprnd
);
317 pr_cont("0x%04x", opcode
);
321 #define BRCC_opcode 0x1000
322 #define BRCC_offset_bits 0
323 #define BRCC_offset_mask 0x3ff
324 #define BRCC_B_bits 10
325 #define BRCC_B_mask 0x1
326 #define BRCC_T_bits 11
327 #define BRCC_T_mask 0x1
328 #define BRCC_code_bits 12
329 #define BRCC_code_mask 0xf
331 static void decode_BRCC_0(unsigned int opcode
)
333 int B
= ((opcode
>> BRCC_B_bits
) & BRCC_B_mask
);
334 int T
= ((opcode
>> BRCC_T_bits
) & BRCC_T_mask
);
336 pr_cont("IF %sCC JUMP pcrel %s", T
? "" : "!", B
? "(BP)" : "");
339 #define CALLa_opcode 0xe2000000
340 #define CALLa_addr_bits 0
341 #define CALLa_addr_mask 0xffffff
342 #define CALLa_S_bits 24
343 #define CALLa_S_mask 0x1
344 #define CALLa_code_bits 25
345 #define CALLa_code_mask 0x7f
347 static void decode_CALLa_0(unsigned int opcode
)
349 int S
= ((opcode
>> (CALLa_S_bits
- 16)) & CALLa_S_mask
);
352 pr_cont("CALL pcrel");
357 #define LoopSetup_opcode 0xe0800000
358 #define LoopSetup_eoffset_bits 0
359 #define LoopSetup_eoffset_mask 0x3ff
360 #define LoopSetup_dontcare_bits 10
361 #define LoopSetup_dontcare_mask 0x3
362 #define LoopSetup_reg_bits 12
363 #define LoopSetup_reg_mask 0xf
364 #define LoopSetup_soffset_bits 16
365 #define LoopSetup_soffset_mask 0xf
366 #define LoopSetup_c_bits 20
367 #define LoopSetup_c_mask 0x1
368 #define LoopSetup_rop_bits 21
369 #define LoopSetup_rop_mask 0x3
370 #define LoopSetup_code_bits 23
371 #define LoopSetup_code_mask 0x1ff
373 static void decode_LoopSetup_0(unsigned int opcode
)
375 int c
= ((opcode
>> LoopSetup_c_bits
) & LoopSetup_c_mask
);
376 int reg
= ((opcode
>> LoopSetup_reg_bits
) & LoopSetup_reg_mask
);
377 int rop
= ((opcode
>> LoopSetup_rop_bits
) & LoopSetup_rop_mask
);
379 pr_cont("LSETUP <> LC%i", c
);
381 pr_cont("= P%i", reg
);
386 #define DspLDST_opcode 0x9c00
387 #define DspLDST_reg_bits 0
388 #define DspLDST_reg_mask 0x7
389 #define DspLDST_i_bits 3
390 #define DspLDST_i_mask 0x3
391 #define DspLDST_m_bits 5
392 #define DspLDST_m_mask 0x3
393 #define DspLDST_aop_bits 7
394 #define DspLDST_aop_mask 0x3
395 #define DspLDST_W_bits 9
396 #define DspLDST_W_mask 0x1
397 #define DspLDST_code_bits 10
398 #define DspLDST_code_mask 0x3f
400 static void decode_dspLDST_0(unsigned int opcode
)
402 int i
= ((opcode
>> DspLDST_i_bits
) & DspLDST_i_mask
);
403 int m
= ((opcode
>> DspLDST_m_bits
) & DspLDST_m_mask
);
404 int W
= ((opcode
>> DspLDST_W_bits
) & DspLDST_W_mask
);
405 int aop
= ((opcode
>> DspLDST_aop_bits
) & DspLDST_aop_mask
);
406 int reg
= ((opcode
>> DspLDST_reg_bits
) & DspLDST_reg_mask
);
435 pr_cont(" = R%i", reg
);
447 #define LDST_opcode 0x9000
448 #define LDST_reg_bits 0
449 #define LDST_reg_mask 0x7
450 #define LDST_ptr_bits 3
451 #define LDST_ptr_mask 0x7
452 #define LDST_Z_bits 6
453 #define LDST_Z_mask 0x1
454 #define LDST_aop_bits 7
455 #define LDST_aop_mask 0x3
456 #define LDST_W_bits 9
457 #define LDST_W_mask 0x1
458 #define LDST_sz_bits 10
459 #define LDST_sz_mask 0x3
460 #define LDST_code_bits 12
461 #define LDST_code_mask 0xf
463 static void decode_LDST_0(unsigned int opcode
)
465 int Z
= ((opcode
>> LDST_Z_bits
) & LDST_Z_mask
);
466 int W
= ((opcode
>> LDST_W_bits
) & LDST_W_mask
);
467 int sz
= ((opcode
>> LDST_sz_bits
) & LDST_sz_mask
);
468 int aop
= ((opcode
>> LDST_aop_bits
) & LDST_aop_mask
);
469 int reg
= ((opcode
>> LDST_reg_bits
) & LDST_reg_mask
);
470 int ptr
= ((opcode
>> LDST_ptr_bits
) & LDST_ptr_mask
);
473 pr_cont("%s%i = ", (sz
== 0 && Z
== 1) ? "P" : "R", reg
);
484 pr_cont("[P%i", ptr
);
497 pr_cont(" = %s%i ", (sz
== 0 && Z
== 1) ? "P" : "R", reg
);
507 #define LDSTii_opcode 0xa000
508 #define LDSTii_reg_bit 0
509 #define LDSTii_reg_mask 0x7
510 #define LDSTii_ptr_bit 3
511 #define LDSTii_ptr_mask 0x7
512 #define LDSTii_offset_bit 6
513 #define LDSTii_offset_mask 0xf
514 #define LDSTii_op_bit 10
515 #define LDSTii_op_mask 0x3
516 #define LDSTii_W_bit 12
517 #define LDSTii_W_mask 0x1
518 #define LDSTii_code_bit 13
519 #define LDSTii_code_mask 0x7
521 static void decode_LDSTii_0(unsigned int opcode
)
523 int reg
= ((opcode
>> LDSTii_reg_bit
) & LDSTii_reg_mask
);
524 int ptr
= ((opcode
>> LDSTii_ptr_bit
) & LDSTii_ptr_mask
);
525 int offset
= ((opcode
>> LDSTii_offset_bit
) & LDSTii_offset_mask
);
526 int op
= ((opcode
>> LDSTii_op_bit
) & LDSTii_op_mask
);
527 int W
= ((opcode
>> LDSTii_W_bit
) & LDSTii_W_mask
);
530 pr_cont("%s%i = %s[P%i + %i]", op
== 3 ? "R" : "P", reg
,
531 op
== 1 || op
== 2 ? "" : "W", ptr
, offset
);
537 pr_cont("%s[P%i + %i] = %s%i", op
== 0 ? "" : "W", ptr
,
538 offset
, op
== 3 ? "P" : "R", reg
);
542 #define LDSTidxI_opcode 0xe4000000
543 #define LDSTidxI_offset_bits 0
544 #define LDSTidxI_offset_mask 0xffff
545 #define LDSTidxI_reg_bits 16
546 #define LDSTidxI_reg_mask 0x7
547 #define LDSTidxI_ptr_bits 19
548 #define LDSTidxI_ptr_mask 0x7
549 #define LDSTidxI_sz_bits 22
550 #define LDSTidxI_sz_mask 0x3
551 #define LDSTidxI_Z_bits 24
552 #define LDSTidxI_Z_mask 0x1
553 #define LDSTidxI_W_bits 25
554 #define LDSTidxI_W_mask 0x1
555 #define LDSTidxI_code_bits 26
556 #define LDSTidxI_code_mask 0x3f
558 static void decode_LDSTidxI_0(unsigned int opcode
)
560 int Z
= ((opcode
>> LDSTidxI_Z_bits
) & LDSTidxI_Z_mask
);
561 int W
= ((opcode
>> LDSTidxI_W_bits
) & LDSTidxI_W_mask
);
562 int sz
= ((opcode
>> LDSTidxI_sz_bits
) & LDSTidxI_sz_mask
);
563 int reg
= ((opcode
>> LDSTidxI_reg_bits
) & LDSTidxI_reg_mask
);
564 int ptr
= ((opcode
>> LDSTidxI_ptr_bits
) & LDSTidxI_ptr_mask
);
565 int offset
= ((opcode
>> LDSTidxI_offset_bits
) & LDSTidxI_offset_mask
);
568 pr_cont("%s%i = ", sz
== 0 && Z
== 1 ? "P" : "R", reg
);
575 pr_cont("[P%i + %s0x%x]", ptr
, offset
& 0x20 ? "-" : "",
576 (offset
& 0x1f) << 2);
578 if (W
== 0 && sz
!= 0) {
586 pr_cont("= %s%i", (sz
== 0 && Z
== 1) ? "P" : "R", reg
);
590 static void decode_opcode(unsigned int opcode
)
593 if (opcode
== BFIN_BUG_OPCODE
)
597 if ((opcode
& 0xffffff00) == ProgCtrl_opcode
)
598 decode_ProgCtrl_0(opcode
);
599 else if ((opcode
& 0xfffff000) == BRCC_opcode
)
600 decode_BRCC_0(opcode
);
601 else if ((opcode
& 0xfffff000) == 0x2000)
603 else if ((opcode
& 0xfe000000) == CALLa_opcode
)
604 decode_CALLa_0(opcode
);
605 else if ((opcode
& 0xff8000C0) == LoopSetup_opcode
)
606 decode_LoopSetup_0(opcode
);
607 else if ((opcode
& 0xfffffc00) == DspLDST_opcode
)
608 decode_dspLDST_0(opcode
);
609 else if ((opcode
& 0xfffff000) == LDST_opcode
)
610 decode_LDST_0(opcode
);
611 else if ((opcode
& 0xffffe000) == LDSTii_opcode
)
612 decode_LDSTii_0(opcode
);
613 else if ((opcode
& 0xfc000000) == LDSTidxI_opcode
)
614 decode_LDSTidxI_0(opcode
);
615 else if (opcode
& 0xffff0000)
616 pr_cont("0x%08x", opcode
);
618 pr_cont("0x%04x", opcode
);
621 #define BIT_MULTI_INS 0x08000000
622 static void decode_instruction(unsigned short *address
)
626 if (!get_instruction(&opcode
, address
))
629 decode_opcode(opcode
);
631 /* If things are a 32-bit instruction, it has the possibility of being
632 * a multi-issue instruction (a 32-bit, and 2 16 bit instrucitions)
633 * This test collidates with the unlink instruction, so disallow that
635 if ((opcode
& 0xc0000000) == 0xc0000000 &&
636 (opcode
& BIT_MULTI_INS
) &&
637 (opcode
& 0xe8000000) != 0xe8000000) {
639 if (!get_instruction(&opcode
, address
+ 2))
641 decode_opcode(opcode
);
643 if (!get_instruction(&opcode
, address
+ 3))
645 decode_opcode(opcode
);
650 void dump_bfin_trace_buffer(void)
652 #ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
653 int tflags
, i
= 0, fault
= 0;
655 unsigned short *addr
;
656 unsigned int cpu
= raw_smp_processor_id();
657 #ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
661 trace_buffer_save(tflags
);
663 pr_notice("Hardware Trace:\n");
665 #ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
666 pr_notice("WARNING: Expanded trace turned on - can not trace exceptions\n");
669 if (likely(bfin_read_TBUFSTAT() & TBUFCNT
)) {
670 for (; bfin_read_TBUFSTAT() & TBUFCNT
; i
++) {
671 addr
= (unsigned short *)bfin_read_TBUF();
672 decode_address(buf
, (unsigned long)addr
);
673 pr_notice("%4i Target : %s\n", i
, buf
);
674 /* Normally, the faulting instruction doesn't go into
675 * the trace buffer, (since it doesn't commit), so
676 * we print out the fault address here
678 if (!fault
&& addr
== ((unsigned short *)evt_ivhw
)) {
679 addr
= (unsigned short *)bfin_read_TBUF();
680 decode_address(buf
, (unsigned long)addr
);
681 pr_notice(" FAULT : %s ", buf
);
682 decode_instruction(addr
);
687 if (!fault
&& addr
== (unsigned short *)trap
&&
688 (cpu_pda
[cpu
].seqstat
& SEQSTAT_EXCAUSE
) > VEC_EXCPT15
) {
689 decode_address(buf
, cpu_pda
[cpu
].icplb_fault_addr
);
690 pr_notice(" FAULT : %s ", buf
);
691 decode_instruction((unsigned short *)cpu_pda
[cpu
].icplb_fault_addr
);
695 addr
= (unsigned short *)bfin_read_TBUF();
696 decode_address(buf
, (unsigned long)addr
);
697 pr_notice(" Source : %s ", buf
);
698 decode_instruction(addr
);
703 #ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
704 if (trace_buff_offset
)
705 index
= trace_buff_offset
/ 4;
709 j
= (1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN
) * 128;
711 decode_address(buf
, software_trace_buff
[index
]);
712 pr_notice("%4i Target : %s\n", i
, buf
);
716 decode_address(buf
, software_trace_buff
[index
]);
717 pr_notice(" Source : %s ", buf
);
718 decode_instruction((unsigned short *)software_trace_buff
[index
]);
728 trace_buffer_restore(tflags
);
731 EXPORT_SYMBOL(dump_bfin_trace_buffer
);
733 void dump_bfin_process(struct pt_regs
*fp
)
735 /* We should be able to look at fp->ipend, but we don't push it on the
736 * stack all the time, so do this until we fix that */
737 unsigned int context
= bfin_read_IPEND();
739 if (oops_in_progress
)
740 pr_emerg("Kernel OOPS in progress\n");
742 if (context
& 0x0020 && (fp
->seqstat
& SEQSTAT_EXCAUSE
) == VEC_HWERR
)
743 pr_notice("HW Error context\n");
744 else if (context
& 0x0020)
745 pr_notice("Deferred Exception context\n");
746 else if (context
& 0x3FC0)
747 pr_notice("Interrupt context\n");
748 else if (context
& 0x4000)
749 pr_notice("Deferred Interrupt context\n");
750 else if (context
& 0x8000)
751 pr_notice("Kernel process context\n");
753 /* Because we are crashing, and pointers could be bad, we check things
754 * pretty closely before we use them
756 if ((unsigned long)current
>= FIXED_CODE_START
&&
757 !((unsigned long)current
& 0x3) && current
->pid
) {
758 pr_notice("CURRENT PROCESS:\n");
759 if (current
->comm
>= (char *)FIXED_CODE_START
)
760 pr_notice("COMM=%s PID=%d",
761 current
->comm
, current
->pid
);
763 pr_notice("COMM= invalid");
765 pr_cont(" CPU=%d\n", current_thread_info()->cpu
);
766 if (!((unsigned long)current
->mm
& 0x3) &&
767 (unsigned long)current
->mm
>= FIXED_CODE_START
) {
768 pr_notice("TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n",
769 (void *)current
->mm
->start_code
,
770 (void *)current
->mm
->end_code
,
771 (void *)current
->mm
->start_data
,
772 (void *)current
->mm
->end_data
);
773 pr_notice(" BSS = 0x%p-0x%p USER-STACK = 0x%p\n\n",
774 (void *)current
->mm
->end_data
,
775 (void *)current
->mm
->brk
,
776 (void *)current
->mm
->start_stack
);
778 pr_notice("invalid mm\n");
780 pr_notice("No Valid process in current context\n");
783 void dump_bfin_mem(struct pt_regs
*fp
)
785 unsigned short *addr
, *erraddr
, val
= 0, err
= 0;
786 char sti
= 0, buf
[6];
788 erraddr
= (void *)fp
->pc
;
790 pr_notice("return address: [0x%p]; contents of:", erraddr
);
792 for (addr
= (unsigned short *)((unsigned long)erraddr
& ~0xF) - 0x10;
793 addr
< (unsigned short *)((unsigned long)erraddr
& ~0xF) + 0x10;
795 if (!((unsigned long)addr
& 0xF))
796 pr_notice("0x%p: ", addr
);
798 if (!get_mem16(&val
, addr
)) {
800 sprintf(buf
, "????");
802 sprintf(buf
, "%04x", val
);
804 if (addr
== erraddr
) {
805 pr_cont("[%s]", buf
);
808 pr_cont(" %s ", buf
);
810 /* Do any previous instructions turn on interrupts? */
811 if (addr
<= erraddr
&& /* in the past */
812 ((val
>= 0x0040 && val
<= 0x0047) || /* STI instruction */
813 val
== 0x017b)) /* [SP++] = RETI */
819 /* Hardware error interrupts can be deferred */
820 if (unlikely(sti
&& (fp
->seqstat
& SEQSTAT_EXCAUSE
) == VEC_HWERR
&&
822 pr_notice("Looks like this was a deferred error - sorry\n");
823 #ifndef CONFIG_DEBUG_HWERR
824 pr_notice("The remaining message may be meaningless\n");
825 pr_notice("You should enable CONFIG_DEBUG_HWERR to get a better idea where it came from\n");
827 /* If we are handling only one peripheral interrupt
828 * and current mm and pid are valid, and the last error
829 * was in that user space process's text area
830 * print it out - because that is where the problem exists
832 if ((!(((fp
)->ipend
& ~0x30) & (((fp
)->ipend
& ~0x30) - 1))) &&
833 (current
->pid
&& current
->mm
)) {
834 /* And the last RETI points to the current userspace context */
835 if ((fp
+ 1)->pc
>= current
->mm
->start_code
&&
836 (fp
+ 1)->pc
<= current
->mm
->end_code
) {
837 pr_notice("It might be better to look around here :\n");
838 pr_notice("-------------------------------------------\n");
840 pr_notice("-------------------------------------------\n");
847 void show_regs(struct pt_regs
*fp
)
850 struct irqaction
*action
;
852 unsigned long flags
= 0;
853 unsigned int cpu
= raw_smp_processor_id();
854 unsigned char in_atomic
= (bfin_read_IPEND() & 0x10) || in_atomic();
857 show_regs_print_info(KERN_NOTICE
);
859 if (CPUID
!= bfin_cpuid())
860 pr_notice("Compiled for cpu family 0x%04x (Rev %d), "
861 "but running on:0x%04x (Rev %d)\n",
862 CPUID
, bfin_compiled_revid(), bfin_cpuid(), bfin_revid());
864 pr_notice("ADSP-%s-0.%d",
865 CPU
, bfin_compiled_revid());
867 if (bfin_compiled_revid() != bfin_revid())
868 pr_cont("(Detected 0.%d)", bfin_revid());
870 pr_cont(" %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n",
871 get_cclk()/1000000, get_sclk()/1000000,
879 pr_notice("%s", linux_banner
);
881 pr_notice("\nSEQUENCER STATUS:\t\t%s\n", print_tainted());
882 pr_notice(" SEQSTAT: %08lx IPEND: %04lx IMASK: %04lx SYSCFG: %04lx\n",
883 (long)fp
->seqstat
, fp
->ipend
, cpu_pda
[raw_smp_processor_id()].ex_imask
, fp
->syscfg
);
884 if (fp
->ipend
& EVT_IRPTEN
)
885 pr_notice(" Global Interrupts Disabled (IPEND[4])\n");
886 if (!(cpu_pda
[raw_smp_processor_id()].ex_imask
& (EVT_IVG13
| EVT_IVG12
| EVT_IVG11
|
887 EVT_IVG10
| EVT_IVG9
| EVT_IVG8
| EVT_IVG7
| EVT_IVTMR
)))
888 pr_notice(" Peripheral interrupts masked off\n");
889 if (!(cpu_pda
[raw_smp_processor_id()].ex_imask
& (EVT_IVG15
| EVT_IVG14
)))
890 pr_notice(" Kernel interrupts masked off\n");
891 if ((fp
->seqstat
& SEQSTAT_EXCAUSE
) == VEC_HWERR
) {
892 pr_notice(" HWERRCAUSE: 0x%lx\n",
893 (fp
->seqstat
& SEQSTAT_HWERRCAUSE
) >> 14);
895 /* If the error was from the EBIU, print it out */
896 if (bfin_read_EBIU_ERRMST() & CORE_ERROR
) {
897 pr_notice(" EBIU Error Reason : 0x%04x\n",
898 bfin_read_EBIU_ERRMST());
899 pr_notice(" EBIU Error Address : 0x%08x\n",
900 bfin_read_EBIU_ERRADD());
904 pr_notice(" EXCAUSE : 0x%lx\n",
905 fp
->seqstat
& SEQSTAT_EXCAUSE
);
906 for (i
= 2; i
<= 15 ; i
++) {
907 if (fp
->ipend
& (1 << i
)) {
909 decode_address(buf
, bfin_read32(EVT0
+ 4*i
));
910 pr_notice(" physical IVG%i asserted : %s\n", i
, buf
);
912 pr_notice(" interrupts disabled\n");
916 /* if no interrupts are going off, don't print this out */
917 if (fp
->ipend
& ~0x3F) {
918 for (i
= 0; i
< (NR_IRQS
- 1); i
++) {
919 struct irq_desc
*desc
= irq_to_desc(i
);
921 raw_spin_lock_irqsave(&desc
->lock
, flags
);
923 action
= desc
->action
;
927 decode_address(buf
, (unsigned int)action
->handler
);
928 pr_notice(" logical irq %3d mapped : %s", i
, buf
);
929 for (action
= action
->next
; action
; action
= action
->next
) {
930 decode_address(buf
, (unsigned int)action
->handler
);
931 pr_cont(", %s", buf
);
936 raw_spin_unlock_irqrestore(&desc
->lock
, flags
);
940 decode_address(buf
, fp
->rete
);
941 pr_notice(" RETE: %s\n", buf
);
942 decode_address(buf
, fp
->retn
);
943 pr_notice(" RETN: %s\n", buf
);
944 decode_address(buf
, fp
->retx
);
945 pr_notice(" RETX: %s\n", buf
);
946 decode_address(buf
, fp
->rets
);
947 pr_notice(" RETS: %s\n", buf
);
948 decode_address(buf
, fp
->pc
);
949 pr_notice(" PC : %s\n", buf
);
951 if (((long)fp
->seqstat
& SEQSTAT_EXCAUSE
) &&
952 (((long)fp
->seqstat
& SEQSTAT_EXCAUSE
) != VEC_HWERR
)) {
953 decode_address(buf
, cpu_pda
[cpu
].dcplb_fault_addr
);
954 pr_notice("DCPLB_FAULT_ADDR: %s\n", buf
);
955 decode_address(buf
, cpu_pda
[cpu
].icplb_fault_addr
);
956 pr_notice("ICPLB_FAULT_ADDR: %s\n", buf
);
959 pr_notice("PROCESSOR STATE:\n");
960 pr_notice(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
961 fp
->r0
, fp
->r1
, fp
->r2
, fp
->r3
);
962 pr_notice(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
963 fp
->r4
, fp
->r5
, fp
->r6
, fp
->r7
);
964 pr_notice(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
965 fp
->p0
, fp
->p1
, fp
->p2
, fp
->p3
);
966 pr_notice(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
967 fp
->p4
, fp
->p5
, fp
->fp
, (long)fp
);
968 pr_notice(" LB0: %08lx LT0: %08lx LC0: %08lx\n",
969 fp
->lb0
, fp
->lt0
, fp
->lc0
);
970 pr_notice(" LB1: %08lx LT1: %08lx LC1: %08lx\n",
971 fp
->lb1
, fp
->lt1
, fp
->lc1
);
972 pr_notice(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
973 fp
->b0
, fp
->l0
, fp
->m0
, fp
->i0
);
974 pr_notice(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
975 fp
->b1
, fp
->l1
, fp
->m1
, fp
->i1
);
976 pr_notice(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
977 fp
->b2
, fp
->l2
, fp
->m2
, fp
->i2
);
978 pr_notice(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
979 fp
->b3
, fp
->l3
, fp
->m3
, fp
->i3
);
980 pr_notice("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
981 fp
->a0w
, fp
->a0x
, fp
->a1w
, fp
->a1x
);
983 pr_notice("USP : %08lx ASTAT: %08lx\n",