arch/blackfin/mach-bf518/head.S

   1 /*
   2  * File:         arch/blackfin/mach-bf518/head.S
   3  * Based on:     arch/blackfin/mach-bf527/head.S
   4  * Author:       Bryan Wu <cooloney@kernel.org>
   5  *
   6  * Created:      2008
   7  * Description:  Startup code for Blackfin BF51x
   8  *
   9  * Modified:
  10  *               Copyright 2004-2008 Analog Devices Inc.
  11  *
  12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, see the file COPYING, or write
  26  * to the Free Software Foundation, Inc.,
  27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  28  */
  29
  30 #include <linux/linkage.h>
  31 #include <linux/init.h>
  32 #include <asm/blackfin.h>
  33 #ifdef CONFIG_BFIN_KERNEL_CLOCK
  34 #include <asm/mach-common/clocks.h>
  35 #include <asm/mach/mem_init.h>
  36 #endif
  37
  38 .section .l1.text
  39 #ifdef CONFIG_BFIN_KERNEL_CLOCK
  40 ENTRY(_start_dma_code)
  41
  42         /* Enable PHY CLK buffer output */
  43         p0.h = hi(VR_CTL);
  44         p0.l = lo(VR_CTL);
  45         r0.l = w[p0];
  46         bitset(r0, 14);
  47         w[p0] = r0.l;
  48         ssync;
  49
  50         p0.h = hi(SIC_IWR0);
  51         p0.l = lo(SIC_IWR0);
  52         r0.l = 0x1;
  53         r0.h = 0x0;
  54         [p0] = r0;
  55         ssync;
  56
  57         /*
  58          *  Set PLL_CTL
  59          *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
  60          *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
  61          *   - [7]     = output delay (add 200ps of delay to mem signals)
  62          *   - [6]     = input delay (add 200ps of input delay to mem signals)
  63          *   - [5]     = PDWN      : 1=All Clocks off
  64          *   - [3]     = STOPCK    : 1=Core Clock off
  65          *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
  66          *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
  67          *   all other bits set to zero
  68          */
  69
  70         p0.h = hi(PLL_LOCKCNT);
  71         p0.l = lo(PLL_LOCKCNT);
  72         r0 = 0x300(Z);
  73         w[p0] = r0.l;
  74         ssync;
  75
  76         P2.H = hi(EBIU_SDGCTL);
  77         P2.L = lo(EBIU_SDGCTL);
  78         R0 = [P2];
  79         BITSET (R0, 24);
  80         [P2] = R0;
  81         ssync;
  82
  83         r0 = CONFIG_VCO_MULT & 63;       /* Load the VCO multiplier         */
  84         r0 = r0 << 9;                    /* Shift it over,                  */
  85         r1 = CLKIN_HALF;                 /* Do we need to divide CLKIN by 2?*/
  86         r0 = r1 | r0;
  87         r1 = PLL_BYPASS;                 /* Bypass the PLL?                 */
  88         r1 = r1 << 8;                    /* Shift it over                   */
  89         r0 = r1 | r0;                    /* add them all together           */
  90 #ifdef ANOMALY_05000265
  91         BITSET(r0, 15);                  /* Add 250 mV of hysteresis to SPORT input pins */
  92 #endif
  93
  94         p0.h = hi(PLL_CTL);
  95         p0.l = lo(PLL_CTL);              /* Load the address                */
  96         cli r2;                          /* Disable interrupts              */
  97         ssync;
  98         w[p0] = r0.l;                    /* Set the value                   */
  99         idle;                            /* Wait for the PLL to stablize    */
 100         sti r2;                          /* Enable interrupts               */
 101
 102 .Lcheck_again:
 103         p0.h = hi(PLL_STAT);
 104         p0.l = lo(PLL_STAT);
 105         R0 = W[P0](Z);
 106         CC = BITTST(R0,5);
 107         if ! CC jump .Lcheck_again;
 108
 109         /* Configure SCLK & CCLK Dividers */
 110         r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
 111         p0.h = hi(PLL_DIV);
 112         p0.l = lo(PLL_DIV);
 113         w[p0] = r0.l;
 114         ssync;
 115
 116         p0.l = lo(EBIU_SDRRC);
 117         p0.h = hi(EBIU_SDRRC);
 118         r0 = mem_SDRRC;
 119         w[p0] = r0.l;
 120         ssync;
 121
 122         P2.H = hi(EBIU_SDGCTL);
 123         P2.L = lo(EBIU_SDGCTL);
 124         R0 = [P2];
 125         BITCLR (R0, 24);
 126         p0.h = hi(EBIU_SDSTAT);
 127         p0.l = lo(EBIU_SDSTAT);
 128         r2.l = w[p0];
 129         cc = bittst(r2,3);
 130         if !cc jump .Lskip;
 131         NOP;
 132         BITSET (R0, 23);
 133 .Lskip:
 134         [P2] = R0;
 135         SSYNC;
 136
 137         R0.L = lo(mem_SDGCTL);
 138         R0.H = hi(mem_SDGCTL);
 139         R1 = [p2];
 140         R1 = R1 | R0;
 141         [P2] = R1;
 142         SSYNC;
 143
 144         RTS;
 145 ENDPROC(_start_dma_code)
 146 #endif /* CONFIG_BFIN_KERNEL_CLOCK */