arch/blackfin/mach-bf527/head.S

   1 /*
   2  * File:         arch/blackfin/mach-bf527/head.S
   3  * Based on:     arch/blackfin/mach-bf533/head.S
   4  * Author:       Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
   5  *
   6  * Created:      1998
   7  * Description:  Startup code for Blackfin BF537
   8  *
   9  * Modified:
  10  *               Copyright 2004-2007 Analog Devices Inc.
  11  *
  12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, see the file COPYING, or write
  26  * to the Free Software Foundation, Inc.,
  27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  28  */
  29
  30 #include <linux/linkage.h>
  31 #include <linux/init.h>
  32 #include <asm/blackfin.h>
  33 #include <asm/trace.h>
  34
  35 #ifdef CONFIG_BFIN_KERNEL_CLOCK
  36 #include <asm/mach-common/clocks.h>
  37 #include <asm/mach/mem_init.h>
  38 #endif
  39
  40 .extern ___bss_stop
  41 .extern ___bss_start
  42 .extern _bf53x_relocate_l1_mem
  43
  44 #define INITIAL_STACK   0xFFB01000
  45
  46 __INIT
  47
  48 ENTRY(__start)
  49         /* R0: argument of command line string, passed from uboot, save it */
  50         R7 = R0;
  51         /* Enable Cycle Counter and Nesting Of Interrupts */
  52 #ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
  53         R0 = SYSCFG_SNEN;
  54 #else
  55         R0 = SYSCFG_SNEN | SYSCFG_CCEN;
  56 #endif
  57         SYSCFG = R0;
  58         R0 = 0;
  59
  60         /* Clear Out All the data and pointer Registers */
  61         R1 = R0;
  62         R2 = R0;
  63         R3 = R0;
  64         R4 = R0;
  65         R5 = R0;
  66         R6 = R0;
  67
  68         P0 = R0;
  69         P1 = R0;
  70         P2 = R0;
  71         P3 = R0;
  72         P4 = R0;
  73         P5 = R0;
  74
  75         LC0 = r0;
  76         LC1 = r0;
  77         L0 = r0;
  78         L1 = r0;
  79         L2 = r0;
  80         L3 = r0;
  81
  82         /* Clear Out All the DAG Registers */
  83         B0 = r0;
  84         B1 = r0;
  85         B2 = r0;
  86         B3 = r0;
  87
  88         I0 = r0;
  89         I1 = r0;
  90         I2 = r0;
  91         I3 = r0;
  92
  93         M0 = r0;
  94         M1 = r0;
  95         M2 = r0;
  96         M3 = r0;
  97
  98         trace_buffer_init(p0,r0);
  99         P0 = R1;
 100         R0 = R1;
 101
 102         /* Turn off the icache */
 103         p0.l = LO(IMEM_CONTROL);
 104         p0.h = HI(IMEM_CONTROL);
 105         R1 = [p0];
 106         R0 = ~ENICPLB;
 107         R0 = R0 & R1;
 108         [p0] = R0;
 109         SSYNC;
 110
 111         /* Turn off the dcache */
 112         p0.l = LO(DMEM_CONTROL);
 113         p0.h = HI(DMEM_CONTROL);
 114         R1 = [p0];
 115         R0 = ~ENDCPLB;
 116         R0 = R0 & R1;
 117         [p0] = R0;
 118         SSYNC;
 119
 120 #if defined(CONFIG_BF527)
 121         p0.h = hi(EMAC_SYSTAT);
 122         p0.l = lo(EMAC_SYSTAT);
 123         R0.h = 0xFFFF; /* Clear EMAC Interrupt Status bits */
 124         R0.l = 0xFFFF;
 125         [P0] = R0;
 126         SSYNC;
 127 #endif
 128
 129         /* Initialise UART - when booting from u-boot, the UART is not disabled
 130          * so if we dont initalize here, our serial console gets hosed */
 131         p0.h = hi(UART1_LCR);
 132         p0.l = lo(UART1_LCR);
 133         r0 = 0x0(Z);
 134         w[p0] = r0.L;   /* To enable DLL writes */
 135         ssync;
 136
 137         p0.h = hi(UART1_DLL);
 138         p0.l = lo(UART1_DLL);
 139         r0 = 0x0(Z);
 140         w[p0] = r0.L;
 141         ssync;
 142
 143         p0.h = hi(UART1_DLH);
 144         p0.l = lo(UART1_DLH);
 145         r0 = 0x00(Z);
 146         w[p0] = r0.L;
 147         ssync;
 148
 149         p0.h = hi(UART1_GCTL);
 150         p0.l = lo(UART1_GCTL);
 151         r0 = 0x0(Z);
 152         w[p0] = r0.L;   /* To enable UART clock */
 153         ssync;
 154
 155         /* Initialize stack pointer */
 156         sp.l = lo(INITIAL_STACK);
 157         sp.h = hi(INITIAL_STACK);
 158         fp = sp;
 159         usp = sp;
 160
 161 #ifdef CONFIG_EARLY_PRINTK
 162         SP += -12;
 163         call _init_early_exception_vectors;
 164         SP += 12;
 165 #endif
 166
 167         /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
 168         call _bf53x_relocate_l1_mem;
 169 #ifdef CONFIG_BFIN_KERNEL_CLOCK
 170         call _start_dma_code;
 171 #endif
 172
 173         /* Code for initializing Async memory banks */
 174
 175         p2.h = hi(EBIU_AMBCTL1);
 176         p2.l = lo(EBIU_AMBCTL1);
 177         r0.h = hi(AMBCTL1VAL);
 178         r0.l = lo(AMBCTL1VAL);
 179         [p2] = r0;
 180         ssync;
 181
 182         p2.h = hi(EBIU_AMBCTL0);
 183         p2.l = lo(EBIU_AMBCTL0);
 184         r0.h = hi(AMBCTL0VAL);
 185         r0.l = lo(AMBCTL0VAL);
 186         [p2] = r0;
 187         ssync;
 188
 189         p2.h = hi(EBIU_AMGCTL);
 190         p2.l = lo(EBIU_AMGCTL);
 191         r0 = AMGCTLVAL;
 192         w[p2] = r0;
 193         ssync;
 194
 195         /* This section keeps the processor in supervisor mode
 196          * during kernel boot.  Switches to user mode at end of boot.
 197          * See page 3-9 of Hardware Reference manual for documentation.
 198          */
 199
 200         /* EVT15 = _real_start */
 201
 202         p0.l = lo(EVT15);
 203         p0.h = hi(EVT15);
 204         p1.l = _real_start;
 205         p1.h = _real_start;
 206         [p0] = p1;
 207         csync;
 208
 209         p0.l = lo(IMASK);
 210         p0.h = hi(IMASK);
 211         p1.l = IMASK_IVG15;
 212         p1.h = 0x0;
 213         [p0] = p1;
 214         csync;
 215
 216         raise 15;
 217         p0.l = .LWAIT_HERE;
 218         p0.h = .LWAIT_HERE;
 219         reti = p0;
 220 #if ANOMALY_05000281
 221         nop; nop; nop;
 222 #endif
 223         rti;
 224
 225 .LWAIT_HERE:
 226         jump .LWAIT_HERE;
 227 ENDPROC(__start)
 228
 229 __FINIT
 230
 231 .section .l1.text
 232 #ifdef CONFIG_BFIN_KERNEL_CLOCK
 233 ENTRY(_start_dma_code)
 234
 235         /* Enable PHY CLK buffer output */
 236         p0.h = hi(VR_CTL);
 237         p0.l = lo(VR_CTL);
 238         r0.l = w[p0];
 239         bitset(r0, 14);
 240         w[p0] = r0.l;
 241         ssync;
 242
 243         p0.h = hi(SIC_IWR0);
 244         p0.l = lo(SIC_IWR0);
 245         r0.l = 0x1;
 246         r0.h = 0x0;
 247         [p0] = r0;
 248         SSYNC;
 249
 250         /*
 251          *  Set PLL_CTL
 252          *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
 253          *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
 254          *   - [7]     = output delay (add 200ps of delay to mem signals)
 255          *   - [6]     = input delay (add 200ps of input delay to mem signals)
 256          *   - [5]     = PDWN      : 1=All Clocks off
 257          *   - [3]     = STOPCK    : 1=Core Clock off
 258          *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
 259          *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
 260          *   all other bits set to zero
 261          */
 262
 263         p0.h = hi(PLL_LOCKCNT);
 264         p0.l = lo(PLL_LOCKCNT);
 265         r0 = 0x300(Z);
 266         w[p0] = r0.l;
 267         ssync;
 268
 269         P2.H = hi(EBIU_SDGCTL);
 270         P2.L = lo(EBIU_SDGCTL);
 271         R0 = [P2];
 272         BITSET (R0, 24);
 273         [P2] = R0;
 274         SSYNC;
 275
 276         r0 = CONFIG_VCO_MULT & 63;       /* Load the VCO multiplier         */
 277         r0 = r0 << 9;                    /* Shift it over,                  */
 278         r1 = CLKIN_HALF;                 /* Do we need to divide CLKIN by 2?*/
 279         r0 = r1 | r0;
 280         r1 = PLL_BYPASS;                 /* Bypass the PLL?                 */
 281         r1 = r1 << 8;                    /* Shift it over                   */
 282         r0 = r1 | r0;                    /* add them all together           */
 283
 284         p0.h = hi(PLL_CTL);
 285         p0.l = lo(PLL_CTL);              /* Load the address                */
 286         cli r2;                          /* Disable interrupts              */
 287         ssync;
 288         w[p0] = r0.l;                    /* Set the value                   */
 289         idle;                            /* Wait for the PLL to stablize    */
 290         sti r2;                          /* Enable interrupts               */
 291
 292 .Lcheck_again:
 293         p0.h = hi(PLL_STAT);
 294         p0.l = lo(PLL_STAT);
 295         R0 = W[P0](Z);
 296         CC = BITTST(R0,5);
 297         if ! CC jump .Lcheck_again;
 298
 299         /* Configure SCLK & CCLK Dividers */
 300         r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
 301         p0.h = hi(PLL_DIV);
 302         p0.l = lo(PLL_DIV);
 303         w[p0] = r0.l;
 304         ssync;
 305
 306         p0.l = lo(EBIU_SDRRC);
 307         p0.h = hi(EBIU_SDRRC);
 308         r0 = mem_SDRRC;
 309         w[p0] = r0.l;
 310         ssync;
 311
 312         P2.H = hi(EBIU_SDGCTL);
 313         P2.L = lo(EBIU_SDGCTL);
 314         R0 = [P2];
 315         BITCLR (R0, 24);
 316         p0.h = hi(EBIU_SDSTAT);
 317         p0.l = lo(EBIU_SDSTAT);
 318         r2.l = w[p0];
 319         cc = bittst(r2,3);
 320         if !cc jump .Lskip;
 321         NOP;
 322         BITSET (R0, 23);
 323 .Lskip:
 324         [P2] = R0;
 325         SSYNC;
 326
 327         R0.L = lo(mem_SDGCTL);
 328         R0.H = hi(mem_SDGCTL);
 329         R1 = [p2];
 330         R1 = R1 | R0;
 331         [P2] = R1;
 332         SSYNC;
 333
 334         p0.h = hi(SIC_IWR0);
 335         p0.l = lo(SIC_IWR0);
 336         r0.l = lo(IWR_ENABLE_ALL);
 337         r0.h = hi(IWR_ENABLE_ALL);
 338         [p0] = r0;
 339         SSYNC;
 340
 341         RTS;
 342 ENDPROC(_start_dma_code)
 343 #endif /* CONFIG_BFIN_KERNEL_CLOCK */