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[mirror_ubuntu-eoan-kernel.git] / arch / blackfin / mach-bf537 / boards / dnp5370.c
1 /*
2 * This is the configuration for SSV Dil/NetPC DNP/5370 board.
3 *
4 * DIL module: http://www.dilnetpc.com/dnp0086.htm
5 * SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm
6 *
7 * Copyright 2010 3ality Digital Systems
8 * Copyright 2005 National ICT Australia (NICTA)
9 * Copyright 2004-2006 Analog Devices Inc.
10 *
11 * Licensed under the GPL-2 or later.
12 */
13
14 #include <linux/device.h>
15 #include <linux/kernel.h>
16 #include <linux/platform_device.h>
17 #include <linux/io.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/mtd/plat-ram.h>
22 #include <linux/mtd/physmap.h>
23 #include <linux/spi/spi.h>
24 #include <linux/spi/flash.h>
25 #include <linux/irq.h>
26 #include <linux/interrupt.h>
27 #include <linux/i2c.h>
28 #include <linux/spi/mmc_spi.h>
29 #include <linux/phy.h>
30 #include <asm/dma.h>
31 #include <asm/bfin5xx_spi.h>
32 #include <asm/reboot.h>
33 #include <asm/portmux.h>
34 #include <asm/dpmc.h>
35
36 /*
37 * Name the Board for the /proc/cpuinfo
38 */
39 const char bfin_board_name[] = "DNP/5370";
40 #define FLASH_MAC 0x202f0000
41 #define CONFIG_MTD_PHYSMAP_LEN 0x300000
42
43 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
44 static struct platform_device rtc_device = {
45 .name = "rtc-bfin",
46 .id = -1,
47 };
48 #endif
49
50 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
51 #include <linux/bfin_mac.h>
52 #include <linux/export.h>
53 static const unsigned short bfin_mac_peripherals[] = P_RMII0;
54
55 static struct bfin_phydev_platform_data bfin_phydev_data[] = {
56 {
57 .addr = 1,
58 .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
59 },
60 };
61
62 static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
63 .phydev_number = 1,
64 .phydev_data = bfin_phydev_data,
65 .phy_mode = PHY_INTERFACE_MODE_RMII,
66 .mac_peripherals = bfin_mac_peripherals,
67 };
68
69 static struct platform_device bfin_mii_bus = {
70 .name = "bfin_mii_bus",
71 .dev = {
72 .platform_data = &bfin_mii_bus_data,
73 }
74 };
75
76 static struct platform_device bfin_mac_device = {
77 .name = "bfin_mac",
78 .dev = {
79 .platform_data = &bfin_mii_bus,
80 }
81 };
82 #endif
83
84 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
85 static struct mtd_partition asmb_flash_partitions[] = {
86 {
87 .name = "bootloader(nor)",
88 .size = 0x30000,
89 .offset = 0,
90 }, {
91 .name = "linux kernel and rootfs(nor)",
92 .size = 0x300000 - 0x30000 - 0x10000,
93 .offset = MTDPART_OFS_APPEND,
94 }, {
95 .name = "MAC address(nor)",
96 .size = 0x10000,
97 .offset = MTDPART_OFS_APPEND,
98 .mask_flags = MTD_WRITEABLE,
99 }
100 };
101
102 static struct physmap_flash_data asmb_flash_data = {
103 .width = 1,
104 .parts = asmb_flash_partitions,
105 .nr_parts = ARRAY_SIZE(asmb_flash_partitions),
106 };
107
108 static struct resource asmb_flash_resource = {
109 .start = 0x20000000,
110 .end = 0x202fffff,
111 .flags = IORESOURCE_MEM,
112 };
113
114 /* 4 MB NOR flash attached to async memory banks 0-2,
115 * therefore only 3 MB visible.
116 */
117 static struct platform_device asmb_flash_device = {
118 .name = "physmap-flash",
119 .id = 0,
120 .dev = {
121 .platform_data = &asmb_flash_data,
122 },
123 .num_resources = 1,
124 .resource = &asmb_flash_resource,
125 };
126 #endif
127
128 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
129
130 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
131
132 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
133 .enable_dma = 0, /* use no dma transfer with this chip*/
134 };
135
136 #endif
137
138 #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
139 /* This mapping is for at45db642 it has 1056 page size,
140 * partition size and offset should be page aligned
141 */
142 static struct mtd_partition bfin_spi_dataflash_partitions[] = {
143 {
144 .name = "JFFS2 dataflash(nor)",
145 #ifdef CONFIG_MTD_PAGESIZE_1024
146 .offset = 0x40000,
147 .size = 0x7C0000,
148 #else
149 .offset = 0x0,
150 .size = 0x840000,
151 #endif
152 }
153 };
154
155 static struct flash_platform_data bfin_spi_dataflash_data = {
156 .name = "mtd_dataflash",
157 .parts = bfin_spi_dataflash_partitions,
158 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
159 .type = "mtd_dataflash",
160 };
161
162 static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
163 .enable_dma = 0, /* use no dma transfer with this chip*/
164 };
165 #endif
166
167 static struct spi_board_info bfin_spi_board_info[] __initdata = {
168 /* SD/MMC card reader at SPI bus */
169 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
170 {
171 .modalias = "mmc_spi",
172 .max_speed_hz = 20000000,
173 .bus_num = 0,
174 .chip_select = 1,
175 .controller_data = &mmc_spi_chip_info,
176 .mode = SPI_MODE_3,
177 },
178 #endif
179
180 /* 8 Megabyte Atmel NOR flash chip at SPI bus */
181 #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
182 {
183 .modalias = "mtd_dataflash",
184 .max_speed_hz = 16700000,
185 .bus_num = 0,
186 .chip_select = 2,
187 .platform_data = &bfin_spi_dataflash_data,
188 .controller_data = &spi_dataflash_chip_info,
189 .mode = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */
190 },
191 #endif
192 };
193
194 /* SPI controller data */
195 /* SPI (0) */
196 static struct resource bfin_spi0_resource[] = {
197 [0] = {
198 .start = SPI0_REGBASE,
199 .end = SPI0_REGBASE + 0xFF,
200 .flags = IORESOURCE_MEM,
201 },
202 [1] = {
203 .start = CH_SPI,
204 .end = CH_SPI,
205 .flags = IORESOURCE_DMA,
206 },
207 [2] = {
208 .start = IRQ_SPI,
209 .end = IRQ_SPI,
210 .flags = IORESOURCE_IRQ,
211 },
212 };
213
214 static struct bfin5xx_spi_master spi_bfin_master_info = {
215 .num_chipselect = 8,
216 .enable_dma = 1, /* master has the ability to do dma transfer */
217 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
218 };
219
220 static struct platform_device spi_bfin_master_device = {
221 .name = "bfin-spi",
222 .id = 0, /* Bus number */
223 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
224 .resource = bfin_spi0_resource,
225 .dev = {
226 .platform_data = &spi_bfin_master_info, /* Passed to driver */
227 },
228 };
229 #endif
230
231 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
232 #ifdef CONFIG_SERIAL_BFIN_UART0
233 static struct resource bfin_uart0_resources[] = {
234 {
235 .start = UART0_THR,
236 .end = UART0_GCTL+2,
237 .flags = IORESOURCE_MEM,
238 },
239 {
240 .start = IRQ_UART0_RX,
241 .end = IRQ_UART0_RX+1,
242 .flags = IORESOURCE_IRQ,
243 },
244 {
245 .start = IRQ_UART0_ERROR,
246 .end = IRQ_UART0_ERROR,
247 .flags = IORESOURCE_IRQ,
248 },
249 {
250 .start = CH_UART0_TX,
251 .end = CH_UART0_TX,
252 .flags = IORESOURCE_DMA,
253 },
254 {
255 .start = CH_UART0_RX,
256 .end = CH_UART0_RX,
257 .flags = IORESOURCE_DMA,
258 },
259 };
260
261 static unsigned short bfin_uart0_peripherals[] = {
262 P_UART0_TX, P_UART0_RX, 0
263 };
264
265 static struct platform_device bfin_uart0_device = {
266 .name = "bfin-uart",
267 .id = 0,
268 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
269 .resource = bfin_uart0_resources,
270 .dev = {
271 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
272 },
273 };
274 #endif
275
276 #ifdef CONFIG_SERIAL_BFIN_UART1
277 static struct resource bfin_uart1_resources[] = {
278 {
279 .start = UART1_THR,
280 .end = UART1_GCTL+2,
281 .flags = IORESOURCE_MEM,
282 },
283 {
284 .start = IRQ_UART1_RX,
285 .end = IRQ_UART1_RX+1,
286 .flags = IORESOURCE_IRQ,
287 },
288 {
289 .start = IRQ_UART1_ERROR,
290 .end = IRQ_UART1_ERROR,
291 .flags = IORESOURCE_IRQ,
292 },
293 {
294 .start = CH_UART1_TX,
295 .end = CH_UART1_TX,
296 .flags = IORESOURCE_DMA,
297 },
298 {
299 .start = CH_UART1_RX,
300 .end = CH_UART1_RX,
301 .flags = IORESOURCE_DMA,
302 },
303 };
304
305 static unsigned short bfin_uart1_peripherals[] = {
306 P_UART1_TX, P_UART1_RX, 0
307 };
308
309 static struct platform_device bfin_uart1_device = {
310 .name = "bfin-uart",
311 .id = 1,
312 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
313 .resource = bfin_uart1_resources,
314 .dev = {
315 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
316 },
317 };
318 #endif
319 #endif
320
321 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
322 static struct resource bfin_twi0_resource[] = {
323 [0] = {
324 .start = TWI0_REGBASE,
325 .end = TWI0_REGBASE + 0xff,
326 .flags = IORESOURCE_MEM,
327 },
328 [1] = {
329 .start = IRQ_TWI,
330 .end = IRQ_TWI,
331 .flags = IORESOURCE_IRQ,
332 },
333 };
334
335 static struct platform_device i2c_bfin_twi_device = {
336 .name = "i2c-bfin-twi",
337 .id = 0,
338 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
339 .resource = bfin_twi0_resource,
340 };
341 #endif
342
343 static struct platform_device *dnp5370_devices[] __initdata = {
344
345 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
346 #ifdef CONFIG_SERIAL_BFIN_UART0
347 &bfin_uart0_device,
348 #endif
349 #ifdef CONFIG_SERIAL_BFIN_UART1
350 &bfin_uart1_device,
351 #endif
352 #endif
353
354 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
355 &asmb_flash_device,
356 #endif
357
358 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
359 &bfin_mii_bus,
360 &bfin_mac_device,
361 #endif
362
363 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
364 &spi_bfin_master_device,
365 #endif
366
367 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
368 &i2c_bfin_twi_device,
369 #endif
370
371 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
372 &rtc_device,
373 #endif
374
375 };
376
377 static int __init dnp5370_init(void)
378 {
379 printk(KERN_INFO "DNP/5370: registering device resources\n");
380 platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices));
381 printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n",
382 ARRAY_SIZE(bfin_spi_board_info));
383 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
384 printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC);
385 return 0;
386 }
387 arch_initcall(dnp5370_init);
388
389 /*
390 * Currently the MAC address is saved in Flash by U-Boot
391 */
392 void bfin_get_ether_addr(char *addr)
393 {
394 *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
395 *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
396 }
397 EXPORT_SYMBOL(bfin_get_ether_addr);