arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h

   1 /*
   2  * file:        include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
   3  * based on:
   4  * author:
   5  *
   6  * created:
   7  * description:
   8  *      blackfin serial driver head file
   9  * rev:
  10  *
  11  * modified:
  12  *
  13  *
  14  * bugs:         enter bugs at http://blackfin.uclinux.org/
  15  *
  16  * this program is free software; you can redistribute it and/or modify
  17  * it under the terms of the gnu general public license as published by
  18  * the free software foundation; either version 2, or (at your option)
  19  * any later version.
  20  *
  21  * this program is distributed in the hope that it will be useful,
  22  * but without any warranty; without even the implied warranty of
  23  * merchantability or fitness for a particular purpose.  see the
  24  * gnu general public license for more details.
  25  *
  26  * you should have received a copy of the gnu general public license
  27  * along with this program; see the file copying.
  28  * if not, write to the free software foundation,
  29  * 59 temple place - suite 330, boston, ma 02111-1307, usa.
  30  */
  31
  32 #include <linux/serial.h>
  33 #include <asm/dma.h>
  34 #include <asm/portmux.h>
  35
  36 #define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
  37 #define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
  38 #define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
  39 #define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
  40 #define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
  41 #define UART_GET_LSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LSR))
  42 #define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
  43 #define UART_GET_MSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MSR))
  44 #define UART_GET_MCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MCR))
  45
  46 #define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
  47 #define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
  48 #define UART_SET_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
  49 #define UART_CLEAR_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
  50 #define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
  51 #define UART_PUT_LSR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
  52 #define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
  53 #define UART_CLEAR_LSR(uart)    bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
  54 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
  55 #define UART_PUT_MCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
  56
  57 #define UART_SET_DLAB(uart)     /* MMRs not muxed on BF54x */
  58 #define UART_CLEAR_DLAB(uart)   /* MMRs not muxed on BF54x */
  59
  60 #define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
  61 #define UART_SET_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS))
  62 #define UART_CLEAR_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) & ~MRTS))
  63 #define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
  64 #define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
  65
  66 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART2_CTSRTS)
  67 # define CONFIG_SERIAL_BFIN_CTSRTS
  68
  69 # ifndef CONFIG_UART0_CTS_PIN
  70 #  define CONFIG_UART0_CTS_PIN -1
  71 # endif
  72
  73 # ifndef CONFIG_UART0_RTS_PIN
  74 #  define CONFIG_UART0_RTS_PIN -1
  75 # endif
  76
  77 # ifndef CONFIG_UART2_CTS_PIN
  78 #  define CONFIG_UART2_CTS_PIN -1
  79 # endif
  80
  81 # ifndef CONFIG_UART2_RTS_PIN
  82 #  define CONFIG_UART2_RTS_PIN -1
  83 # endif
  84 #endif
  85
  86 #define BFIN_UART_TX_FIFO_SIZE  2
  87
  88 /*
  89  * The pin configuration is different from schematic
  90  */
  91 struct bfin_serial_port {
  92         struct uart_port        port;
  93         unsigned int            old_status;
  94 #ifdef CONFIG_SERIAL_BFIN_DMA
  95         int                     tx_done;
  96         int                     tx_count;
  97         struct circ_buf         rx_dma_buf;
  98         struct timer_list       rx_dma_timer;
  99         int                     rx_dma_nrows;
 100         unsigned int            tx_dma_channel;
 101         unsigned int            rx_dma_channel;
 102         struct work_struct      tx_dma_workqueue;
 103 #endif
 104 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 105         struct timer_list       cts_timer;
 106         int             cts_pin;
 107         int             rts_pin;
 108 #endif
 109 };
 110
 111 struct bfin_serial_res {
 112         unsigned long   uart_base_addr;
 113         int             uart_irq;
 114 #ifdef CONFIG_SERIAL_BFIN_DMA
 115         unsigned int    uart_tx_dma_channel;
 116         unsigned int    uart_rx_dma_channel;
 117 #endif
 118 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 119         int     uart_cts_pin;
 120         int     uart_rts_pin;
 121 #endif
 122 };
 123
 124 struct bfin_serial_res bfin_serial_resource[] = {
 125 #ifdef CONFIG_SERIAL_BFIN_UART0
 126         {
 127         0xFFC00400,
 128         IRQ_UART0_RX,
 129 #ifdef CONFIG_SERIAL_BFIN_DMA
 130         CH_UART0_TX,
 131         CH_UART0_RX,
 132 #endif
 133 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 134         CONFIG_UART0_CTS_PIN,
 135         CONFIG_UART0_RTS_PIN,
 136 #endif
 137         },
 138 #endif
 139 #ifdef CONFIG_SERIAL_BFIN_UART1
 140         {
 141         0xFFC02000,
 142         IRQ_UART1_RX,
 143 #ifdef CONFIG_SERIAL_BFIN_DMA
 144         CH_UART1_TX,
 145         CH_UART1_RX,
 146 #endif
 147 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 148         0,
 149         0,
 150 #endif
 151         },
 152 #endif
 153 #ifdef CONFIG_SERIAL_BFIN_UART2
 154         {
 155         0xFFC02100,
 156         IRQ_UART2_RX,
 157 #ifdef CONFIG_SERIAL_BFIN_DMA
 158         CH_UART2_TX,
 159         CH_UART2_RX,
 160 #endif
 161 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 162         CONFIG_UART2_CTS_PIN,
 163         CONFIG_UART2_RTS_PIN,
 164 #endif
 165         },
 166 #endif
 167 #ifdef CONFIG_SERIAL_BFIN_UART3
 168         {
 169         0xFFC03100,
 170         IRQ_UART3_RX,
 171 #ifdef CONFIG_SERIAL_BFIN_DMA
 172         CH_UART3_TX,
 173         CH_UART3_RX,
 174 #endif
 175 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 176         0,
 177         0,
 178 #endif
 179         },
 180 #endif
 181 };
 182
 183 #define DRIVER_NAME "bfin-uart"
 184
 185 static void bfin_serial_hw_init(struct bfin_serial_port *uart)
 186 {
 187 #ifdef CONFIG_SERIAL_BFIN_UART0
 188         peripheral_request(P_UART0_TX, DRIVER_NAME);
 189         peripheral_request(P_UART0_RX, DRIVER_NAME);
 190 #endif
 191
 192 #ifdef CONFIG_SERIAL_BFIN_UART1
 193         peripheral_request(P_UART1_TX, DRIVER_NAME);
 194         peripheral_request(P_UART1_RX, DRIVER_NAME);
 195
 196 #ifdef CONFIG_BFIN_UART1_CTSRTS
 197         peripheral_request(P_UART1_RTS, DRIVER_NAME);
 198         peripheral_request(P_UART1_CTS, DRIVER_NAME);
 199 #endif
 200 #endif
 201
 202 #ifdef CONFIG_SERIAL_BFIN_UART2
 203         peripheral_request(P_UART2_TX, DRIVER_NAME);
 204         peripheral_request(P_UART2_RX, DRIVER_NAME);
 205 #endif
 206
 207 #ifdef CONFIG_SERIAL_BFIN_UART3
 208         peripheral_request(P_UART3_TX, DRIVER_NAME);
 209         peripheral_request(P_UART3_RX, DRIVER_NAME);
 210
 211 #ifdef CONFIG_BFIN_UART3_CTSRTS
 212         peripheral_request(P_UART3_RTS, DRIVER_NAME);
 213         peripheral_request(P_UART3_CTS, DRIVER_NAME);
 214 #endif
 215 #endif
 216         SSYNC();
 217 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 218         if (uart->cts_pin >= 0) {
 219                 gpio_request(uart->cts_pin, DRIVER_NAME);
 220                 gpio_direction_input(uart->cts_pin);
 221         }
 222
 223         if (uart->rts_pin >= 0) {
 224                 gpio_request(uart->rts_pin, DRIVER_NAME);
 225                 gpio_direction_output(uart->rts_pin, 0);
 226         }
 227 #endif
 228 }