arch/blackfin/mach-bf561/Kconfig

   1 # SPDX-License-Identifier: GPL-2.0
   2 if (BF561)
   3
   4 source "arch/blackfin/mach-bf561/boards/Kconfig"
   5
   6 menu "BF561 Specific Configuration"
   7
   8 if (!SMP)
   9
  10 comment "Core B Support"
  11
  12 config BF561_COREB
  13         bool "Enable Core B loader"
  14         default y
  15
  16 endif
  17
  18 comment "Interrupt Priority Assignment"
  19
  20 menu "Priority"
  21
  22 config IRQ_PLL_WAKEUP
  23         int "PLL Wakeup Interrupt"
  24         default 7
  25 config IRQ_DMA1_ERROR
  26         int "DMA1 Error (generic)"
  27         default 7
  28 config IRQ_DMA2_ERROR
  29         int "DMA2 Error (generic)"
  30         default 7
  31 config IRQ_IMDMA_ERROR
  32         int "IMDMA Error (generic)"
  33         default 7
  34 config IRQ_PPI0_ERROR
  35         int "PPI0 Error Interrupt"
  36         default 7
  37 config IRQ_PPI1_ERROR
  38         int "PPI1 Error Interrupt"
  39         default 7
  40 config IRQ_SPORT0_ERROR
  41         int "SPORT0 Error Interrupt"
  42         default 7
  43 config IRQ_SPORT1_ERROR
  44         int "SPORT1 Error Interrupt"
  45         default 7
  46 config IRQ_SPI_ERROR
  47         int "SPI Error Interrupt"
  48         default 7
  49 config IRQ_UART_ERROR
  50         int "UART Error Interrupt"
  51         default 7
  52 config IRQ_RESERVED_ERROR
  53         int "Reserved Interrupt"
  54         default 7
  55 config IRQ_DMA1_0
  56         int "DMA1 0  Interrupt(PPI1)"
  57         default 8
  58 config IRQ_DMA1_1
  59         int "DMA1 1  Interrupt(PPI2)"
  60         default 8
  61 config IRQ_DMA1_2
  62         int "DMA1 2  Interrupt"
  63         default 8
  64 config IRQ_DMA1_3
  65         int "DMA1 3  Interrupt"
  66         default 8
  67 config IRQ_DMA1_4
  68         int "DMA1 4  Interrupt"
  69         default 8
  70 config IRQ_DMA1_5
  71         int "DMA1 5  Interrupt"
  72         default 8
  73 config IRQ_DMA1_6
  74         int "DMA1 6  Interrupt"
  75         default 8
  76 config IRQ_DMA1_7
  77         int "DMA1 7  Interrupt"
  78         default 8
  79 config IRQ_DMA1_8
  80         int "DMA1 8  Interrupt"
  81         default 8
  82 config IRQ_DMA1_9
  83         int "DMA1 9  Interrupt"
  84         default 8
  85 config IRQ_DMA1_10
  86         int "DMA1 10 Interrupt"
  87         default 8
  88 config IRQ_DMA1_11
  89         int "DMA1 11 Interrupt"
  90         default 8
  91 config IRQ_DMA2_0
  92         int "DMA2 0  (SPORT0 RX)"
  93         default 9
  94 config IRQ_DMA2_1
  95         int "DMA2 1  (SPORT0 TX)"
  96         default 9
  97 config IRQ_DMA2_2
  98         int "DMA2 2  (SPORT1 RX)"
  99         default 9
 100 config IRQ_DMA2_3
 101         int "DMA2 3  (SPORT2 TX)"
 102         default 9
 103 config IRQ_DMA2_4
 104         int "DMA2 4  (SPI)"
 105         default 9
 106 config IRQ_DMA2_5
 107         int "DMA2 5  (UART RX)"
 108         default 9
 109 config IRQ_DMA2_6
 110         int "DMA2 6  (UART TX)"
 111         default 9
 112 config IRQ_DMA2_7
 113         int "DMA2 7  Interrupt"
 114         default 9
 115 config IRQ_DMA2_8
 116         int "DMA2 8  Interrupt"
 117         default 9
 118 config IRQ_DMA2_9
 119         int "DMA2 9  Interrupt"
 120         default 9
 121 config IRQ_DMA2_10
 122         int "DMA2 10 Interrupt"
 123         default 9
 124 config IRQ_DMA2_11
 125         int "DMA2 11 Interrupt"
 126         default 9
 127 config IRQ_TIMER0
 128         int "TIMER 0  Interrupt"
 129         default 7 if TICKSOURCE_GPTMR0
 130         default 8
 131 config IRQ_TIMER1
 132         int "TIMER 1  Interrupt"
 133         default 10
 134 config IRQ_TIMER2
 135         int "TIMER 2  Interrupt"
 136         default 10
 137 config IRQ_TIMER3
 138         int "TIMER 3  Interrupt"
 139         default 10
 140 config IRQ_TIMER4
 141         int "TIMER 4  Interrupt"
 142         default 10
 143 config IRQ_TIMER5
 144         int "TIMER 5  Interrupt"
 145         default 10
 146 config IRQ_TIMER6
 147         int "TIMER 6  Interrupt"
 148         default 10
 149 config IRQ_TIMER7
 150         int "TIMER 7  Interrupt"
 151         default 10
 152 config IRQ_TIMER8
 153         int "TIMER 8  Interrupt"
 154         default 10
 155 config IRQ_TIMER9
 156         int "TIMER 9  Interrupt"
 157         default 10
 158 config IRQ_TIMER10
 159         int "TIMER 10 Interrupt"
 160         default 10
 161 config IRQ_TIMER11
 162         int "TIMER 11 Interrupt"
 163         default 10
 164 config IRQ_PROG0_INTA
 165         int "Programmable Flags0 A (8)"
 166         default 11
 167 config IRQ_PROG0_INTB
 168         int "Programmable Flags0 B (8)"
 169         default 11
 170 config IRQ_PROG1_INTA
 171         int "Programmable Flags1 A (8)"
 172         default 11
 173 config IRQ_PROG1_INTB
 174         int "Programmable Flags1 B (8)"
 175         default 11
 176 config IRQ_PROG2_INTA
 177         int "Programmable Flags2 A (8)"
 178         default 11
 179 config IRQ_PROG2_INTB
 180         int "Programmable Flags2 B (8)"
 181         default 11
 182 config IRQ_DMA1_WRRD0
 183         int "MDMA1 0 write/read INT"
 184         default 8
 185 config IRQ_DMA1_WRRD1
 186         int "MDMA1 1 write/read INT"
 187         default 8
 188 config IRQ_DMA2_WRRD0
 189         int "MDMA2 0 write/read INT"
 190         default 9
 191 config IRQ_DMA2_WRRD1
 192         int "MDMA2 1 write/read INT"
 193         default 9
 194 config IRQ_IMDMA_WRRD0
 195         int "IMDMA 0 write/read INT"
 196         default 12
 197 config IRQ_IMDMA_WRRD1
 198         int "IMDMA 1 write/read INT"
 199         default 12
 200 config IRQ_WDTIMER
 201         int "Watch Dog Timer"
 202         default 13
 203
 204         help
 205           Enter the priority numbers between 7-13 ONLY.  Others are Reserved.
 206           This applies to all the above.  It is not recommended to assign the
 207           highest priority number 7 to UART or any other device.
 208
 209 endmenu
 210
 211 endmenu
 212
 213 endif