arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h

   1 /*
   2  * file:        include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
   3  * based on:
   4  * author:
   5  *
   6  * created:
   7  * description:
   8  *      blackfin serial driver head file
   9  * rev:
  10  *
  11  * modified:
  12  *
  13  *
  14  * bugs:         enter bugs at http://blackfin.uclinux.org/
  15  *
  16  * this program is free software; you can redistribute it and/or modify
  17  * it under the terms of the gnu general public license as published by
  18  * the free software foundation; either version 2, or (at your option)
  19  * any later version.
  20  *
  21  * this program is distributed in the hope that it will be useful,
  22  * but without any warranty; without even the implied warranty of
  23  * merchantability or fitness for a particular purpose.  see the
  24  * gnu general public license for more details.
  25  *
  26  * you should have received a copy of the gnu general public license
  27  * along with this program; see the file copying.
  28  * if not, write to the free software foundation,
  29  * 59 temple place - suite 330, boston, ma 02111-1307, usa.
  30  */
  31
  32 #include <linux/serial.h>
  33 #include <asm/dma.h>
  34 #include <asm/portmux.h>
  35
  36 #define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
  37 #define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
  38 #define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
  39 #define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
  40 #define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
  41 #define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
  42 #define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
  43
  44 #define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
  45 #define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
  46 #define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
  47 #define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
  48 #define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
  49 #define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
  50 #define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
  51 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
  52
  53 #define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
  54 #define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
  55
  56 #define UART_GET_CTS(x) (!gpio_get_value(x->cts_pin))
  57 #define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
  58 #define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
  59 #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
  60 #define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
  61
  62 #ifdef CONFIG_BFIN_UART0_CTSRTS
  63 # define CONFIG_SERIAL_BFIN_CTSRTS
  64 # ifndef CONFIG_UART0_CTS_PIN
  65 #  define CONFIG_UART0_CTS_PIN -1
  66 # endif
  67 # ifndef CONFIG_UART0_RTS_PIN
  68 #  define CONFIG_UART0_RTS_PIN -1
  69 # endif
  70 #endif
  71
  72 #define BFIN_UART_TX_FIFO_SIZE  2
  73
  74 struct bfin_serial_port {
  75         struct uart_port        port;
  76         unsigned int            old_status;
  77         int                     status_irq;
  78         unsigned int lsr;
  79 #ifdef CONFIG_SERIAL_BFIN_DMA
  80         int                     tx_done;
  81         int                     tx_count;
  82         struct circ_buf         rx_dma_buf;
  83         struct timer_list       rx_dma_timer;
  84         int                     rx_dma_nrows;
  85         unsigned int            tx_dma_channel;
  86         unsigned int            rx_dma_channel;
  87         struct work_struct      tx_dma_workqueue;
  88 #else
  89 # if ANOMALY_05000363
  90         unsigned int anomaly_threshold;
  91 # endif
  92 #endif
  93 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  94         struct timer_list       cts_timer;
  95         int                     cts_pin;
  96         int                     rts_pin;
  97 #endif
  98 };
  99
 100 /* The hardware clears the LSR bits upon read, so we need to cache
 101  * some of the more fun bits in software so they don't get lost
 102  * when checking the LSR in other code paths (TX).
 103  */
 104 static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
 105 {
 106         unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
 107         uart->lsr |= (lsr & (BI|FE|PE|OE));
 108         return lsr | uart->lsr;
 109 }
 110
 111 static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
 112 {
 113         uart->lsr = 0;
 114         bfin_write16(uart->port.membase + OFFSET_LSR, -1);
 115 }
 116
 117 struct bfin_serial_res {
 118         unsigned long   uart_base_addr;
 119         int             uart_irq;
 120         int             uart_status_irq;
 121 #ifdef CONFIG_SERIAL_BFIN_DMA
 122         unsigned int    uart_tx_dma_channel;
 123         unsigned int    uart_rx_dma_channel;
 124 #endif
 125 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 126         int             uart_cts_pin;
 127         int             uart_rts_pin;
 128 #endif
 129 };
 130
 131 struct bfin_serial_res bfin_serial_resource[] = {
 132         {
 133         0xFFC00400,
 134         IRQ_UART_RX,
 135         IRQ_UART_ERROR,
 136 #ifdef CONFIG_SERIAL_BFIN_DMA
 137         CH_UART_TX,
 138         CH_UART_RX,
 139 #endif
 140 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 141         CONFIG_UART0_CTS_PIN,
 142         CONFIG_UART0_RTS_PIN,
 143 #endif
 144         }
 145 };
 146
 147 #define DRIVER_NAME "bfin-uart"