arch/blackfin/mach-bf561/include/mach/mem_map.h

   1 /*
   2  * Memory MAP
   3  * Common header file for blackfin BF561 of processors.
   4  */
   5
   6 #ifndef _MEM_MAP_561_H_
   7 #define _MEM_MAP_561_H_
   8
   9 #define COREMMR_BASE           0xFFE00000        /* Core MMRs */
  10 #define SYSMMR_BASE            0xFFC00000        /* System MMRs */
  11
  12 /* Async Memory Banks */
  13 #define ASYNC_BANK3_BASE        0x2C000000       /* Async Bank 3 */
  14 #define ASYNC_BANK3_SIZE        0x04000000      /* 64M */
  15 #define ASYNC_BANK2_BASE        0x28000000       /* Async Bank 2 */
  16 #define ASYNC_BANK2_SIZE        0x04000000      /* 64M */
  17 #define ASYNC_BANK1_BASE        0x24000000       /* Async Bank 1 */
  18 #define ASYNC_BANK1_SIZE        0x04000000      /* 64M */
  19 #define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
  20 #define ASYNC_BANK0_SIZE        0x04000000      /* 64M */
  21
  22 /* Boot ROM Memory */
  23
  24 #define BOOT_ROM_START          0xEF000000
  25 #define BOOT_ROM_LENGTH         0x800
  26
  27 /* Level 1 Memory */
  28
  29 #ifdef CONFIG_BFIN_ICACHE
  30 #define BFIN_ICACHESIZE (16*1024)
  31 #else
  32 #define BFIN_ICACHESIZE (0*1024)
  33 #endif
  34
  35 /* Memory Map for ADSP-BF561 processors */
  36
  37 #ifdef CONFIG_BF561
  38 #define COREA_L1_CODE_START       0xFFA00000
  39 #define COREA_L1_DATA_A_START     0xFF800000
  40 #define COREA_L1_DATA_B_START     0xFF900000
  41 #define COREB_L1_CODE_START       0xFF600000
  42 #define COREB_L1_DATA_A_START     0xFF400000
  43 #define COREB_L1_DATA_B_START     0xFF500000
  44
  45 #define L1_CODE_START       COREA_L1_CODE_START
  46 #define L1_DATA_A_START     COREA_L1_DATA_A_START
  47 #define L1_DATA_B_START     COREA_L1_DATA_B_START
  48
  49 #define L1_CODE_LENGTH      0x4000
  50
  51 #ifdef CONFIG_BFIN_DCACHE
  52
  53 #ifdef CONFIG_BFIN_DCACHE_BANKA
  54 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
  55 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
  56 #define L1_DATA_B_LENGTH      0x8000
  57 #define BFIN_DCACHESIZE (16*1024)
  58 #define BFIN_DSUPBANKS  1
  59 #else
  60 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
  61 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
  62 #define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
  63 #define BFIN_DCACHESIZE (32*1024)
  64 #define BFIN_DSUPBANKS  2
  65 #endif
  66
  67 #else
  68 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
  69 #define L1_DATA_A_LENGTH      0x8000
  70 #define L1_DATA_B_LENGTH      0x8000
  71 #define BFIN_DCACHESIZE (0*1024)
  72 #define BFIN_DSUPBANKS  0
  73 #endif /*CONFIG_BFIN_DCACHE*/
  74 #endif
  75
  76 /* Level 2 Memory */
  77 #define L2_START                0xFEB00000
  78 #define L2_LENGTH               0x20000
  79
  80 /* Scratch Pad Memory */
  81
  82 #define COREA_L1_SCRATCH_START  0xFFB00000
  83 #define COREB_L1_SCRATCH_START  0xFF700000
  84
  85 #define L1_SCRATCH_START        COREA_L1_SCRATCH_START
  86 #define L1_SCRATCH_LENGTH       0x1000
  87
  88 #endif                          /* _MEM_MAP_533_H_ */