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[mirror_ubuntu-artful-kernel.git] / arch / blackfin / mach-common / ints-priority.c
1 /*
2 * File: arch/blackfin/mach-common/ints-priority.c
3 * Based on:
4 * Author:
5 *
6 * Created: ?
7 * Description: Set up the interrupt priorities
8 *
9 * Modified:
10 * 1996 Roman Zippel
11 * 1999 D. Jeff Dionne <jeff@uclinux.org>
12 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl>
16 * Copyright 2004-2008 Analog Devices Inc.
17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 */
35
36 #include <linux/module.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/seq_file.h>
39 #include <linux/irq.h>
40 #ifdef CONFIG_KGDB
41 #include <linux/kgdb.h>
42 #endif
43 #include <asm/traps.h>
44 #include <asm/blackfin.h>
45 #include <asm/gpio.h>
46 #include <asm/irq_handler.h>
47
48 #ifdef BF537_FAMILY
49 # define BF537_GENERIC_ERROR_INT_DEMUX
50 #else
51 # undef BF537_GENERIC_ERROR_INT_DEMUX
52 #endif
53
54 /*
55 * NOTES:
56 * - we have separated the physical Hardware interrupt from the
57 * levels that the LINUX kernel sees (see the description in irq.h)
58 * -
59 */
60
61 /* Initialize this to an actual value to force it into the .data
62 * section so that we know it is properly initialized at entry into
63 * the kernel but before bss is initialized to zero (which is where
64 * it would live otherwise). The 0x1f magic represents the IRQs we
65 * cannot actually mask out in hardware.
66 */
67 unsigned long irq_flags = 0x1f;
68
69 /* The number of spurious interrupts */
70 atomic_t num_spurious;
71
72 #ifdef CONFIG_PM
73 unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
74 #endif
75
76 struct ivgx {
77 /* irq number for request_irq, available in mach-bf5xx/irq.h */
78 unsigned int irqno;
79 /* corresponding bit in the SIC_ISR register */
80 unsigned int isrflag;
81 } ivg_table[NR_PERI_INTS];
82
83 struct ivg_slice {
84 /* position of first irq in ivg_table for given ivg */
85 struct ivgx *ifirst;
86 struct ivgx *istop;
87 } ivg7_13[IVG13 - IVG7 + 1];
88
89
90 /*
91 * Search SIC_IAR and fill tables with the irqvalues
92 * and their positions in the SIC_ISR register.
93 */
94 static void __init search_IAR(void)
95 {
96 unsigned ivg, irq_pos = 0;
97 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
98 int irqn;
99
100 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
101
102 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
103 int iar_shift = (irqn & 7) * 4;
104 if (ivg == (0xf &
105 #ifndef CONFIG_BF52x
106 bfin_read32((unsigned long *)SIC_IAR0 +
107 (irqn >> 3)) >> iar_shift)) {
108 #else
109 bfin_read32((unsigned long *)SIC_IAR0 +
110 ((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) {
111 #endif
112 ivg_table[irq_pos].irqno = IVG7 + irqn;
113 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
114 ivg7_13[ivg].istop++;
115 irq_pos++;
116 }
117 }
118 }
119 }
120
121 /*
122 * This is for core internal IRQs
123 */
124
125 static void bfin_ack_noop(unsigned int irq)
126 {
127 /* Dummy function. */
128 }
129
130 static void bfin_core_mask_irq(unsigned int irq)
131 {
132 irq_flags &= ~(1 << irq);
133 if (!irqs_disabled())
134 local_irq_enable();
135 }
136
137 static void bfin_core_unmask_irq(unsigned int irq)
138 {
139 irq_flags |= 1 << irq;
140 /*
141 * If interrupts are enabled, IMASK must contain the same value
142 * as irq_flags. Make sure that invariant holds. If interrupts
143 * are currently disabled we need not do anything; one of the
144 * callers will take care of setting IMASK to the proper value
145 * when reenabling interrupts.
146 * local_irq_enable just does "STI irq_flags", so it's exactly
147 * what we need.
148 */
149 if (!irqs_disabled())
150 local_irq_enable();
151 return;
152 }
153
154 static void bfin_internal_mask_irq(unsigned int irq)
155 {
156 #ifdef CONFIG_BF53x
157 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
158 ~(1 << SIC_SYSIRQ(irq)));
159 #else
160 unsigned mask_bank, mask_bit;
161 mask_bank = SIC_SYSIRQ(irq) / 32;
162 mask_bit = SIC_SYSIRQ(irq) % 32;
163 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
164 ~(1 << mask_bit));
165 #endif
166 SSYNC();
167 }
168
169 static void bfin_internal_unmask_irq(unsigned int irq)
170 {
171 #ifdef CONFIG_BF53x
172 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
173 (1 << SIC_SYSIRQ(irq)));
174 #else
175 unsigned mask_bank, mask_bit;
176 mask_bank = SIC_SYSIRQ(irq) / 32;
177 mask_bit = SIC_SYSIRQ(irq) % 32;
178 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
179 (1 << mask_bit));
180 #endif
181 SSYNC();
182 }
183
184 #ifdef CONFIG_PM
185 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
186 {
187 unsigned bank, bit;
188 unsigned long flags;
189 bank = SIC_SYSIRQ(irq) / 32;
190 bit = SIC_SYSIRQ(irq) % 32;
191
192 local_irq_save(flags);
193
194 if (state)
195 bfin_sic_iwr[bank] |= (1 << bit);
196 else
197 bfin_sic_iwr[bank] &= ~(1 << bit);
198
199 local_irq_restore(flags);
200
201 return 0;
202 }
203 #endif
204
205 static struct irq_chip bfin_core_irqchip = {
206 .ack = bfin_ack_noop,
207 .mask = bfin_core_mask_irq,
208 .unmask = bfin_core_unmask_irq,
209 };
210
211 static struct irq_chip bfin_internal_irqchip = {
212 .ack = bfin_ack_noop,
213 .mask = bfin_internal_mask_irq,
214 .unmask = bfin_internal_unmask_irq,
215 .mask_ack = bfin_internal_mask_irq,
216 .disable = bfin_internal_mask_irq,
217 .enable = bfin_internal_unmask_irq,
218 #ifdef CONFIG_PM
219 .set_wake = bfin_internal_set_wake,
220 #endif
221 };
222
223 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
224 static int error_int_mask;
225
226 static void bfin_generic_error_mask_irq(unsigned int irq)
227 {
228 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
229
230 if (!error_int_mask)
231 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
232 }
233
234 static void bfin_generic_error_unmask_irq(unsigned int irq)
235 {
236 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
237 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
238 }
239
240 static struct irq_chip bfin_generic_error_irqchip = {
241 .ack = bfin_ack_noop,
242 .mask_ack = bfin_generic_error_mask_irq,
243 .mask = bfin_generic_error_mask_irq,
244 .unmask = bfin_generic_error_unmask_irq,
245 };
246
247 static void bfin_demux_error_irq(unsigned int int_err_irq,
248 struct irq_desc *inta_desc)
249 {
250 int irq = 0;
251
252 SSYNC();
253
254 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
255 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
256 irq = IRQ_MAC_ERROR;
257 else
258 #endif
259 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
260 irq = IRQ_SPORT0_ERROR;
261 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
262 irq = IRQ_SPORT1_ERROR;
263 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
264 irq = IRQ_PPI_ERROR;
265 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
266 irq = IRQ_CAN_ERROR;
267 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
268 irq = IRQ_SPI_ERROR;
269 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
270 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
271 irq = IRQ_UART0_ERROR;
272 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
273 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
274 irq = IRQ_UART1_ERROR;
275
276 if (irq) {
277 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
278 struct irq_desc *desc = irq_desc + irq;
279 desc->handle_irq(irq, desc);
280 } else {
281
282 switch (irq) {
283 case IRQ_PPI_ERROR:
284 bfin_write_PPI_STATUS(PPI_ERR_MASK);
285 break;
286 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
287 case IRQ_MAC_ERROR:
288 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
289 break;
290 #endif
291 case IRQ_SPORT0_ERROR:
292 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
293 break;
294
295 case IRQ_SPORT1_ERROR:
296 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
297 break;
298
299 case IRQ_CAN_ERROR:
300 bfin_write_CAN_GIS(CAN_ERR_MASK);
301 break;
302
303 case IRQ_SPI_ERROR:
304 bfin_write_SPI_STAT(SPI_ERR_MASK);
305 break;
306
307 default:
308 break;
309 }
310
311 pr_debug("IRQ %d:"
312 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
313 irq);
314 }
315 } else
316 printk(KERN_ERR
317 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
318 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
319 __func__, __FILE__, __LINE__);
320
321 }
322 #endif /* BF537_GENERIC_ERROR_INT_DEMUX */
323
324 #if !defined(CONFIG_BF54x)
325
326 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
327 static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
328
329 extern void bfin_gpio_irq_prepare(unsigned gpio);
330
331 static void bfin_gpio_ack_irq(unsigned int irq)
332 {
333 u16 gpionr = irq - IRQ_PF0;
334
335 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
336 set_gpio_data(gpionr, 0);
337 SSYNC();
338 }
339 }
340
341 static void bfin_gpio_mask_ack_irq(unsigned int irq)
342 {
343 u16 gpionr = irq - IRQ_PF0;
344
345 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
346 set_gpio_data(gpionr, 0);
347 SSYNC();
348 }
349
350 set_gpio_maska(gpionr, 0);
351 SSYNC();
352 }
353
354 static void bfin_gpio_mask_irq(unsigned int irq)
355 {
356 set_gpio_maska(irq - IRQ_PF0, 0);
357 SSYNC();
358 }
359
360 static void bfin_gpio_unmask_irq(unsigned int irq)
361 {
362 set_gpio_maska(irq - IRQ_PF0, 1);
363 SSYNC();
364 }
365
366 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
367 {
368 u16 gpionr = irq - IRQ_PF0;
369
370 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
371 bfin_gpio_irq_prepare(gpionr);
372
373 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
374 bfin_gpio_unmask_irq(irq);
375
376 return 0;
377 }
378
379 static void bfin_gpio_irq_shutdown(unsigned int irq)
380 {
381 bfin_gpio_mask_irq(irq);
382 gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
383 }
384
385 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
386 {
387 u16 gpionr = irq - IRQ_PF0;
388
389 if (type == IRQ_TYPE_PROBE) {
390 /* only probe unenabled GPIO interrupt lines */
391 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
392 return 0;
393 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
394 }
395
396 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
397 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
398 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
399 bfin_gpio_irq_prepare(gpionr);
400
401 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
402 } else {
403 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
404 return 0;
405 }
406
407 set_gpio_inen(gpionr, 0);
408 set_gpio_dir(gpionr, 0);
409
410 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
411 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
412 set_gpio_both(gpionr, 1);
413 else
414 set_gpio_both(gpionr, 0);
415
416 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
417 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
418 else
419 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
420
421 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
422 set_gpio_edge(gpionr, 1);
423 set_gpio_inen(gpionr, 1);
424 gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
425 set_gpio_data(gpionr, 0);
426
427 } else {
428 set_gpio_edge(gpionr, 0);
429 gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
430 set_gpio_inen(gpionr, 1);
431 }
432
433 SSYNC();
434
435 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
436 set_irq_handler(irq, handle_edge_irq);
437 else
438 set_irq_handler(irq, handle_level_irq);
439
440 return 0;
441 }
442
443 #ifdef CONFIG_PM
444 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
445 {
446 unsigned gpio = irq_to_gpio(irq);
447
448 if (state)
449 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
450 else
451 gpio_pm_wakeup_free(gpio);
452
453 return 0;
454 }
455 #endif
456
457 static struct irq_chip bfin_gpio_irqchip = {
458 .ack = bfin_gpio_ack_irq,
459 .mask = bfin_gpio_mask_irq,
460 .mask_ack = bfin_gpio_mask_ack_irq,
461 .unmask = bfin_gpio_unmask_irq,
462 .disable = bfin_gpio_mask_irq,
463 .enable = bfin_gpio_unmask_irq,
464 .set_type = bfin_gpio_irq_type,
465 .startup = bfin_gpio_irq_startup,
466 .shutdown = bfin_gpio_irq_shutdown,
467 #ifdef CONFIG_PM
468 .set_wake = bfin_gpio_set_wake,
469 #endif
470 };
471
472 static void bfin_demux_gpio_irq(unsigned int inta_irq,
473 struct irq_desc *desc)
474 {
475 unsigned int i, gpio, mask, irq, search = 0;
476
477 switch (inta_irq) {
478 #if defined(CONFIG_BF53x)
479 case IRQ_PROG_INTA:
480 irq = IRQ_PF0;
481 search = 1;
482 break;
483 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
484 case IRQ_MAC_RX:
485 irq = IRQ_PH0;
486 break;
487 # endif
488 #elif defined(CONFIG_BF52x)
489 case IRQ_PORTF_INTA:
490 irq = IRQ_PF0;
491 break;
492 case IRQ_PORTG_INTA:
493 irq = IRQ_PG0;
494 break;
495 case IRQ_PORTH_INTA:
496 irq = IRQ_PH0;
497 break;
498 #elif defined(CONFIG_BF561)
499 case IRQ_PROG0_INTA:
500 irq = IRQ_PF0;
501 break;
502 case IRQ_PROG1_INTA:
503 irq = IRQ_PF16;
504 break;
505 case IRQ_PROG2_INTA:
506 irq = IRQ_PF32;
507 break;
508 #endif
509 default:
510 BUG();
511 return;
512 }
513
514 if (search) {
515 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
516 irq += i;
517
518 mask = get_gpiop_data(i) &
519 (gpio_enabled[gpio_bank(i)] &
520 get_gpiop_maska(i));
521
522 while (mask) {
523 if (mask & 1) {
524 desc = irq_desc + irq;
525 desc->handle_irq(irq, desc);
526 }
527 irq++;
528 mask >>= 1;
529 }
530 }
531 } else {
532 gpio = irq_to_gpio(irq);
533 mask = get_gpiop_data(gpio) &
534 (gpio_enabled[gpio_bank(gpio)] &
535 get_gpiop_maska(gpio));
536
537 do {
538 if (mask & 1) {
539 desc = irq_desc + irq;
540 desc->handle_irq(irq, desc);
541 }
542 irq++;
543 mask >>= 1;
544 } while (mask);
545 }
546
547 }
548
549 #else /* CONFIG_BF54x */
550
551 #define NR_PINT_SYS_IRQS 4
552 #define NR_PINT_BITS 32
553 #define NR_PINTS 160
554 #define IRQ_NOT_AVAIL 0xFF
555
556 #define PINT_2_BANK(x) ((x) >> 5)
557 #define PINT_2_BIT(x) ((x) & 0x1F)
558 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
559
560 static unsigned char irq2pint_lut[NR_PINTS];
561 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
562
563 static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS];
564 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
565
566
567 struct pin_int_t {
568 unsigned int mask_set;
569 unsigned int mask_clear;
570 unsigned int request;
571 unsigned int assign;
572 unsigned int edge_set;
573 unsigned int edge_clear;
574 unsigned int invert_set;
575 unsigned int invert_clear;
576 unsigned int pinstate;
577 unsigned int latch;
578 };
579
580 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
581 (struct pin_int_t *)PINT0_MASK_SET,
582 (struct pin_int_t *)PINT1_MASK_SET,
583 (struct pin_int_t *)PINT2_MASK_SET,
584 (struct pin_int_t *)PINT3_MASK_SET,
585 };
586
587 extern void bfin_gpio_irq_prepare(unsigned gpio);
588
589 inline unsigned short get_irq_base(u8 bank, u8 bmap)
590 {
591
592 u16 irq_base;
593
594 if (bank < 2) { /*PA-PB */
595 irq_base = IRQ_PA0 + bmap * 16;
596 } else { /*PC-PJ */
597 irq_base = IRQ_PC0 + bmap * 16;
598 }
599
600 return irq_base;
601
602 }
603
604 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
605 void init_pint_lut(void)
606 {
607 u16 bank, bit, irq_base, bit_pos;
608 u32 pint_assign;
609 u8 bmap;
610
611 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
612
613 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
614
615 pint_assign = pint[bank]->assign;
616
617 for (bit = 0; bit < NR_PINT_BITS; bit++) {
618
619 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
620
621 irq_base = get_irq_base(bank, bmap);
622
623 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
624 bit_pos = bit + bank * NR_PINT_BITS;
625
626 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
627 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
628
629 }
630
631 }
632
633 }
634
635 static void bfin_gpio_ack_irq(unsigned int irq)
636 {
637 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
638 u32 pintbit = PINT_BIT(pint_val);
639 u8 bank = PINT_2_BANK(pint_val);
640
641 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
642 if (pint[bank]->invert_set & pintbit)
643 pint[bank]->invert_clear = pintbit;
644 else
645 pint[bank]->invert_set = pintbit;
646 }
647 pint[bank]->request = pintbit;
648
649 SSYNC();
650 }
651
652 static void bfin_gpio_mask_ack_irq(unsigned int irq)
653 {
654 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
655 u32 pintbit = PINT_BIT(pint_val);
656 u8 bank = PINT_2_BANK(pint_val);
657
658 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
659 if (pint[bank]->invert_set & pintbit)
660 pint[bank]->invert_clear = pintbit;
661 else
662 pint[bank]->invert_set = pintbit;
663 }
664
665 pint[bank]->request = pintbit;
666 pint[bank]->mask_clear = pintbit;
667 SSYNC();
668 }
669
670 static void bfin_gpio_mask_irq(unsigned int irq)
671 {
672 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
673
674 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
675 SSYNC();
676 }
677
678 static void bfin_gpio_unmask_irq(unsigned int irq)
679 {
680 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
681 u32 pintbit = PINT_BIT(pint_val);
682 u8 bank = PINT_2_BANK(pint_val);
683
684 pint[bank]->request = pintbit;
685 pint[bank]->mask_set = pintbit;
686 SSYNC();
687 }
688
689 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
690 {
691 u16 gpionr = irq_to_gpio(irq);
692 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
693
694 if (pint_val == IRQ_NOT_AVAIL) {
695 printk(KERN_ERR
696 "GPIO IRQ %d :Not in PINT Assign table "
697 "Reconfigure Interrupt to Port Assignemt\n", irq);
698 return -ENODEV;
699 }
700
701 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
702 bfin_gpio_irq_prepare(gpionr);
703
704 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
705 bfin_gpio_unmask_irq(irq);
706
707 return 0;
708 }
709
710 static void bfin_gpio_irq_shutdown(unsigned int irq)
711 {
712 u16 gpionr = irq_to_gpio(irq);
713
714 bfin_gpio_mask_irq(irq);
715 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
716 }
717
718 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
719 {
720
721 u16 gpionr = irq_to_gpio(irq);
722 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
723 u32 pintbit = PINT_BIT(pint_val);
724 u8 bank = PINT_2_BANK(pint_val);
725
726 if (pint_val == IRQ_NOT_AVAIL)
727 return -ENODEV;
728
729 if (type == IRQ_TYPE_PROBE) {
730 /* only probe unenabled GPIO interrupt lines */
731 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
732 return 0;
733 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
734 }
735
736 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
737 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
738 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
739 bfin_gpio_irq_prepare(gpionr);
740
741 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
742 } else {
743 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
744 return 0;
745 }
746
747 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
748 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
749 else
750 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
751
752 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
753 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
754
755 gpio_both_edge_triggered[bank] |= pintbit;
756
757 if (gpio_get_value(gpionr))
758 pint[bank]->invert_set = pintbit;
759 else
760 pint[bank]->invert_clear = pintbit;
761 } else {
762 gpio_both_edge_triggered[bank] &= ~pintbit;
763 }
764
765 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
766 pint[bank]->edge_set = pintbit;
767 set_irq_handler(irq, handle_edge_irq);
768 } else {
769 pint[bank]->edge_clear = pintbit;
770 set_irq_handler(irq, handle_level_irq);
771 }
772
773 SSYNC();
774
775 return 0;
776 }
777
778 #ifdef CONFIG_PM
779 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
780 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
781
782 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
783 {
784 u32 pint_irq;
785 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
786 u32 bank = PINT_2_BANK(pint_val);
787 u32 pintbit = PINT_BIT(pint_val);
788
789 switch (bank) {
790 case 0:
791 pint_irq = IRQ_PINT0;
792 break;
793 case 2:
794 pint_irq = IRQ_PINT2;
795 break;
796 case 3:
797 pint_irq = IRQ_PINT3;
798 break;
799 case 1:
800 pint_irq = IRQ_PINT1;
801 break;
802 default:
803 return -EINVAL;
804 }
805
806 bfin_internal_set_wake(pint_irq, state);
807
808 if (state)
809 pint_wakeup_masks[bank] |= pintbit;
810 else
811 pint_wakeup_masks[bank] &= ~pintbit;
812
813 return 0;
814 }
815
816 u32 bfin_pm_setup(void)
817 {
818 u32 val, i;
819
820 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
821 val = pint[i]->mask_clear;
822 pint_saved_masks[i] = val;
823 if (val ^ pint_wakeup_masks[i]) {
824 pint[i]->mask_clear = val;
825 pint[i]->mask_set = pint_wakeup_masks[i];
826 }
827 }
828
829 return 0;
830 }
831
832 void bfin_pm_restore(void)
833 {
834 u32 i, val;
835
836 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
837 val = pint_saved_masks[i];
838 if (val ^ pint_wakeup_masks[i]) {
839 pint[i]->mask_clear = pint[i]->mask_clear;
840 pint[i]->mask_set = val;
841 }
842 }
843 }
844 #endif
845
846 static struct irq_chip bfin_gpio_irqchip = {
847 .ack = bfin_gpio_ack_irq,
848 .mask = bfin_gpio_mask_irq,
849 .mask_ack = bfin_gpio_mask_ack_irq,
850 .unmask = bfin_gpio_unmask_irq,
851 .disable = bfin_gpio_mask_irq,
852 .enable = bfin_gpio_unmask_irq,
853 .set_type = bfin_gpio_irq_type,
854 .startup = bfin_gpio_irq_startup,
855 .shutdown = bfin_gpio_irq_shutdown,
856 #ifdef CONFIG_PM
857 .set_wake = bfin_gpio_set_wake,
858 #endif
859 };
860
861 static void bfin_demux_gpio_irq(unsigned int inta_irq,
862 struct irq_desc *desc)
863 {
864 u8 bank, pint_val;
865 u32 request, irq;
866
867 switch (inta_irq) {
868 case IRQ_PINT0:
869 bank = 0;
870 break;
871 case IRQ_PINT2:
872 bank = 2;
873 break;
874 case IRQ_PINT3:
875 bank = 3;
876 break;
877 case IRQ_PINT1:
878 bank = 1;
879 break;
880 default:
881 return;
882 }
883
884 pint_val = bank * NR_PINT_BITS;
885
886 request = pint[bank]->request;
887
888 while (request) {
889 if (request & 1) {
890 irq = pint2irq_lut[pint_val] + SYS_IRQS;
891 desc = irq_desc + irq;
892 desc->handle_irq(irq, desc);
893 }
894 pint_val++;
895 request >>= 1;
896 }
897
898 }
899 #endif
900
901 void __init init_exception_vectors(void)
902 {
903 SSYNC();
904
905 /* cannot program in software:
906 * evt0 - emulation (jtag)
907 * evt1 - reset
908 */
909 bfin_write_EVT2(evt_nmi);
910 bfin_write_EVT3(trap);
911 bfin_write_EVT5(evt_ivhw);
912 bfin_write_EVT6(evt_timer);
913 bfin_write_EVT7(evt_evt7);
914 bfin_write_EVT8(evt_evt8);
915 bfin_write_EVT9(evt_evt9);
916 bfin_write_EVT10(evt_evt10);
917 bfin_write_EVT11(evt_evt11);
918 bfin_write_EVT12(evt_evt12);
919 bfin_write_EVT13(evt_evt13);
920 bfin_write_EVT14(evt14_softirq);
921 bfin_write_EVT15(evt_system_call);
922 CSYNC();
923 }
924
925 /*
926 * This function should be called during kernel startup to initialize
927 * the BFin IRQ handling routines.
928 */
929 int __init init_arch_irq(void)
930 {
931 int irq;
932 unsigned long ilat = 0;
933 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
934 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
935 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
936 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
937 # ifdef CONFIG_BF54x
938 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
939 # endif
940 #else
941 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
942 #endif
943
944 local_irq_disable();
945
946 #ifdef CONFIG_BF54x
947 # ifdef CONFIG_PINTx_REASSIGN
948 pint[0]->assign = CONFIG_PINT0_ASSIGN;
949 pint[1]->assign = CONFIG_PINT1_ASSIGN;
950 pint[2]->assign = CONFIG_PINT2_ASSIGN;
951 pint[3]->assign = CONFIG_PINT3_ASSIGN;
952 # endif
953 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
954 init_pint_lut();
955 #endif
956
957 for (irq = 0; irq <= SYS_IRQS; irq++) {
958 if (irq <= IRQ_CORETMR)
959 set_irq_chip(irq, &bfin_core_irqchip);
960 else
961 set_irq_chip(irq, &bfin_internal_irqchip);
962
963 switch (irq) {
964 #if defined(CONFIG_BF53x)
965 case IRQ_PROG_INTA:
966 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
967 case IRQ_MAC_RX:
968 # endif
969 #elif defined(CONFIG_BF54x)
970 case IRQ_PINT0:
971 case IRQ_PINT1:
972 case IRQ_PINT2:
973 case IRQ_PINT3:
974 #elif defined(CONFIG_BF52x)
975 case IRQ_PORTF_INTA:
976 case IRQ_PORTG_INTA:
977 case IRQ_PORTH_INTA:
978 #elif defined(CONFIG_BF561)
979 case IRQ_PROG0_INTA:
980 case IRQ_PROG1_INTA:
981 case IRQ_PROG2_INTA:
982 #endif
983 set_irq_chained_handler(irq,
984 bfin_demux_gpio_irq);
985 break;
986 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
987 case IRQ_GENERIC_ERROR:
988 set_irq_handler(irq, bfin_demux_error_irq);
989
990 break;
991 #endif
992 default:
993 set_irq_handler(irq, handle_simple_irq);
994 break;
995 }
996 }
997
998 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
999 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1000 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1001 handle_level_irq);
1002 #endif
1003
1004 /* if configured as edge, then will be changed to do_edge_IRQ */
1005 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1006 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1007 handle_level_irq);
1008
1009
1010 bfin_write_IMASK(0);
1011 CSYNC();
1012 ilat = bfin_read_ILAT();
1013 CSYNC();
1014 bfin_write_ILAT(ilat);
1015 CSYNC();
1016
1017 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1018 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
1019 * local_irq_enable()
1020 */
1021 program_IAR();
1022 /* Therefore it's better to setup IARs before interrupts enabled */
1023 search_IAR();
1024
1025 /* Enable interrupts IVG7-15 */
1026 irq_flags = irq_flags | IMASK_IVG15 |
1027 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1028 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1029
1030 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1031 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
1032 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
1033 # ifdef CONFIG_BF54x
1034 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
1035 # endif
1036 #else
1037 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
1038 #endif
1039
1040 return 0;
1041 }
1042
1043 #ifdef CONFIG_DO_IRQ_L1
1044 __attribute__((l1_text))
1045 #endif
1046 void do_irq(int vec, struct pt_regs *fp)
1047 {
1048 if (vec == EVT_IVTMR_P) {
1049 vec = IRQ_CORETMR;
1050 } else {
1051 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1052 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1053 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1054 unsigned long sic_status[3];
1055
1056 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1057 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1058 #ifdef CONFIG_BF54x
1059 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1060 #endif
1061 for (;; ivg++) {
1062 if (ivg >= ivg_stop) {
1063 atomic_inc(&num_spurious);
1064 return;
1065 }
1066 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1067 break;
1068 }
1069 #else
1070 unsigned long sic_status;
1071
1072 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1073
1074 for (;; ivg++) {
1075 if (ivg >= ivg_stop) {
1076 atomic_inc(&num_spurious);
1077 return;
1078 } else if (sic_status & ivg->isrflag)
1079 break;
1080 }
1081 #endif
1082 vec = ivg->irqno;
1083 }
1084 asm_do_IRQ(vec, fp);
1085
1086 #ifdef CONFIG_KGDB
1087 kgdb_process_breakpoint();
1088 #endif
1089 }
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