arch/blackfin/mach-common/pm.c

   1 /*
   2  * Blackfin power management
   3  *
   4  * Copyright 2006-2009 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2
   7  * based on arm/mach-omap/pm.c
   8  *    Copyright 2001, Cliff Brake <cbrake@accelent.com> and others
   9  */
  10
  11 #include <linux/suspend.h>
  12 #include <linux/sched.h>
  13 #include <linux/proc_fs.h>
  14 #include <linux/slab.h>
  15 #include <linux/io.h>
  16 #include <linux/irq.h>
  17
  18 #include <asm/cplb.h>
  19 #include <asm/gpio.h>
  20 #include <asm/dma.h>
  21 #include <asm/dpmc.h>
  22
  23 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H
  24 #define WAKEUP_TYPE     PM_WAKE_HIGH
  25 #endif
  26
  27 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_L
  28 #define WAKEUP_TYPE     PM_WAKE_LOW
  29 #endif
  30
  31 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_F
  32 #define WAKEUP_TYPE     PM_WAKE_FALLING
  33 #endif
  34
  35 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_R
  36 #define WAKEUP_TYPE     PM_WAKE_RISING
  37 #endif
  38
  39 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_B
  40 #define WAKEUP_TYPE     PM_WAKE_BOTH_EDGES
  41 #endif
  42
  43
  44 void bfin_pm_suspend_standby_enter(void)
  45 {
  46         unsigned long flags;
  47
  48 #ifdef CONFIG_PM_WAKEUP_BY_GPIO
  49         gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE);
  50 #endif
  51
  52         local_irq_save_hw(flags);
  53         bfin_pm_standby_setup();
  54
  55 #ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
  56         sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
  57 #else
  58         sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
  59 #endif
  60
  61         bfin_pm_standby_restore();
  62
  63 #ifdef SIC_IWR0
  64         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
  65 # ifdef SIC_IWR1
  66         /* BF52x system reset does not properly reset SIC_IWR1 which
  67          * will screw up the bootrom as it relies on MDMA0/1 waking it
  68          * up from IDLE instructions.  See this report for more info:
  69          * http://blackfin.uclinux.org/gf/tracker/4323
  70          */
  71         if (ANOMALY_05000435)
  72                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
  73         else
  74                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
  75 # endif
  76 # ifdef SIC_IWR2
  77         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
  78 # endif
  79 #else
  80         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
  81 #endif
  82
  83         local_irq_restore_hw(flags);
  84 }
  85
  86 int bf53x_suspend_l1_mem(unsigned char *memptr)
  87 {
  88         dma_memcpy(memptr, (const void *) L1_CODE_START, L1_CODE_LENGTH);
  89         dma_memcpy(memptr + L1_CODE_LENGTH, (const void *) L1_DATA_A_START,
  90                         L1_DATA_A_LENGTH);
  91         dma_memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
  92                         (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
  93         memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
  94                         L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
  95                         L1_SCRATCH_LENGTH);
  96
  97         return 0;
  98 }
  99
 100 int bf53x_resume_l1_mem(unsigned char *memptr)
 101 {
 102         dma_memcpy((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
 103         dma_memcpy((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
 104                         L1_DATA_A_LENGTH);
 105         dma_memcpy((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
 106                         L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
 107         memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
 108                         L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
 109
 110         return 0;
 111 }
 112
 113 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
 114 static void flushinv_all_dcache(void)
 115 {
 116         u32 way, bank, subbank, set;
 117         u32 status, addr;
 118         u32 dmem_ctl = bfin_read_DMEM_CONTROL();
 119
 120         for (bank = 0; bank < 2; ++bank) {
 121                 if (!(dmem_ctl & (1 << (DMC1_P - bank))))
 122                         continue;
 123
 124                 for (way = 0; way < 2; ++way)
 125                         for (subbank = 0; subbank < 4; ++subbank)
 126                                 for (set = 0; set < 64; ++set) {
 127
 128                                         bfin_write_DTEST_COMMAND(
 129                                                 way << 26 |
 130                                                 bank << 23 |
 131                                                 subbank << 16 |
 132                                                 set << 5
 133                                         );
 134                                         CSYNC();
 135                                         status = bfin_read_DTEST_DATA0();
 136
 137                                         /* only worry about valid/dirty entries */
 138                                         if ((status & 0x3) != 0x3)
 139                                                 continue;
 140
 141                                         /* construct the address using the tag */
 142                                         addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
 143
 144                                         /* flush it */
 145                                         __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
 146                                 }
 147         }
 148 }
 149 #endif
 150
 151 int bfin_pm_suspend_mem_enter(void)
 152 {
 153         unsigned long flags;
 154         int wakeup, ret;
 155
 156         unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
 157                                          + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH,
 158                                           GFP_KERNEL);
 159
 160         if (memptr == NULL) {
 161                 panic("bf53x_suspend_l1_mem malloc failed");
 162                 return -ENOMEM;
 163         }
 164
 165         wakeup = bfin_read_VR_CTL() & ~FREQ;
 166         wakeup |= SCKELOW;
 167
 168 #ifdef CONFIG_PM_BFIN_WAKE_PH6
 169         wakeup |= PHYWE;
 170 #endif
 171 #ifdef CONFIG_PM_BFIN_WAKE_GP
 172         wakeup |= GPWE;
 173 #endif
 174
 175         local_irq_save_hw(flags);
 176
 177         ret = blackfin_dma_suspend();
 178
 179         if (ret) {
 180                 local_irq_restore_hw(flags);
 181                 kfree(memptr);
 182                 return ret;
 183         }
 184
 185         bfin_gpio_pm_hibernate_suspend();
 186
 187 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
 188         flushinv_all_dcache();
 189 #endif
 190         _disable_dcplb();
 191         _disable_icplb();
 192         bf53x_suspend_l1_mem(memptr);
 193
 194         do_hibernate(wakeup | vr_wakeup);       /* Goodbye */
 195
 196         bf53x_resume_l1_mem(memptr);
 197
 198         _enable_icplb();
 199         _enable_dcplb();
 200
 201         bfin_gpio_pm_hibernate_restore();
 202         blackfin_dma_resume();
 203
 204         local_irq_restore_hw(flags);
 205         kfree(memptr);
 206
 207         return 0;
 208 }
 209
 210 /*
 211  *      bfin_pm_valid - Tell the PM core that we only support the standby sleep
 212  *                      state
 213  *      @state:         suspend state we're checking.
 214  *
 215  */
 216 static int bfin_pm_valid(suspend_state_t state)
 217 {
 218         return (state == PM_SUSPEND_STANDBY
 219 #if !(defined(BF533_FAMILY) || defined(CONFIG_BF561))
 220         /*
 221          * On BF533/2/1:
 222          * If we enter Hibernate the SCKE Pin is driven Low,
 223          * so that the SDRAM enters Self Refresh Mode.
 224          * However when the reset sequence that follows hibernate
 225          * state is executed, SCKE is driven High, taking the
 226          * SDRAM out of Self Refresh.
 227          *
 228          * If you reconfigure and access the SDRAM "very quickly",
 229          * you are likely to avoid errors, otherwise the SDRAM
 230          * start losing its contents.
 231          * An external HW workaround is possible using logic gates.
 232          */
 233         || state == PM_SUSPEND_MEM
 234 #endif
 235         );
 236 }
 237
 238 /*
 239  *      bfin_pm_enter - Actually enter a sleep state.
 240  *      @state:         State we're entering.
 241  *
 242  */
 243 static int bfin_pm_enter(suspend_state_t state)
 244 {
 245         switch (state) {
 246         case PM_SUSPEND_STANDBY:
 247                 bfin_pm_suspend_standby_enter();
 248                 break;
 249         case PM_SUSPEND_MEM:
 250                 bfin_pm_suspend_mem_enter();
 251                 break;
 252         default:
 253                 return -EINVAL;
 254         }
 255
 256         return 0;
 257 }
 258
 259 struct platform_suspend_ops bfin_pm_ops = {
 260         .enter = bfin_pm_enter,
 261         .valid  = bfin_pm_valid,
 262 };
 263
 264 static int __init bfin_pm_init(void)
 265 {
 266         suspend_set_ops(&bfin_pm_ops);
 267         return 0;
 268 }
 269
 270 __initcall(bfin_pm_init);