2 * Blackfin power management
4 * Copyright 2006-2009 Analog Devices Inc.
6 * Licensed under the GPL-2
7 * based on arm/mach-omap/pm.c
8 * Copyright 2001, Cliff Brake <cbrake@accelent.com> and others
11 #include <linux/suspend.h>
12 #include <linux/sched.h>
13 #include <linux/proc_fs.h>
14 #include <linux/slab.h>
16 #include <linux/irq.h>
23 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H
24 #define WAKEUP_TYPE PM_WAKE_HIGH
27 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_L
28 #define WAKEUP_TYPE PM_WAKE_LOW
31 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_F
32 #define WAKEUP_TYPE PM_WAKE_FALLING
35 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_R
36 #define WAKEUP_TYPE PM_WAKE_RISING
39 #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_B
40 #define WAKEUP_TYPE PM_WAKE_BOTH_EDGES
44 void bfin_pm_suspend_standby_enter(void)
48 #ifdef CONFIG_PM_WAKEUP_BY_GPIO
49 gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER
, WAKEUP_TYPE
);
52 local_irq_save_hw(flags
);
53 bfin_pm_standby_setup();
55 #ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
56 sleep_deeper(bfin_sic_iwr
[0], bfin_sic_iwr
[1], bfin_sic_iwr
[2]);
58 sleep_mode(bfin_sic_iwr
[0], bfin_sic_iwr
[1], bfin_sic_iwr
[2]);
61 bfin_pm_standby_restore();
64 bfin_write_SIC_IWR0(IWR_DISABLE_ALL
);
66 /* BF52x system reset does not properly reset SIC_IWR1 which
67 * will screw up the bootrom as it relies on MDMA0/1 waking it
68 * up from IDLE instructions. See this report for more info:
69 * http://blackfin.uclinux.org/gf/tracker/4323
72 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
74 bfin_write_SIC_IWR1(IWR_DISABLE_ALL
);
77 bfin_write_SIC_IWR2(IWR_DISABLE_ALL
);
80 bfin_write_SIC_IWR(IWR_DISABLE_ALL
);
83 local_irq_restore_hw(flags
);
86 int bf53x_suspend_l1_mem(unsigned char *memptr
)
88 dma_memcpy(memptr
, (const void *) L1_CODE_START
, L1_CODE_LENGTH
);
89 dma_memcpy(memptr
+ L1_CODE_LENGTH
, (const void *) L1_DATA_A_START
,
91 dma_memcpy(memptr
+ L1_CODE_LENGTH
+ L1_DATA_A_LENGTH
,
92 (const void *) L1_DATA_B_START
, L1_DATA_B_LENGTH
);
93 memcpy(memptr
+ L1_CODE_LENGTH
+ L1_DATA_A_LENGTH
+
94 L1_DATA_B_LENGTH
, (const void *) L1_SCRATCH_START
,
100 int bf53x_resume_l1_mem(unsigned char *memptr
)
102 dma_memcpy((void *) L1_CODE_START
, memptr
, L1_CODE_LENGTH
);
103 dma_memcpy((void *) L1_DATA_A_START
, memptr
+ L1_CODE_LENGTH
,
105 dma_memcpy((void *) L1_DATA_B_START
, memptr
+ L1_CODE_LENGTH
+
106 L1_DATA_A_LENGTH
, L1_DATA_B_LENGTH
);
107 memcpy((void *) L1_SCRATCH_START
, memptr
+ L1_CODE_LENGTH
+
108 L1_DATA_A_LENGTH
+ L1_DATA_B_LENGTH
, L1_SCRATCH_LENGTH
);
113 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
114 static void flushinv_all_dcache(void)
116 u32 way
, bank
, subbank
, set
;
118 u32 dmem_ctl
= bfin_read_DMEM_CONTROL();
120 for (bank
= 0; bank
< 2; ++bank
) {
121 if (!(dmem_ctl
& (1 << (DMC1_P
- bank
))))
124 for (way
= 0; way
< 2; ++way
)
125 for (subbank
= 0; subbank
< 4; ++subbank
)
126 for (set
= 0; set
< 64; ++set
) {
128 bfin_write_DTEST_COMMAND(
135 status
= bfin_read_DTEST_DATA0();
137 /* only worry about valid/dirty entries */
138 if ((status
& 0x3) != 0x3)
141 /* construct the address using the tag */
142 addr
= (status
& 0xFFFFC800) | (subbank
<< 12) | (set
<< 5);
145 __asm__
__volatile__("FLUSHINV[%0];" : : "a"(addr
));
151 int bfin_pm_suspend_mem_enter(void)
156 unsigned char *memptr
= kmalloc(L1_CODE_LENGTH
+ L1_DATA_A_LENGTH
157 + L1_DATA_B_LENGTH
+ L1_SCRATCH_LENGTH
,
160 if (memptr
== NULL
) {
161 panic("bf53x_suspend_l1_mem malloc failed");
165 wakeup
= bfin_read_VR_CTL() & ~FREQ
;
168 #ifdef CONFIG_PM_BFIN_WAKE_PH6
171 #ifdef CONFIG_PM_BFIN_WAKE_GP
175 local_irq_save_hw(flags
);
177 ret
= blackfin_dma_suspend();
180 local_irq_restore_hw(flags
);
185 bfin_gpio_pm_hibernate_suspend();
187 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
188 flushinv_all_dcache();
192 bf53x_suspend_l1_mem(memptr
);
194 do_hibernate(wakeup
| vr_wakeup
); /* Goodbye */
196 bf53x_resume_l1_mem(memptr
);
201 bfin_gpio_pm_hibernate_restore();
202 blackfin_dma_resume();
204 local_irq_restore_hw(flags
);
211 * bfin_pm_valid - Tell the PM core that we only support the standby sleep
213 * @state: suspend state we're checking.
216 static int bfin_pm_valid(suspend_state_t state
)
218 return (state
== PM_SUSPEND_STANDBY
219 #if !(defined(BF533_FAMILY) || defined(CONFIG_BF561))
222 * If we enter Hibernate the SCKE Pin is driven Low,
223 * so that the SDRAM enters Self Refresh Mode.
224 * However when the reset sequence that follows hibernate
225 * state is executed, SCKE is driven High, taking the
226 * SDRAM out of Self Refresh.
228 * If you reconfigure and access the SDRAM "very quickly",
229 * you are likely to avoid errors, otherwise the SDRAM
230 * start losing its contents.
231 * An external HW workaround is possible using logic gates.
233 || state
== PM_SUSPEND_MEM
239 * bfin_pm_enter - Actually enter a sleep state.
240 * @state: State we're entering.
243 static int bfin_pm_enter(suspend_state_t state
)
246 case PM_SUSPEND_STANDBY
:
247 bfin_pm_suspend_standby_enter();
250 bfin_pm_suspend_mem_enter();
259 struct platform_suspend_ops bfin_pm_ops
= {
260 .enter
= bfin_pm_enter
,
261 .valid
= bfin_pm_valid
,
264 static int __init
bfin_pm_init(void)
266 suspend_set_ops(&bfin_pm_ops
);
270 __initcall(bfin_pm_init
);