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git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - arch/blackfin/mm/isram-driver.c
2 * Instruction SRAM accessor functions for the Blackfin
4 * Copyright 2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later
9 #define pr_fmt(fmt) "isram: " fmt
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/slab.h>
15 #include <linux/spinlock.h>
16 #include <linux/sched.h>
17 #include <linux/sched/debug.h>
19 #include <asm/blackfin.h>
23 * IMPORTANT WARNING ABOUT THESE FUNCTIONS
25 * The emulator will not function correctly if a write command is left in
26 * ITEST_COMMAND or DTEST_COMMAND AND access to cache memory is needed by
27 * the emulator. To avoid such problems, ensure that both ITEST_COMMAND
28 * and DTEST_COMMAND are zero when exiting these functions.
33 * On the Blackfin, L1 instruction sram (which operates at core speeds) can not
34 * be accessed by a normal core load, so we need to go through a few hoops to
36 * To try to make it easier - we export a memcpy interface, where either src or
37 * dest can be in this special L1 memory area.
38 * The low level read/write functions should not be exposed to the rest of the
39 * kernel, since they operate on 64-bit data, and need specific address alignment
42 static DEFINE_SPINLOCK(dtest_lock
);
44 /* Takes a void pointer */
45 #define IADDR2DTEST(x) \
46 ({ unsigned long __addr = (unsigned long)(x); \
47 ((__addr & (1 << 11)) << (26 - 11)) | /* addr bit 11 (Way0/Way1) */ \
48 (1 << 24) | /* instruction access = 1 */ \
49 ((__addr & (1 << 15)) << (23 - 15)) | /* addr bit 15 (Data Bank) */ \
50 ((__addr & (3 << 12)) << (16 - 12)) | /* addr bits 13:12 (Subbank) */ \
51 (__addr & 0x47F8) | /* addr bits 14 & 10:3 */ \
52 (1 << 2); /* data array = 1 */ \
55 /* Takes a pointer, and returns the offset (in bits) which things should be shifted */
56 #define ADDR2OFFSET(x) ((((unsigned long)(x)) & 0x7) * 8)
58 /* Takes a pointer, determines if it is the last byte in the isram 64-bit data type */
59 #define ADDR2LAST(x) ((((unsigned long)x) & 0x7) == 0x7)
61 static void isram_write(const void *addr
, uint64_t data
)
66 if (unlikely(addr
>= (void *)(L1_CODE_START
+ L1_CODE_LENGTH
)))
69 cmd
= IADDR2DTEST(addr
) | 2; /* write */
72 * Writes to DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
73 * While in exception context - atomicity is guaranteed or double fault
75 spin_lock_irqsave(&dtest_lock
, flags
);
77 bfin_write_DTEST_DATA0(data
& 0xFFFFFFFF);
78 bfin_write_DTEST_DATA1(data
>> 32);
80 /* use the builtin, since interrupts are already turned off */
81 __builtin_bfin_csync();
82 bfin_write_DTEST_COMMAND(cmd
);
83 __builtin_bfin_csync();
85 bfin_write_DTEST_COMMAND(0);
86 __builtin_bfin_csync();
88 spin_unlock_irqrestore(&dtest_lock
, flags
);
91 static uint64_t isram_read(const void *addr
)
97 if (unlikely(addr
> (void *)(L1_CODE_START
+ L1_CODE_LENGTH
)))
100 cmd
= IADDR2DTEST(addr
) | 0; /* read */
103 * Reads of DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
104 * While in exception context - atomicity is guaranteed or double fault
106 spin_lock_irqsave(&dtest_lock
, flags
);
107 /* use the builtin, since interrupts are already turned off */
108 __builtin_bfin_csync();
109 bfin_write_DTEST_COMMAND(cmd
);
110 __builtin_bfin_csync();
111 ret
= bfin_read_DTEST_DATA0() | ((uint64_t)bfin_read_DTEST_DATA1() << 32);
113 bfin_write_DTEST_COMMAND(0);
114 __builtin_bfin_csync();
115 spin_unlock_irqrestore(&dtest_lock
, flags
);
120 static bool isram_check_addr(const void *addr
, size_t n
)
122 if ((addr
>= (void *)L1_CODE_START
) &&
123 (addr
< (void *)(L1_CODE_START
+ L1_CODE_LENGTH
))) {
124 if (unlikely((addr
+ n
) > (void *)(L1_CODE_START
+ L1_CODE_LENGTH
))) {
125 show_stack(NULL
, NULL
);
126 pr_err("copy involving %p length (%zu) too long\n", addr
, n
);
134 * The isram_memcpy() function copies n bytes from memory area src to memory area dest.
135 * The isram_memcpy() function returns a pointer to dest.
136 * Either dest or src can be in L1 instruction sram.
138 void *isram_memcpy(void *dest
, const void *src
, size_t n
)
140 uint64_t data_in
= 0, data_out
= 0;
142 bool dest_in_l1
, src_in_l1
, need_data
, put_data
;
143 unsigned char byte
, *src_byte
, *dest_byte
;
145 src_byte
= (unsigned char *)src
;
146 dest_byte
= (unsigned char *)dest
;
148 dest_in_l1
= isram_check_addr(dest
, n
);
149 src_in_l1
= isram_check_addr(src
, n
);
153 for (count
= 0; count
< n
; count
++) {
156 data_in
= isram_read(src
+ count
);
160 if (ADDR2LAST(src
+ count
))
163 byte
= (unsigned char)((data_in
>> ADDR2OFFSET(src
+ count
)) & 0xff);
166 /* src is in L2 or L3 - so just dereference*/
167 byte
= src_byte
[count
];
172 data_out
= isram_read(dest
+ count
);
176 data_out
&= ~((uint64_t)0xff << ADDR2OFFSET(dest
+ count
));
177 data_out
|= ((uint64_t)byte
<< ADDR2OFFSET(dest
+ count
));
179 if (ADDR2LAST(dest
+ count
)) {
181 isram_write(dest
+ count
, data_out
);
184 /* dest in L2 or L3 - so just dereference */
185 dest_byte
[count
] = byte
;
189 /* make sure we dump the last byte if necessary */
190 if (dest_in_l1
&& !put_data
)
191 isram_write(dest
+ count
, data_out
);
195 EXPORT_SYMBOL(isram_memcpy
);
197 #ifdef CONFIG_BFIN_ISRAM_SELF_TEST
199 static int test_len
= 0x20000;
201 static __init
void hex_dump(unsigned char *buf
, int len
)
204 pr_cont("%02x", *buf
++);
207 static __init
int isram_read_test(char *sdram
, void *l1inst
)
210 uint64_t data1
, data2
;
212 pr_info("INFO: running isram_read tests\n");
214 /* setup some different data to play with */
215 for (i
= 0; i
< test_len
; ++i
)
217 dma_memcpy(l1inst
, sdram
, test_len
);
219 /* make sure we can read the L1 inst */
220 for (i
= 0; i
< test_len
; i
+= sizeof(uint64_t)) {
221 data1
= isram_read(l1inst
+ i
);
222 memcpy(&data2
, sdram
+ i
, sizeof(data2
));
223 if (data1
!= data2
) {
224 pr_err("FAIL: isram_read(%p) returned %#llx but wanted %#llx\n",
225 l1inst
+ i
, data1
, data2
);
233 static __init
int isram_write_test(char *sdram
, void *l1inst
)
236 uint64_t data1
, data2
;
238 pr_info("INFO: running isram_write tests\n");
240 /* setup some different data to play with */
241 memset(sdram
, 0, test_len
* 2);
242 dma_memcpy(l1inst
, sdram
, test_len
);
243 for (i
= 0; i
< test_len
; ++i
)
246 /* make sure we can write the L1 inst */
247 for (i
= 0; i
< test_len
; i
+= sizeof(uint64_t)) {
248 memcpy(&data1
, sdram
+ i
, sizeof(data1
));
249 isram_write(l1inst
+ i
, data1
);
250 data2
= isram_read(l1inst
+ i
);
251 if (data1
!= data2
) {
252 pr_err("FAIL: isram_write(%p, %#llx) != %#llx\n",
253 l1inst
+ i
, data1
, data2
);
258 dma_memcpy(sdram
+ test_len
, l1inst
, test_len
);
259 if (memcmp(sdram
, sdram
+ test_len
, test_len
)) {
260 pr_err("FAIL: isram_write() did not work properly\n");
268 _isram_memcpy_test(char pattern
, void *sdram
, void *l1inst
, const char *smemcpy
,
269 void *(*fmemcpy
)(void *, const void *, size_t))
271 memset(sdram
, pattern
, test_len
);
272 fmemcpy(l1inst
, sdram
, test_len
);
273 fmemcpy(sdram
+ test_len
, l1inst
, test_len
);
274 if (memcmp(sdram
, sdram
+ test_len
, test_len
)) {
275 pr_err("FAIL: %s(%p <=> %p, %#x) failed (data is %#x)\n",
276 smemcpy
, l1inst
, sdram
, test_len
, pattern
);
281 #define _isram_memcpy_test(a, b, c, d) _isram_memcpy_test(a, b, c, #d, d)
283 static __init
int isram_memcpy_test(char *sdram
, void *l1inst
)
285 int i
, j
, thisret
, ret
= 0;
287 /* check broad isram_memcpy() */
288 pr_info("INFO: running broad isram_memcpy tests\n");
289 for (i
= 0xf; i
>= 0; --i
)
290 ret
+= _isram_memcpy_test(i
, sdram
, l1inst
, isram_memcpy
);
292 /* check read of small, unaligned, and hardware 64bit limits */
293 pr_info("INFO: running isram_memcpy (read) tests\n");
295 /* setup some different data to play with */
296 for (i
= 0; i
< test_len
; ++i
)
298 dma_memcpy(l1inst
, sdram
, test_len
);
301 for (i
= 0; i
< test_len
- 32; ++i
) {
302 unsigned char cmp
[32];
303 for (j
= 1; j
<= 32; ++j
) {
304 memset(cmp
, 0, sizeof(cmp
));
305 isram_memcpy(cmp
, l1inst
+ i
, j
);
306 if (memcmp(cmp
, sdram
+ i
, j
)) {
307 pr_err("FAIL: %p:", l1inst
+ 1);
310 hex_dump(sdram
+ i
, j
);
312 if (++thisret
> 20) {
313 pr_err("FAIL: skipping remaining series\n");
322 /* check write of small, unaligned, and hardware 64bit limits */
323 pr_info("INFO: running isram_memcpy (write) tests\n");
325 memset(sdram
+ test_len
, 0, test_len
);
326 dma_memcpy(l1inst
, sdram
+ test_len
, test_len
);
329 for (i
= 0; i
< test_len
- 32; ++i
) {
330 unsigned char cmp
[32];
331 for (j
= 1; j
<= 32; ++j
) {
332 isram_memcpy(l1inst
+ i
, sdram
+ i
, j
);
333 dma_memcpy(cmp
, l1inst
+ i
, j
);
334 if (memcmp(cmp
, sdram
+ i
, j
)) {
335 pr_err("FAIL: %p:", l1inst
+ i
);
338 hex_dump(sdram
+ i
, j
);
340 if (++thisret
> 20) {
341 pr_err("FAIL: skipping remaining series\n");
353 static __init
int isram_test_init(void)
359 /* Try to test as much of L1SRAM as possible */
362 l1inst
= l1_inst_sram_alloc(test_len
);
367 pr_warning("SKIP: could not allocate L1 inst\n");
370 pr_info("INFO: testing %#x bytes (%p - %p)\n",
371 test_len
, l1inst
, l1inst
+ test_len
);
373 sdram
= kmalloc(test_len
* 2, GFP_KERNEL
);
376 pr_warning("SKIP: could not allocate sdram\n");
380 /* sanity check initial L1 inst state */
382 pr_info("INFO: running initial dma_memcpy checks %p\n", sdram
);
383 if (_isram_memcpy_test(0xa, sdram
, l1inst
, dma_memcpy
))
385 if (_isram_memcpy_test(0x5, sdram
, l1inst
, dma_memcpy
))
389 ret
+= isram_read_test(sdram
, l1inst
);
390 ret
+= isram_write_test(sdram
, l1inst
);
391 ret
+= isram_memcpy_test(sdram
, l1inst
);
400 pr_info("PASS: all tests worked !\n");
403 late_initcall(isram_test_init
);
405 static __exit
void isram_test_exit(void)
407 /* stub to allow unloading */
409 module_exit(isram_test_exit
);