arch/cris/arch-v32/mach-a3/dram_init.S

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * DDR SDRAM initialization - alter with care
   4  * This file is intended to be included from other assembler files
   5  *
   6  * Note: This file may not modify r8 or r9 because they are used to
   7  * carry information from the decompressor to the kernel
   8  *
   9  * Copyright (C) 2005-2007 Axis Communications AB
  10  *
  11  * Authors:  Mikael Starvik <starvik@axis.com>
  12  */
  13
  14 /* Just to be certain the config file is included, we include it here
  15  * explicitly instead of depending on it being included in the file that
  16  * uses this code.
  17  */
  18
  19 #include <hwregs/asm/reg_map_asm.h>
  20 #include <hwregs/asm/ddr2_defs_asm.h>
  21
  22         ;; WARNING! The registers r8 and r9 are used as parameters carrying
  23         ;; information from the decompressor (if the kernel was compressed).
  24         ;; They should not be used in the code below.
  25
  26         ;; Refer to ddr2 MDS for initialization sequence
  27
  28         ; 2. Wait 200us
  29         move.d   10000, $r2
  30 1:      bne      1b
  31         subq     1, $r2
  32
  33         ; Start clock
  34         move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_cfg), $r0
  35         move.d   REG_STATE(ddr2, rw_phy_cfg, en, yes), $r1
  36         move.d   $r1, [$r0]
  37
  38         ; 2. Wait 200us
  39         move.d   10000, $r2
  40 1:      bne      1b
  41         subq     1, $r2
  42
  43         ; Reset phy and start calibration
  44         move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_ctrl), $r0
  45         move.d   REG_STATE(ddr2, rw_phy_ctrl, rst, yes) | \
  46                  REG_STATE(ddr2, rw_phy_ctrl, cal_rst, yes), $r1
  47         move.d   $r1, [$r0]
  48         move.d   REG_STATE(ddr2, rw_phy_ctrl, cal_start, yes), $r1
  49         move.d   $r1, [$r0]
  50
  51         ; 2. Wait 200us
  52         move.d   10000, $r2
  53 1:      bne      1b
  54         subq     1, $r2
  55
  56         ; Issue commands
  57         move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_ctrl), $r0
  58         move.d   sdram_commands_start, $r2
  59 command_loop:
  60         movu.b  [$r2+], $r1
  61         movu.w  [$r2+], $r3
  62 do_cmd:
  63         lslq     16, $r1
  64         or.d     $r3, $r1
  65         move.d   $r1, [$r0]
  66         ; 2. Wait 200us
  67         move.d   10000, $r4
  68 1:      bne      1b
  69         subq     1, $r4
  70         cmp.d    sdram_commands_end, $r2
  71         blo      command_loop
  72         nop
  73
  74         ; Set timing
  75         move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing), $r0
  76         move.d   CONFIG_ETRAX_DDR2_TIMING, $r1
  77         move.d   $r1, [$r0]
  78
  79         ; Set latency
  80         move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency), $r0
  81         move.d   CONFIG_ETRAX_DDR2_LATENCY, $r1
  82         move.d   $r1, [$r0]
  83
  84         ; Set configuration
  85         move.d   REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg), $r0
  86         move.d   CONFIG_ETRAX_DDR2_CONFIG, $r1
  87         move.d   $r1, [$r0]
  88
  89         ba after_sdram_commands
  90         nop
  91
  92 sdram_commands_start:
  93         .byte regk_ddr2_deselect
  94         .word 0
  95         .byte regk_ddr2_pre
  96         .word regk_ddr2_pre_all
  97         .byte regk_ddr2_emrs2
  98         .word 0
  99         .byte regk_ddr2_emrs3
 100         .word 0
 101         .byte regk_ddr2_emrs
 102         .word regk_ddr2_dll_en
 103         .byte regk_ddr2_mrs
 104         .word regk_ddr2_dll_rst
 105         .byte regk_ddr2_pre
 106         .word regk_ddr2_pre_all
 107         .byte regk_ddr2_ref
 108         .word 0
 109         .byte regk_ddr2_ref
 110         .word 0
 111         .byte regk_ddr2_mrs
 112         .word CONFIG_ETRAX_DDR2_MRS & 0xffff
 113         .byte regk_ddr2_emrs
 114         .word regk_ddr2_ocd_default | regk_ddr2_dll_en
 115         .byte regk_ddr2_emrs
 116         .word regk_ddr2_ocd_exit | regk_ddr2_dll_en | (CONFIG_ETRAX_DDR2_MRS >> 16)
 117 sdram_commands_end:
 118         .align 1
 119 after_sdram_commands: