1 /* Wrapper for DMA channel allocator that starts clocks etc */
3 #include <linux/kernel.h>
4 #include <linux/spinlock.h>
6 #include <hwregs/reg_map.h>
7 #include <hwregs/reg_rdwr.h>
8 #include <hwregs/marb_defs.h>
9 #include <hwregs/config_defs.h>
10 #include <hwregs/strmux_defs.h>
11 #include <linux/errno.h>
12 #include <mach/arbiter.h>
14 static char used_dma_channels
[MAX_DMA_CHANNELS
];
15 static const char *used_dma_channels_users
[MAX_DMA_CHANNELS
];
17 static DEFINE_SPINLOCK(dma_lock
);
19 int crisv32_request_dma(unsigned int dmanr
, const char *device_id
,
20 unsigned options
, unsigned int bandwidth
,
24 reg_config_rw_clk_ctrl clk_ctrl
;
25 reg_strmux_rw_cfg strmux_cfg
;
27 if (crisv32_arbiter_allocate_bandwidth(dmanr
,
28 options
& DMA_INT_MEM
?
29 INT_REGION
: EXT_REGION
,
33 spin_lock_irqsave(&dma_lock
, flags
);
35 if (used_dma_channels
[dmanr
]) {
36 spin_unlock_irqrestore(&dma_lock
, flags
);
37 if (options
& DMA_VERBOSE_ON_ERROR
) {
38 printk(KERN_ERR
"Failed to request DMA %i for %s, "
39 "already allocated by %s\n",
42 used_dma_channels_users
[dmanr
]);
44 if (options
& DMA_PANIC_ON_ERROR
)
45 panic("request_dma error!");
48 clk_ctrl
= REG_RD(config
, regi_config
, rw_clk_ctrl
);
49 strmux_cfg
= REG_RD(strmux
, regi_strmux
, rw_cfg
);
54 clk_ctrl
.dma01_eth0
= 1;
70 clk_ctrl
.dma89_strcop
= 1;
72 #if MAX_DMA_CHANNELS-1 != 9
76 spin_unlock_irqrestore(&dma_lock
, flags
);
77 if (options
& DMA_VERBOSE_ON_ERROR
) {
78 printk(KERN_ERR
"Failed to request DMA %i for %s, "
80 dmanr
, device_id
, MAX_DMA_CHANNELS
- 1);
83 if (options
& DMA_PANIC_ON_ERROR
)
84 panic("request_dma error!");
91 strmux_cfg
.dma0
= regk_strmux_eth0
;
93 strmux_cfg
.dma1
= regk_strmux_eth0
;
95 panic("Invalid DMA channel for eth0\n");
99 strmux_cfg
.dma6
= regk_strmux_eth1
;
101 strmux_cfg
.dma7
= regk_strmux_eth1
;
103 panic("Invalid DMA channel for eth1\n");
107 strmux_cfg
.dma2
= regk_strmux_iop0
;
109 strmux_cfg
.dma3
= regk_strmux_iop0
;
111 panic("Invalid DMA channel for iop0\n");
115 strmux_cfg
.dma4
= regk_strmux_iop1
;
117 strmux_cfg
.dma5
= regk_strmux_iop1
;
119 panic("Invalid DMA channel for iop1\n");
123 strmux_cfg
.dma6
= regk_strmux_ser0
;
125 strmux_cfg
.dma7
= regk_strmux_ser0
;
127 panic("Invalid DMA channel for ser0\n");
131 strmux_cfg
.dma4
= regk_strmux_ser1
;
133 strmux_cfg
.dma5
= regk_strmux_ser1
;
135 panic("Invalid DMA channel for ser1\n");
139 strmux_cfg
.dma2
= regk_strmux_ser2
;
141 strmux_cfg
.dma3
= regk_strmux_ser2
;
143 panic("Invalid DMA channel for ser2\n");
147 strmux_cfg
.dma8
= regk_strmux_ser3
;
149 strmux_cfg
.dma9
= regk_strmux_ser3
;
151 panic("Invalid DMA channel for ser3\n");
155 strmux_cfg
.dma4
= regk_strmux_sser0
;
157 strmux_cfg
.dma5
= regk_strmux_sser0
;
159 panic("Invalid DMA channel for sser0\n");
163 strmux_cfg
.dma6
= regk_strmux_sser1
;
165 strmux_cfg
.dma7
= regk_strmux_sser1
;
167 panic("Invalid DMA channel for sser1\n");
171 strmux_cfg
.dma2
= regk_strmux_ata
;
173 strmux_cfg
.dma3
= regk_strmux_ata
;
175 panic("Invalid DMA channel for ata\n");
179 strmux_cfg
.dma8
= regk_strmux_strcop
;
181 strmux_cfg
.dma9
= regk_strmux_strcop
;
183 panic("Invalid DMA channel for strp\n");
187 strmux_cfg
.dma6
= regk_strmux_ext0
;
189 panic("Invalid DMA channel for ext0\n");
193 strmux_cfg
.dma7
= regk_strmux_ext1
;
195 panic("Invalid DMA channel for ext1\n");
199 strmux_cfg
.dma2
= regk_strmux_ext2
;
201 strmux_cfg
.dma8
= regk_strmux_ext2
;
203 panic("Invalid DMA channel for ext2\n");
207 strmux_cfg
.dma3
= regk_strmux_ext3
;
209 strmux_cfg
.dma9
= regk_strmux_ext2
;
211 panic("Invalid DMA channel for ext2\n");
215 used_dma_channels
[dmanr
] = 1;
216 used_dma_channels_users
[dmanr
] = device_id
;
217 REG_WR(config
, regi_config
, rw_clk_ctrl
, clk_ctrl
);
218 REG_WR(strmux
, regi_strmux
, rw_cfg
, strmux_cfg
);
219 spin_unlock_irqrestore(&dma_lock
, flags
);
223 void crisv32_free_dma(unsigned int dmanr
)
225 spin_lock(&dma_lock
);
226 used_dma_channels
[dmanr
] = 0;
227 spin_unlock(&dma_lock
);